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? 2010 microchip technology inc. preliminary ds39979a pic18f87j72 family data sheet 80-pin, high-performance microcontrollers with dual channel afe, lcd driver and nanowatt technology downloaded from: http:///
ds39979a-page 2 preliminary ? 2010 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2010, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-314-1 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specifications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 3 analog features: dual-channel, 24-bit analog front end (afe): - 90 db sinad, -101 dbc thd (to 35th harmonic), 103 db sfdr for each channel - 10 ppm inl - differential voltage input pins - low drift internal voltage reference (12 ppm/c) - programmable data rate to 64 ksps - high-gain pga on each channel (up to 32 v/v) - phase delay compensation between channels (1 s resolution) 12-bit, 12-channel sar a/d converter: - auto-acquisition - conversion available during sleep two analog comparators programmable reference voltage for comparators charge time measurement unit (ctmu): - capacitance measurement - time measurement with 1 ns typical resolution - temperature sensing lcd driver and keypad interface features: direct lcd panel drive capability: - can drive lcd panel while in sleep mode - wake-up from interrupt up to 33 segments and 132 pixels: software selectable programmable lcd timing module: - multiple lcd timing sources available - up to four commons: static, 1/2, 1/3 or 1/4 multiplex - static, 1/2 or 1/3 bias configuration on-chip lcd boost voltage regulator for contrast control ctmu for capacitive touch sensing adc for resistive touch sensing flexible oscillator structure: external crystal and clock modes, with operation up to 48 mhz 4x phase lock loop (pll) internal oscillator block with pll: - eight user-selectable frequencies from 31.25 khz to 8 mhz secondary oscillator using timer1 at 32 khz fail-safe clock monitor (fscm): - allows for safe shutdown if peripheral clock fails low-power features: power-managed modes: - run: cpu on, peripherals on - idle: cpu off, peripherals on - sleep: cpu off, peripherals off two-speed oscillator start-up peripheral highlights: high-current sink/source 25 ma/25 ma (portb and portc) up to four external interrupts four 8-bit/16-bit timer/counter modules two capture/compare/pwm (ccp) modules master synchronous serial port (mssp) module with two modes of operation: - 3-wire/4-wire spi (supports all four spi modes) -i 2 c? master and slave mode one addressable usart module one enhanced addressable usart module: - lin/j2602 support - auto-wake-up on start bit and break character - auto-baud detect (abd) hardware real-time clock and calendar (rtcc) with clock, calendar and alarm functions special microcontroller features: 10,000 erase/write cycle flash program memory, typical flash retention 20 years, minimum self-programmable under software control word write capability for flash program memory for data eeprom emulators priority levels for interrupts 8 x 8 single-cycle hardware multiplier extended watchdog timer (wdt): - programmable period from 4 ms to 131s selectable open-drain configuration for serial communication and ccp pins for driving outputs up to 5v in-circuit serial programming? (icsp?) via two pins in-circuit debug via two pins operating voltage range: 4.5v to 5.5v ( ??? adc), 2.0v to 3.6v (digital and sar adc) 5.5v tolerant input (digital pins only) on-chip 2.5v regulator target applications: energy metering power measurement and monitoring portable instrumentation medical monitoring pic18f87j72 family 80-pin, high-performance microcontrollers with dual-channel afe, lcd driver and nanowatt technology downloaded from: http:///
pic18f87j72 family ds39979a-page 4 preliminary ? 2010 microchip technology inc. pin diagram device flash program memory (bytes) sram data memory (bytes) lcd (pixels) i/o a/d comparators ccp bor/lvd mssp a/eusart timers 8-bit/16-bit rtcc ctmu 12-bit sar (channels) 24-bit afe (channels) pic18f86j72 64k 3,923 132 51 12 2 2 2 y 1 1/1 1/3 y y pic18f87j72 128k 3,923 132 51 12 2 2 2 y 1 1/1 1/3 y y pic18f86j72 note 1: pinouts are subject to change. 2: the ccp2 pin placement depends on the setting of the ccp2mx configuration bit. 34 5 6 7 8 9 10 11 12 13 14 15 16 4847 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 12 1718 37 5049 1920 33 34 35 36 38 5857 56 55 54 53 52 51 6059 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 rd7/seg7 rd6/seg6 rd5/seg5 rd4/seg4 rd3/seg3 rd2/seg2 rd1/seg1 sv dd v ss rd0/seg0/ctpls re7/ccp2 (2) /seg31 re6/com3 re5/com2 re4/com1 re3/com0 re2/lcdbias3 re1/lcdbias2 re0/lcdbias1 rg0/lcdbias0 rg1/tx2/ck2 rg2/rx2/dt2/v lcap 1 rg3/v lcap 2 mclr rg4/seg26/rtcc v ss v ddcore /v cap rf7/an5/ss /seg25 rf6/an11/seg24/c1ina rf5/an10/cv ref /seg23/c1inb rf4/an9/seg22/c2ina rf3/an8/seg21/c2inb rf2/an7/c1out/seg20 rf1/an6/c2out/seg19 envreg a vdd a vss ra3/an3/v ref + ra2/an2/v ref - ra1/an1/seg18 ra0/an0 v ss ra5/an4/seg15 ra4/t0cki/seg14 rc1/t1osi/ccp2 (2) i/seg32 rc0/t1oso/t13cki rc6/tx1/ck1/seg27 rc7/rx1/dt1/seg28 rc2/ccp1/seg13 rc3/sck/scl/seg17 rc4/sdi/sda/seg16 rc5/sdo/seg12 rb7/kbi3/pgd v dd osc1/clki/ra7 osc2/clko/ra6 v ss rb6/kbi2/pgc rb5/kbi1/seg29 rb4/kbi0/seg11 rb3/int3/seg10/cted2 rb2/int2/seg9/cted1 rb1/int1/seg8 rb0/int0/seg30 sav dd v dd areset sdia csa scka sdoa clkia dr sv ss refin- refin+/out sav ss ch0+ ch0- ch1- ch1+ 80-pin tqfp (1) pins are tolerant up to 5.5 v dedicated 24-bit afe pins pic18f87j72 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 5 pic18f87j72 family typical application circuit: single-phase power meter lcd glass l n eeprom rs-485 rf/plc current sensor(s) (1) seg/com spi/i 2 c? ctmu ch0+ ch0- ch1+ ch1- uart1 uart2 tou c h keypad temperature sensor up to 33 seg/4 com 24-bit afe with pga pic18f87j72 (2) low-voltage detect 12-bit a/d h/w rtcc 32 khz 10 mhz note 1: generic current sense configuration shown. many circuit configurations using current and/or voltage sensing are possible, including the use of shunts, transformers or rogowski coils. 2: power metering, with the measurement of active and reactive power, is done with the power metering firmware application available through microchip technology. line voltage measurement digital i/o indicator leds anti-tamper sensors main osc downloaded from: http:///
pic18f87j72 family ds39979a-page 6 preliminary ? 2010 microchip technology inc. table of contents 1.0 device overview ............................................................................ ................................. ............................................................. 9 2.0 guidelines for getting started with pic18fj microcontrollers ................................................................ ................................... 21 3.0 oscillator configurations .................................... ............................................................... ......................................................... 25 4.0 power-managed modes ............................................ ................................................... .......... .................................................... 35 5.0 reset .......................................................................................... ................................................................................................ 43 6.0 memory organization .......................................... ................................................... ............ ........................................................ 55 7.0 flash program memory.................................................................. ...................................... ...................................................... 77 8.0 8 x 8 hardware multiplier............................................... .................................................... ......................................................... 87 9.0 interrupts .................................................................................... ................................................................................................ 89 10.0 i/o ports ....................................................................................... ........................... ................................................................. 105 11.0 timer0 module .............................................. ................................................... ............. ........................................................... 123 12.0 timer1 module .............................................. ................................................... ............. ........................................................... 127 13.0 timer2 module .............................................. ................................................... ............. ........................................................... 133 14.0 timer3 module .............................................. ................................................... ............. ........................................................... 135 15.0 real-time clock and calendar (rtcc) ...................................... .................................................. ........................................... 139 16.0 capture/compare/pwm (ccp) modules ....................................... ................................................... ....................................... 157 17.0 liquid crystal display (lcd) driver module ................................................ ................................. ............................................ 167 18.0 master synchronous serial port (mssp) module ................................. .............................................. ..................................... 195 19.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) ....................................... ........... ............. 239 20.0 addressable universal synchronous asynchr onous receiver transmitter (ausart) ......................................... ...... ............ 259 21.0 12-bit analog-to-digital converter (a/d) module ................................ ............................................ ......................................... 273 22.0 dual-channel, 24-bit analog front end (afe)..................................... ........................................... ......................................... 283 23.0 comparator module......................................... ................................................... .............. ........................................................ 293 24.0 comparator voltage reference module ................................. ................................................... .... ........................................... 299 25.0 charge time measurement unit (ctmu) .......................................... .............................................. ........................................ 303 26.0 special features of the cpu ...................................................... .......................................... .................................................... 319 27.0 instruction set summary ....................................................... ............................................. ...................................................... 333 28.0 development support............................................ ................................................... ......... ....................................................... 385 29.0 electrical characteristics ....................................................... .......................................... ......................................................... 389 30.0 packaging information............................................. ......................................................... ........................................................ 429 appendix a: revision history.......................................... ................................................... ...... .......................................................... 433 appendix b: dual-channel, 24-bit afe reference...................................... ........................................... ........................................... 434 the microchip web site .................................................................. ....................................... ............................................................ 477 customer change notification service ....................................... ................................................... . ................................................... 477 customer support ............................................... ................................................... ............. ............................................................... 477 reader response ................................................. ................................................... ............ .............................................................. 478 product identification system.................................................. ................................................................................................. .......... 479 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 7 pic18f87j72 family to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
pic18f87j72 family ds39979a-page 8 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 9 pic18f87j72 family 1.0 device overview this document contains device-specific information for the following devices: pic18f86j72 pic18f87j72 this family combines the traditional advantages of all pic18 microcontrollers C namely, high computational performance and a rich feature set C with a versatile on-chip lcd driver and a high-performance, high-accuracy analog front end. these features make the pic18f87j72 family a logical choice for many high-performance power and metering applications where price is a primary consideration. 1.1 core features 1.1.1 nanowatt technology all of the devices in the pic18f87j72 family incorporate a range of features that c an significantly reduce power consumption during operation. key items include: alternate run modes: by clocking the controller from the timer1 source or the internal rc oscillator, power consumption during code execution can be reduced by as much as 90%. multiple idle modes: the controller can also run with its cpu core disabled but the peripherals still active. in these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. on-the-fly mode switching: the power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their applications software design. 1.1.2 oscillator options and features all of the devices in the pic18f87j72 family offer six different oscillator options, allowing users a range of choices in developing application hardware. these include: two crystal modes using crystals or ceramic resonators. two external clock modes offering the option of a divide-by-4 clock output. a phase lock loop (pll) frequency multiplier, available to the external oscillator modes which allows clock speeds of up to 40 mhz. pll can also be used with the internal oscillator. an internal oscillator block which provides an 8 mhz clock (2% accuracy) and an intrc source (approximately 31 khz, stable over temperature and v dd ), as well as a range of six user-selectable clock frequencies, between 125 khz to 4 mhz, for a total of eight clock frequencies. this option frees the two oscillator pins for use as additional general purpose i/o. the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: fail-safe clock monitor: this option constantly monitors the main clock source against a reference signal provided by the internal oscillator. if a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. two-speed start-up: this option allows the internal oscillator to serve as the clock source from power-on reset, or wake-up from sleep mode, until the primary clock source is available. 1.1.3 memory options the pic18f87j72 family provides ample room for application code with 128 kbytes of code space. the flash cells for program memory are rated to last up to 10,000 erase/write cycles. data retention without refresh is conservatively estimated to be greater than 20 years. the flash program memory is readable and writable. during normal operation, the pic18f87j72 family also provides plenty of room for dynamic application data with up to 3,923 bytes of data ram. 1.1.4 extended instruction set the pic18f87j72 family implements the optional extension to the pic18 instruction set, adding 8 new instructions and an indexed addressing mode. enabled as a device configuration option, the extension has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as c. 1.1.5 easy migration regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. the consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. the pic18f87j72 family is also largely pin compatible with other pic18 families, such as the pic18f8720 and pic18f8722, the pic18f85j11, and the pic18f8490 and pic18f85j90 families of microcontrollers with lcd drivers. this allows a new dimension to the evolution of applications, allowing developers to select different price points within microchips pic18 portfolio, while maintaining a similar feature set. downloaded from: http:///
pic18f87j72 family ds39979a-page 10 preliminary ? 2010 microchip technology inc. 1.2 analog features dual-channel, 24-bit adc front end (afe): this module contains two synchronous sampling, ?? analog-to-digital (a/d) converters, plus sup- porting programmable gain amplifiers (pgas) and an internal voltage reference, to perform high-accuracy and low noise analog conversions. the afe is controlled, and its data read, through a dedicated, high-speed (20 mhz) spi interface. 12-bit a/d converter: in addition to the afe, pic18f87j72 family devices also include a stan- dard sar a/d converter with 12 independent analog inputs. the module incorporates program- mable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. charge time measurement unit (ctmu): the ctmu is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. together with other on-chip analog modules, the ctmu can precisely measure time, measure capacitance or relative changes in capacitance, or generate output pulses that are independent of the system clock. 1.3 lcd driver the on-chip lcd driver includes many features that make the integration of displays in low-power applications easier. these include an integrated volt- age regulator with charge pump that allows contrast control in software and display operation above device v dd . 1.4 other special features communications: the pic18f87j72 family incorporates a range of serial communication peripherals, including an addressable usart, a separate enhanced usart that supports lin/j2602 specification 1.2, and one master ssp module capable of both spi and i 2 c? (master and slave) modes of operation. ccp modules: all devices in the family incorporate two capture/compare/pwm (ccp) modules. up to four different time bases may be used to perform several different operations at once. extended watchdog timer (wdt): this enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. see section 29.0 electrical characteristics for time-out periods. real time clock and calendar module (rtcc): the rtcc module is intended for applications requiring that accurate time be maintained for extended periods of time with minimum to no intervention from the cpu. the module is a 100-year clock and calendar with automatic leap year detection. the range of the clock is from 00:00:00 (midnight) on january 1, 2000 to 23:59:59 on december 31, 2099. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 11 pic18f87j72 family 1.5 details on individual family members devices in the pic18f87j72 family are available in 80-pin packages. block diagrams for the two groups are shown in figure 1-1. the devices are differentiated in that pic18f86j72 devices have a flash program memory of 64 kbytes and pic18f87j72 devices memory is 128 kbytes all other features for the devices are identical. these are summarized in table 1-1. the pinouts for all devices are listed in table 1-2. table 1-1: device features for the pic18f8xj72 (80-pin devices) features pic18f86j72 pic18f87j72 operating frequency dc C 48 mhz program memory (bytes) 64k 128k program memory (instructions) 32,768 65,536 data memory (bytes) 3,923 3,923 interrupt sources 29 i/o ports ports a, b, c, d, e, f, g lcd driver (available pixels to drive) 132 (33 segs x 4 coms) timers 4 comparators 2 ctmu yes rtcc yes capture/compare/pwm modules 2 serial communications mssp, addressable usart, enhanced usart 12-bit analog-to-digital module 12 input channels dual-channel 24-bit analog front end yes resets (and delays) por, bor, reset instruction, stack full, stack underflow, mclr , wdt (pwrt, ost) instruction set 75 instructions, 83 with extended instruction set enabled packages 80-pin tqfp downloaded from: http:///
pic18f87j72 family ds39979a-page 12 preliminary ? 2010 microchip technology inc. figure 1-1: pic18f8xj72 (80-pin) block diagram instruction decode and control porta data latch data memory (2.0, 3.9 address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31-level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (96 kbytes) data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 pclatu pcu note 1: see table 1-2 for i/o port pin descriptions. 2: ra6 and ra7 are only available as digital i/o in select oscillator modes. see section 3.0 oscillator configurations for more information 3: brown-out reset and low-voltage detect functions are provided when the on-board voltage regulator is enabled. ausart comparators mssp timer3 timer2 ctmu timer1 ccp2 adc 12-bit w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 eusart rom latch lcd portc portd porte portf portg ra0:ra7 (1,2) rc0:rc7 (1) rd0:rd7 (1) re0:re1, rf1:rf7 (1) rg0:rg4 (1) portb rb0:rb7 (1) osc1/clki osc2/clko v dd , timing generation v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer bor and lvd (3) precision reference band gap intrc oscillator regulator voltage v ddcore /v cap envreg kbytes) driver 8 mhz oscillator re3:re7 (1) timer0 ccp1 rtcc dual-channel sdia afe sdoa csa dr clkia chn+ chn- sv dd sv ss areset sav dd sav ss downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 13 pic18f87j72 family table 1-2: pic18f8xj72 pi nout i/o de scriptions pin name pin number pin type buffer type description tqfp mclr 9 i st master clear (input) or programming voltage (input). this pin is an active-low reset to the device. osc1/clki/ra7 osc1 clki ra7 48 ii i/o cmos cmos ttl oscillator crystal or external clock input. oscillator crystal input. external clock source input. always associated with pin function, osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 49 oo i/o ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in ec modes, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. porta is a bidirectional i/o port. ra0/an0 ra0 an0 31 i/o i ttl analog digital i/o. analog input 0. ra1/an1/seg18 ra1 an1 seg18 30 i/o i o ttl analog analog digital i/o. analog input 1. seg18 output for lcd. ra2/an2/v ref - ra2 an2 v ref - 27 i/o ii ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 25 i/o ii ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki/seg14 ra4 t0cki seg14 34 i/o i o stst analog digital i/o. timer0 external clock input. seg14 output for lcd. ra5/an4/seg15 ra5 an4 seg15 33 i/o i o ttl analog analog digital i/o. analog input 4. seg15 output for lcd. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i2c = i 2 c/smbus compatible input od = open-drain (no p diode to v dd ) i = input o = output p= p o w e r note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j72 family ds39979a-page 14 preliminary ? 2010 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/seg30 rb0 int0 seg30 57 i/o i o ttl st analog digital i/o. external interrupt 0. seg30 output for lcd. rb1/int1/seg8 rb1 int1 seg8 56 i/o i o ttl st analog digital i/o. external interrupt 1. seg8 output for lcd. rb2/int2/seg9/ cted1 rb2 int2 cted1 seg9 55 i/o ii o ttl stst analog digital i/o. external interrupt 2. ctmu edge 1 input. seg9 output for lcd. rb3/int3/seg10/ cted2 rb3 int3 seg10 cted2 54 i/o i o i ttl st analog st digital i/o. external interrupt 3. seg10 output for lcd. ctmu edge 2 input. rb4/kbi0/seg11 rb4 kbi0 seg11 53 i/o i o ttl ttl analog digital i/o. interrupt-on-change pin. seg11 output for lcd. rb5/kbi1/seg29 rb5 kbi1 seg29 52 i/o i o ttl ttl analog digital i/o. interrupt-on-change pin. seg29 output for lcd. rb6/kbi2/pgc rb6 kbi2 pgc 51 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 46 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-2: pic18f8xj72 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i2c = i 2 c/smbus compatible input od = open-drain (no p diode to v dd ) i = input o = output p= p o w e r note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 15 pic18f87j72 family portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 37 i/o o i st st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2/ seg32 rc1 t1osi ccp2 (1) seg32 35 i/o i i/o o st cmos st analog digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm2 output. seg32 output for lcd. rc2/ccp1/seg13 rc2 ccp1 seg13 42 i/oi/o o stst analog digital i/o. capture 1 input/compare 1 output/pwm1 output. seg13 output for lcd. rc3/sck/scl/seg17 rc3 sck scl seg17 43 i/oi/o i/o o stst i2c analog digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. seg17 output for lcd. rc4/sdi/sda/seg16 rc4sdi sda seg16 44 i/o i i/o o stst i2c analog digital i/o. spi data in. i 2 c data i/o. seg16 output for lcd. rc5/sdo/seg12 rc5 sdo seg12 45 i/o oo st analog digital i/o. spi data out. seg12 output for lcd. rc6/tx1/ck1/seg27 rc6 tx1 ck1 seg27 38 i/o o i/o o st st analog digital i/o. eusart asynchronous transmit. eusart synchronous clock (see related rx1/dt1). seg27 output for lcd. rc7/rx1/dt1/seg28 rc7 rx1 dt1 seg28 39 i/o i i/o o stst st analog digital i/o. eusart asynchronous receive. eusart synchronous data (see related tx1/ck1). seg28 output for lcd. table 1-2: pic18f8xj72 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i2c = i 2 c/smbus compatible input od = open-drain (no p diode to v dd ) i = input o = output p= p o w e r note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j72 family ds39979a-page 16 preliminary ? 2010 microchip technology inc. portd is a bidirectional i/o port. rd0/seg0/ctpls rd0 seg0 ctpls 73 i/o oo st analog digital i/o. seg0 output for lcd. ctmu pulse generator output. rd1/seg1 rd1 seg1 68 i/o o st analog digital i/o. seg1 output for lcd. rd2/seg2 rd2 seg2 67 i/o o st analog digital i/o. seg2 output for lcd. rd3/seg3 rd3 seg3 66 i/o o st analog digital i/o. seg3 output for lcd. rd4/seg4 rd4 seg4 65 i/o o st analog digital i/o. seg4 output for lcd. rd5/seg5 rd5 seg5 63 i/o o st analog digital i/o. seg5 output for lcd. rd6/seg6 rd6 seg6 62 i/o o st analog digital i/o. seg6 output for lcd. rd7/seg7 rd7 seg7 61 i/o o st analog digital i/o. seg7 output for lcd. table 1-2: pic18f8xj72 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i2c = i 2 c/smbus compatible input od = open-drain (no p diode to v dd ) i = input o = output p= p o w e r note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 17 pic18f87j72 family porte is a bidirectional i/o port. re0/lcdbias1 re0 lcdbias1 4 i/o i st analog digital i/o. bias1 input for lcd. re1/lcdbias2 re1 lcdbias2 3 i/o i st analog digital i/o. bias2 input for lcd. re2/lcdbias3 re2 lcdbias3 80 i/o i st analog digital i/o. bias3 input for lcd. re3/com0 re3 com0 79 i/o o st analog digital i/o. com0 output for lcd. re4/com1 re4 com1 78 i/o o st analog digital i/o. com1 output for lcd. re5/com2 re5 com2 77 i/o o st analog digital i/o. com2 output for lcd. re6/com3 re6 com3 76 i/o o st analog digital i/o. com3 output for lcd. re7/ccp2/seg31 re7 ccp2 (2) seg31 75 i/oi/o o stst analog digital i/o. capture 2 input/compare 2 output/pwm2 output. seg31 output for lcd. table 1-2: pic18f8xj72 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i2c = i 2 c/smbus compatible input od = open-drain (no p diode to v dd ) i = input o = output p= p o w e r note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j72 family ds39979a-page 18 preliminary ? 2010 microchip technology inc. portf is a bidirectional i/o port. rf1/an6/c2out/ seg19 rf1 an6 c2out seg19 21 i/o i oo st analog analog digital i/o. analog input 6. comparator 2 output. seg19 output for lcd. rf2/an7/c1out/ seg20 rf2 an7 c1out seg20 18 i/o i oo st analog analog digital i/o. analog input 7. comparator 1 output. seg20 output for lcd. rf3/an8/seg21/ c2inb rf3 an8 seg21 c2inb 17 i/o i o i st analog analog analog digital i/o. analog input 8. seg21 output for lcd. comparator 2 input b. rf4/an9/seg22/ c2ina rf4 an9 seg22 c2ina 16 i/o i o i st analog analog analog digital i/o. analog input 9. seg22 output for lcd comparator 2 input a. rf5/an10/cv ref / seg23/c1inb rf5 an10 cv ref seg23 c1inb 15 i/o i oo i st analog analog analog analog digital i/o. analog input 10. comparator reference voltage output. seg23 output for lcd. comparator 1 input b. rf6/an11/seg24/ c1ina rf6 an11 seg24 c1ina 14 i/o i o i st analog analog analog digital i/o. analog input 11. seg24 output for lcd comparator 1 input a. rf7/an5/ss /seg25 rf7 an5 ss seg25 13 i/o o i o st analog ttl analog digital i/o. analog input 5. spi slave select input. seg25 output for lcd. table 1-2: pic18f8xj72 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i2c = i 2 c/smbus compatible input od = open-drain (no p diode to v dd ) i = input o = output p= p o w e r note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 19 pic18f87j72 family portg is a bidirectional i/o port. rg0/lcdbias0 rg0 lcdbias0 5 i/o i st analog digital i/o. bias0 input for lcd. rg1/tx2/ck2 rg1 tx2 ck2 6 i/o o i/o st st digital i/o. ausart asynchronous transmit. ausart synchronous clock (see related rx2/dt2). rg2/rx2/dt2/v lcap 1 rg2 rx2 dt2 v lcap 1 7 i/o i i/o i stst st analog digital i/o. ausart asynchronous receive. ausart synchronous data (see related tx2/ck2). lcd charge pump capacitor input. rg3/v lcap 2 rg3 v lcap 2 8 i/o i st analog digital i/o. lcd charge pump capacitor input. rg4/seg26/rtcc rg4 seg26 rtcc 10 i/o oo st analog digital i/o. seg26 output for lcd. rtcc output. v ss 11,32,50, 71 p ground reference for logic and i/o pins. v dd 47, 72 p positive supply for logic and i/o pins. av ss 24 p ground reference for analog modules. av dd 23 p positive supply for analog modules. envreg 22 i st enable for on-chip voltage regulator. v ddcore /v cap v ddcore v cap 12 pp core logic power or external filter capacitor connection. positive supply for microcontroller core logic (regulator disabled). external filter capacitor connection (regulator enabled). table 1-2: pic18f8xj72 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i2c = i 2 c/smbus compatible input od = open-drain (no p diode to v dd ) i = input o = output p= p o w e r note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j72 family ds39979a-page 20 preliminary ? 2010 microchip technology inc. reset 69 i st afe master reset logic input pin. sv dd 70 p afe digital power supply pin. sav dd 74 p afe analog power supply reference pin. ch0+ 1 i analog channel 0 non-inverting analog input pin. ch0- 2 i analog channel 0 inverting analog input pin. ch1- 19 i analog channel 1 inverting analog input pin. ch1+ 20 i analog channel 1 non-inverting analog input pin sav ss 26 p afe analog ground pin (return path for analog circuitry). refin+/out refin+ refout 28 i o analog analog afe non-inverting voltage reference input. internal reference output pin. refin- 29 i analog inverting voltage reference input pin. sv ss 36 p afe digital ground pin (return path for digital circuitry). dr 40 afe data ready signal output pin. clkia 41 i cmos afe oscillator crystal connection pin or external clock input pin. csa 58 i ttl afe serial interface chip select pin. scka 59 i ttl afe serial interface clock pin. sdoa 60 o ttl afe serial interface data output pin. sdia 64 i ttl afe serial interface data input pin. table 1-2: pic18f8xj72 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i2c = i 2 c/smbus compatible input od = open-drain (no p diode to v dd ) i = input o = output p= p o w e r note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2010 microchip technology inc. ds39979a-page 21 pic18f87j72 family 2.0 guidelines for getting started with pic18fj microcontrollers 2.1 basic connection requirements getting started with the pic18f87j72 family family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. the following pins must always be connected: all v dd and v ss pins (see section 2.2 power supply pins ) all av dd and av ss pins, regardless of whether or not the analog device features are used (see section 2.2 power supply pins ) mclr pin (see section 2.3 master clear (mclr) pin ) envreg (if implemented) and v cap /v ddcore pins (see section 2.4 voltage regulator pins (envreg and v cap /v ddcore ) ) these pins must also be connected if they are being used in the end application: pgc/pgd pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 icsp pins ) osci and osco pins when an external oscillator source is used (see section 2.6 external oscillator pins ) additionally, the following pins may be required: v ref +/v ref - pins are used when external voltage reference for analog modules is implemented the minimum mandatory connections are shown in figure 2-1. figure 2-1: recommended minimum connections note: the av dd and av ss pins must always be connected, regardless of whether any of the analog modules are being used. pic18fxxjxx v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss c1 r1 v dd mclr v cap /v ddcore r2 envreg (1) c7 c2 (2) c3 (2) c4 (2) c5 (2) c6 (2) key (all values are recommendations): c1 through c6: 0.1 ? f, 20v ceramic c7: 10 ? f, 6.3v or greater, tantalum or ceramic r1: 10 k ? r2: 100 ? to 470 ? note 1: see section 2.4 voltage regulator pins (envreg and v cap /v ddcore ) for explanation of envreg pin connections. 2: the example shown is for a pic18f device with five v dd /v ss and av dd /av ss pairs. other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. (1) downloaded from: http:///
pic18f87j72 family ds39979a-page 22 ? 2010 microchip technology inc. 2.2 power supply pins 2.2.1 decoupling capacitors the use of decoupling capacitors on every pair of power supply pins, such as v dd , v ss , av dd and av ss , is required. consider the following criteria when using decoupling capacitors: value and type of capacitor: a 0.1 ? f (100 nf), 10-20v capacitor is recommended. the capacitor should be a low-esr device, with a resonance frequency in the range of 200 mhz and higher. ceramic capacitors are recommended. placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended to place the capacitors on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). handling high-frequency noise: if the board is experiencing high-frequency noise (upward of tens of mhz), add a second ceramic type capaci- tor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 ? f to 0.001 ? f. place this second capacitor next to each primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 ? f in parallel with 0.001 ? f). maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing pcb trace inductance. 2.2.2 tank capacitors on boards with power traces running longer than six inches in length, it is suggested to use a tank capac- itor for integrated circuits, including microcontrollers, to supply a local power source. the value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. in other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. typical values range from 4.7 ? f to 47 ? f. 2.3 master clear (mclr ) pin the mclr pin provides two specific device functions: device reset, and device programming and debugging. if programming and debugging are not required in the end application, a direct connection to v dd may be all that is required. the addition of other components, to help increase the applications resistance to spurious resets from voltage sags, may be beneficial. a typical configuration is shown in figure 2-1. other circuit designs may be implemented, depending on the applications requirements. during programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. therefore, specific values of r1 and c1 will need to be adjusted based on the application and pcb requirements. for example, it is recommended that the capacitor, c1, be isolated from the mclr pin during programming and debugging operations by using a jumper (figure 2-2). the jumper is replaced for normal run-time operations. any components associated with the mclr pin should be placed within 0.25 inch (6 mm) of the pin. figure 2-2: example of mclr pin connections note 1: r1 ?? 10 k ? is recommended. a suggested starting value is 10 k ? . ensure that the mclr pin v ih and v il specifications are met. 2: r2 ?? 470 ? will limit any current flowing into mclr from the external capacitor, c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. c1 r2 r1 v dd mclr pic18fxxjxx jp downloaded from: http:///
? 2010 microchip technology inc. ds39979a-page 23 pic18f87j72 family 2.4 voltage regulator pins (envreg and v cap /v ddcore ) the on-chip voltage regulator enable pin, envreg, must always be connected directly to either a supply voltage or to ground. tying envreg to v dd enables the regulator, while tying it to ground disables the regulator. refer to section 26.3 on-chip voltage regulator for details on connecting and using the on-chip regulator. when the regulator is enabled, a low-esr (< 5 ? ) capacitor is required on the v cap /v ddcore pin to stabilize the voltage regulator output voltage. the v cap /v ddcore pin must not be connected to v dd and must use a capacitor of 10 ? f connected to ground. the type can be ceramic or tantalum. a suitable example is the murata grm21bf50j106ze01 (10 ? f, 6.3v) or equivalent. designers may use figure 2-3 to evaluate esr equivalence of candidate devices. it is recommended that the trace length not exceed 0.25 inch (6 mm). refer to section 29.0 electrical characteristics for additional information. when the regulator is disabled, the v cap /v ddcore pin must be tied to a voltage supply at the v ddcore level. refer to section 29.0 electrical characteristics for information on v dd and v ddcore . note that the lf versions of some low pin count pic18fj parts (e.g., the pic18lf45j10) do not have the envreg pin. these devices are provided with the voltage regulator permanently disabled; they must always be provided with a supply voltage on the v ddcore pin. figure 2-3: frequency vs. esr performance for suggested v cap 2.5 icsp pins the pgc and pgd pins are used for in-circuit serial programming? (icsp?) and debugging purposes. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recom- mended, with the value in the range of a few tens of ohms, not to exceed 100 ? . pull-up resistors, series diodes, and capacitors on the pgc and pgd pins are not recommended as they will interfere with the programmer/debugger communica- tions to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alter- natively, refer to the ac/dc characteristics and timing requirements information in the respective device flash programming specification for information on capacitive loading limits, and pin input voltage high (v ih ) and input low (v il ) requirements. for device emulation, ensure that the communication channel select (i.e., pgcx/pgdx pins) programmed into the device matches the physical connections for the icsp to the microchip debugger/emulator tool. for more information on available microchip development tools connection requirements, refer to section 28.0 development support . 10 1 0.1 0.01 0.001 0.01 0.1 1 10 100 1000 10,000 frequency (mhz) esr ( ? ) note: data for murata grm21bf50j106ze01 shown. measurements at 25c, 0v dc bias. downloaded from: http:///
pic18f87j72 family ds39979a-page 24 ? 2010 microchip technology inc. 2.6 external oscillator pins many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to section 3.0 oscillator configurations for details). the oscillator circuit should be placed on the same side of the board as the device. place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. layout suggestions are shown in figure 2-4. in-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. with fine-pitch packages, it is not always possible to com- pletely surround the pins and components. a suitable solution is to tie the broken guard sections to a mirrored ground layer. in all cases, the guard trace(s) must be returned to ground. in planning the applications routing and i/o assign- ments, ensure that adjacent port pins and other signals in close proximity to the oscillator are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). for additional information and design guidance on oscillator circuits, please refer to these microchip application notes, available at the corporate web site (www.microchip.com): an826, crystal oscillator basics and crystal selection for rfpic? and picmicro ? devices an849, basic picmicro ? oscillator design an943, practical picmicro ? oscillator analysis and design an949, making your oscillator work 2.7 unused i/os unused i/o pins should be configured as outputs and driven to a logic low state. alternatively, connect a 1 k ? to 10 k ? resistor to v ss on unused pins and drive the output to logic low. figure 2-4: suggested placement of the oscillator circuit gnd `` ` osc1 osc2 t1oso t1os i copper pour primary oscillator crystal timer1 oscillator crystal device pins primary oscillator c1c2 t1 oscillator: c1 t1 oscillator: c2 (tied to ground) single-sided and in-line layouts: fine-pitch (dual-sided) layouts: gnd osco osci bottom layer copper pour oscillator crystal top layer copper pour c2 c1 device pins (tied to ground) (tied to ground) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 25 pic18f87j72 family 3.0 oscillator configurations 3.1 oscillator types the pic18f87j72 family of devices can be operated in eight different oscillator modes: 1. ecpll osc1/osc2 as primary; ecpll oscillator with pll enabled, clko on ra6 2. ec osc1/osc2 as primary; external clock with f osc /4 output 3. hspll osc1/osc2 as primary; high-speed crystal/resonator with software pll control 4. hs osc1/osc2 as primary; high-speed crystal/resonator 5. intpll1 internal oscillator block with software pll control, f osc /4 output on ra6 and i/o on ra7 6. intio1 internal oscillator block with f osc /4 output on ra6 and i/o on ra7 7. intpll2 internal oscillator block with software pll control and i/o on ra6 and ra7 8. intio2 internal oscillator block with i/o on ra6 and ra7 all of these modes are selected by the user by programming the fosc<2:0> configuration bits. in addition, pic18f87j72 family devices can switch between different clock sources, either under software control or automatically under certain conditions. this allows for additional power savings by managing device clock speed in real time without resetting the application. the clock sources for the pic18f87j72 family of devices are shown in figure 3-1. figure 3-1: pic18f87j72 family clock diagram 4 x pll fosc<2:0> secondary oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep hspll, ecpll, intpll hs, ec t1osc cpu peripherals idlen postscaler mux mux 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 125 khz 250 khz osccon<6:4> 111110 101 100 011 010 001 000 31 khz intrc source internal oscillator block wdt, pwrt, fscm 8 mhz internal oscillator (intosc) osccon<6:4> clock control osccon<1:0> source 8 mhz 31 khz (intrc) 0 1 osctune<7> and two-speed start-up primary oscillator osctune<6> downloaded from: http:///
pic18f87j72 family ds39979a-page 26 preliminary ? 2010 microchip technology inc. 3.2 control registers the osccon register (register 3-1) controls the main aspects of the device clocks operation. it selects the oscillator type to be used, which of the power-managed modes to invoke and the output frequency of the intosc source. it also provides status on the oscillators. the osctune register (register 3-2) controls the tuning and operation of the internal oscillator block. it also implements the pllen bits which control the operation of the phase locked loop (pll) (see section 3.4.3 pll frequency multiplier ). register 3-1: osccon: os cillator control register (1) r/w-0 r/w-1 r/w-1 r/w-0 r (2) r-0 r/w-0 r/w-0 idlen ircf2 (3) ircf1 (3) ircf0 (3) osts iofs scs1 (5) scs0 (5) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 idlen: idle enable bit 1 = device enters an idle mode when a sleep instruction is executed 0 = device enters sleep mode when a sleep instruction is executed bit 6-4 ircf<2:0>: intosc source frequency select bits (3) 111 = 8 mhz (intosc drives clock directly) 110 = 4 mhz (default) 101 = 2 mhz 100 = 1 mhz 011 = 500 khz 010 = 250 khz 001 = 125 khz 000 = 31 khz (from either intosc/256 or intrc) (4) bit 3 osts: oscillator start-up timer time-out status bit (2) 1 = oscillator start-up timer (ost) time-out has expired; primary oscillator is running 0 = oscillator start-up timer (ost) time-out is running; primary oscillator is not ready bit 2 iofs: intosc frequency stable bit 1 = fast rc oscillator frequency is stable 0 = fast rc oscillator frequency is not stable bit 1-0 scs<1:0>: system clock select bits (5) 11 = internal oscillator block 10 = primary oscillator 01 = timer1 oscillator 00 = default primary oscillator (as defined by fosc<2:0> configuration bits) note 1: default (legacy) sfr at this address; available when wdtcon<4> = 0 . 2: reset state depends on the state of the ieso configuration bit. 3: modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. 4: source selected by the intsrc bit (osctune<7>), see text. 5: modifying these bits will cause an immediate clock source switch. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 27 pic18f87j72 family 3.3 clock sources and oscillator switching essentially, pic18f87j72 family devices have three independent clock sources: primary oscillators secondary oscillators internal oscillator the primary oscillators can be thought of as the main device oscillators. these are any external oscillators connected to the osc1 and osc2 pins, and include the external crystal and resonator modes and the external clock modes. if selected by the fosc<2:0> configuration bits, the internal oscillator block (either the 31 khz intrc or the 8 mhz intosc source) may be considered a primary oscillator. the particular mode is defined by the fosc configuration bits. the details of these modes are covered in section 3.4 external oscillator modes . the secondary oscillators are external clock sources that are not connected to the osc1 or osc2 pins. these sources may continue to operate even after the controller is placed in a power-managed mode. pic18f87j72 family devices offer the timer1 oscillator as a secondary oscillator source. this oscillator, in all power-managed modes, is often the time base for functions such as a real-time clock (rtc). the timer1 oscillator is discussed in greater detail in section 12.0 timer1 module . in addition to being a primary clock source in some circumstances, the internal oscillator is available as a power-managed mode clock source. the intrc source is also used as the clock source for several special features, such as the wdt and fail-safe clock monitor. the internal oscillator block is discussed in more detail in section 3.5 internal oscillator block . the pic18f87j72 family includes features that allow the device clock source to be switched from the main oscillator, chosen by device configuration, to one of the alternate clock sources. when an alternate clock source is enabled, various power-managed operating modes are available. register 3-2: osctune: osci llator tuning register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 intsrc pllen tun5 tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 intsrc: internal oscillator low-frequency source select bit 1 = 31.25 khz device clock derived from 8 mhz intosc source (divide-by-256 enabled) 0 = 31 khz device clock derived from intrc 31 khz oscillator bit 6 pllen: frequency multiplier pll enable bit 1 = pll is enabled 0 = pll is disabled bit 5-0 tun<5:0>: fast rc oscillator (intosc) frequency tuning bits 011111 = maximum frequency 000001 000000 = center frequency. fast rc oscillator is running at the calibrated frequency. 111111 100000 = minimum frequency downloaded from: http:///
pic18f87j72 family ds39979a-page 28 preliminary ? 2010 microchip technology inc. 3.3.1 clock source selection the system clock select bits, scs<1:0> (osccon<1:0>), select the clock source. the avail- able clock sources are the primary clock defined by the fosc<2:0> configuration bits, the secondary clock (timer1 oscillator) and the internal oscillator. the clock source changes after one or more of the bits is written to, following a brief clock transition interval. the osts (osccon<3>) and t1run (t1con<6>) bits indicate which clock source is currently providing the device clock. the osts bit indicates that the oscillator start-up timer (ost) has timed out and the primary clock is providing the device clock in primary clock modes. the t1run bit indicates when the timer1 oscillator is providing the device clock in sec- ondary clock modes. in power-managed modes, only one of these bits will be set at any time. if neither of these bits is set, the intrc is providing the clock or the internal oscillator has just started and is not yet stable. the idlen bit determines if the device goes into sleep mode or one of the idle modes when the sleep instruction is executed. the use of the flag and control bits in the osccon register is discussed in more detail in section 4.0 power-managed modes . 3.3.1.1 system clock selection and device resets since the scs bits are cleared on all forms of reset, this means the primary oscillator defined by the fosc<2:0> configuration bits is used as the primary clock source on device resets. this could either be the internal oscillator block by itself or one of the other primary clock source (hs, ec, hspll, ecpll1/2 or intpll1/2). in those cases, when the internal oscillator block with- out pll, is the default clock on reset, the fast rc oscillator (intosc) will be used as the device clock source. it will initially start at 1 mhz, which is the postscaler selection that corresponds to the reset value of the ircf<2:0> bits ( 100 ). regardless of which primary oscillator is selected, intrc will always be enabled on device power-up. it serves as the clock source until the device has loaded its configuration values from memory. it is at this point that the fosc configuration bits are read and the oscillator selection of the operational mode is made. note that either the primary clock source, or the internal oscillator, will have two bit setting options for the possible values of the scs<1:0> bits at any given time. 3.3.2 oscillator transitions pic18f87j72 family devices contain circuitry to prevent clock glitches when switching between clock sources. a short pause in the device clock occurs dur- ing the clock switch. the length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. clock transitions are discussed in greater detail in section 4.1.2 entering power-managed modes . note 1: the timer1 oscillator must be enabled to select the secondary clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control regis- ter (t1con<3>). if the timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a sleep instruction will be ignored. 2: it is recommended that the timer1 oscillator be operating and stable before executing the sleep instruction or a very long delay may occur while the timer1 oscillator starts. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 29 pic18f87j72 family 3.4 external oscillator modes 3.4.1 crystal oscillator/ceramic resonators (hs modes) in hs or hspll oscillator modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation. figure 3-2 shows the pin connections. the oscillator design requires the use of a crystal rated for parallel resonant operation. table 3-1: capacitor selection for ceramic resonators table 3-2: capacitor selection for crystal oscillator figure 3-2: crystal/ceramic resonator operation (hs or hspll configuration) note: use of a crystal rated for series resonant operation may give a frequency out of the crystal manufacturers specifications. typical capacitor values used: mode freq. osc1 osc2 hs 8.0 mhz 16.0 mhz 27 pf 22 pf 27 pf22 pf capacitor values are for design guidance only. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. refer to the following application notes for oscillator specific information: an588, pic ? microcontroller oscillator design guide an826, crystal oscillator basics and crystal selection for rfpic ? and pic ? devices an849, basic pic ? oscillator design an943, practical pic ? oscillator analysis and design an949, making your oscillator work see the notes following table 3-2 for additional information. osc type crystal freq. typical capacitor values tested: c1 c2 hs 4 mhz 27 pf 27 pf 8 mhz 22 pf 22 pf 20 mhz 15 pf 15 pf capacitor values are for design guidance only. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. refer to the microchip application notes cited in table 3-1 for oscillator specific information. also see the notes following this table for additional information. note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: rs may be required to avoid overdriving crystals with low drive level specification. 4: always verify oscillator performance over the v dd and temperature range that is expected for the application. note 1: see table 3-1 and table 3-2 for initial values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the oscillator mode chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep tologic r s (2) internal pic18f87j72 downloaded from: http:///
pic18f87j72 family ds39979a-page 30 preliminary ? 2010 microchip technology inc. 3.4.2 external clock input (ec modes) the ec and ecpll oscillator modes require an external clock source to be connected to the osc1 pin. there is no oscillator start-up time required after a power-on reset or after an exit from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 3-3 shows the pin connections for the ec oscillator mode. figure 3-3: external clock input operation (ec configuration) an external clock source may also be connected to the osc1 pin in the hs mode, as shown in figure 3-4. in this configuration, the divide-by-4 output on osc2 is not available. current consumption in this configuration will be somewhat higher than ec mode, as the internal oscillators feedback circuitry will be enabled (in ec mode, the feedback circuit is disabled). figure 3-4: external clock input operation (hs osc configuration) 3.4.3 pll frequency multiplier a phase locked loop (pll) circuit is provided as an option for users who want to use a lower frequency oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. this may be useful for customers who are concerned with emi due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. 3.4.3.1 hspll and ecpll modes the hspll and ecpll modes provide the ability to selectively run the device at 4 times the external oscillating source to produce frequencies up to 40 mhz. the pll is enabled by programming the fosc<2:0> configuration bits to either 111 (for ecpll) or 101 (for hspll). in addition, the pllen bit (osctune<6>) must also be set. clearing pllen disables the pll, regardless of the chosen oscillator configuration. it also allows additional flexibility for controlling the applications clock speed in software. figure 3-5: pll block diagram 3.4.3.2 pll and intosc the pll is also available to the internal oscillator block when the internal oscillator block is configured as the primary clock source. in this configuration, the pll is enabled in software and generates a clock output of up to 32 mhz. the operation of intosc with the pll is described in section 3.5.2 intpll modes . osc1/clki osc2/clko f osc /4 clock from ext. system pic18f87j72 osc1 osc2 open clock from ext. system (hs mode) pic18f87j72 mux vco loop filter osc2 osc1 pll enable (osctune) f in f out sysclk phase comparator hspll or ecpll (config2l) ? 4 hs or ec mode downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 31 pic18f87j72 family 3.5 internal oscillator block the pic18f87j72 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcon- trollers clock source. this may eliminate the need for an external oscillator circuit on the osc1 and/or osc2 pins. the main output is the fast rc oscillator, or intosc, an 8 mhz clock source which can be used to directly drive the device clock. it also drives a postscaler, which can provide a range of clock frequencies from 31 khz to 4 mhz. intosc is enabled when a clock frequency from 125 khz to 8 mhz is selected. the intosc out- put can also be enabled when 31 khz is selected, depending on the intsrc bit (osctune<7>). the other clock source is the internal rc (intrc) oscillator, which provides a nominal 31 khz output. intrc is enabled if it is selected as the device clock source. it is also enabled automatically when any of the following are enabled: power-up timer fail-safe clock monitor watchdog timer two-speed start-up these features are discussed in greater detail in section 26.0 special features of the cpu . the clock source frequency (intosc direct, intosc with postscaler or intrc direct) is selected by config- uring the ircf bits of the osccon register. the default frequency on device resets is 4 mhz. 3.5.1 intio modes using the internal oscillator as the clock source elimi- nates the need for up to two external oscillator pins, which can then be used for digital i/o. two distinct oscillator configurations, which are determined by the fosc configuration bits, are available: in intio1 mode, the osc2 pin outputs f osc /4 while osc1 functions as ra7 (see figure 3-6) for digital input and output. in intio2 mode, osc1 functions as ra7 and osc2 functions as ra6 (see figure 3-7), both for digital input and output. figure 3-6: intio1 oscillator mode figure 3-7: intio2 oscillator mode 3.5.2 intpll modes the 4x phase locked loop (pll) can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with the internal oscillator sources. when enabled, the pll produces a clock speed of 16 mhz or 32 mhz. pll operation is controlled through software. the con- trol bit, pllen (osctune<6>), is used to enable or disable its operation. the pll is available only to intosc when the device is configured to use one of the intpll modes as the primary clock source (fosc<2:0> = 011 or 001 ). additionally, the pll will only function when the selected output frequency is either 4 mhz or 8 mhz (osccon<6:4> = 111 or 110 ). like the intio modes, there are two distinct intpll modes available: in intpll1 mode, the osc2 pin outputs f osc /4, while osc1 functions as ra7 for digital input and output. externally, this is identical in appearance to intio1 (figure 3-6). in intpll2 mode, osc1 functions as ra7 and osc2 functions as ra6, both for digital input and output. externally, this is identical to intio2 (figure 3-7). osc2 f osc /4 i/o (osc1) ra7 pic18f87j72 i/o (osc2) ra6 i/o (osc1) ra7 pic18f87j72 downloaded from: http:///
pic18f87j72 family ds39979a-page 32 preliminary ? 2010 microchip technology inc. 3.5.3 internal oscillator output frequency and tuning the internal oscillator block is calibrated at the factory to produce an intosc output frequency of 8 mhz. it can be adjusted in the users application by writing to tun<5:0> (osctune<5:0>) in the osctune register (register 3-2). when the osctune register is modified, the intosc frequency will begin shifting to the new frequency. the oscillator will stabilize within 1 ms. code execution continues during this shift and there is no indication that the shift has occurred. the intrc oscillator operates independently of the intosc source. any changes in intosc across voltage and temperature are not necessarily reflected by changes in intrc or vice versa. the frequency of intrc is not affected by osctune. 3.5.4 intosc frequency drift the intosc frequency may drift as v dd or tempera- ture changes and can affect the controller operation in a variety of ways. it is possible to adjust the intosc frequency by modifying the value in the osctune register. depending on the device, this may have no effect on the intrc clock source frequency. tuning intosc requires knowing when to make the adjustment, in which direction it should be made, and in some cases, how large a change is needed. three compensation techniques are shown here. 3.5.4.1 compensating with the eusart an adjustment may be required when the eusart begins to generate framing errors or receives data with errors while in asynchronous mode. framing errors indicate that the device clock frequency is too high. to adjust for this, decrement the value in osctune to reduce the clock frequency. on the other hand, errors in data may suggest that the clock speed is too low. to compensate, increment osctune to increase the clock frequency. 3.5.4.2 compensating with the timers this technique compares device clock speed to some reference clock. two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the timer1 oscillator. both timers are cleared, but the timer clocked by the reference generates interrupts. when an interrupt occurs, the internally clocked timer is read and both timers are cleared. if the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. to adjust for this, decrement the osctune register. 3.5.4.3 compensating with the ccp module in capture mode a ccp module can use free-running timer1 (or timer3), clocked by the internal oscillator block and an external event with a known period (i.e., ac power frequency). the time of the first event is captured in the ccprxh:ccprxl registers and is recorded for use later. when the second event causes a capture, the time of the first event is subtracted from the time of the second event. since the period of the external event is known, the time difference between events can be calculated. if the measured time is much greater than the calculated time, the internal oscillator block is running too fast. to compensate, decrement the osctune register. if the measured time is much less than the calculated time, the internal oscillator block is running too slow. to compensate, increment the osctune register. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 33 pic18f87j72 family 3.6 effects of power-managed modes on the various clock sources when pri_idle mode is selected, the designated pri- mary oscillator continues to run without interruption. for all other power-managed modes, the oscillator using the osc1 pin is disabled. the osc1 pin (and osc2 pin if used by the oscillator) will stop oscillating. in secondary clock modes (sec_run and sec_idle), the timer1 oscillator is operating and providing the device clock. the timer1 oscillator may also run in all power-managed modes if required to clock timer1 or timer3. in rc_run and rc_idle modes, the internal oscillator provides the device clock source. the 31 khz intrc output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see section 26.2 watchdog timer (wdt) through section 26.5 fail-safe clock monitor for more information on wdt, fail-safe clock monitor and two-speed start-up). if the sleep mode is selected, all clock sources are stopped. since all the transistor switching currents have been stopped, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the intrc is required to support wdt operation. the timer1 oscillator may be operating to support a real- time clock (rtc). other features may be operating that do not require a device clock source (i.e., mssp slave, intx pins and others). peripherals that may add significant current consumption are listed in section 29.2 dc characteristics: power-down and supply current pic18f87j72 family (industrial) . 3.7 power-up delays power-up delays are controlled by two timers, so that no external reset circuitry is required for most applica- tions. the delays ensure that the device is kept in reset until the device power supply is stable under nor- mal circumstances, and the primary clock is operating and stable. for additional information on power-up delays, see section 5.6 power-up timer (pwrt) . the first timer is the power-up timer (pwrt), which provides a fixed delay on power-up (parameter 33, table 29-11); it is always enabled. the second timer is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable (hs modes). the ost does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. there is a delay of interval, t csd (parameter 38, table 29-11), following por, while the controller becomes ready to execute instructions. table 3-3: osc1 and osc2 pin states in sleep mode oscillator mode osc1 pin osc2 pin ec, ecpll floating, pulled by external clock at logic low (clock/4 output) hs, hspll feedback inverter disabled at quiescent voltage level feedback inverter disabled at quiescent voltage level intosc, intpll1/2 i/o pin, ra6, direction controlled by trisa<6> i/o pin, ra6, direction controlled by trisa<7> note: see section 5.0 reset for time-outs due to sleep and mclr reset. downloaded from: http:///
pic18f87j72 family ds39979a-page 34 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 35 pic18f87j72 family 4.0 power-managed modes the pic18f87j72 family devices provide the ability to manage power consumption by simply managing clock- ing to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. for the sake of managing power in an application, there are three primary modes of operation: run mode idle mode sleep mode these modes define which portions of the device are clocked and at what speed. the run and idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the sleep mode does not use a clock source. the power-managed modes include several power-saving features offered on previous pic ? devices. one is the clock switching feature, offered in other pic18 devices, allowing the controller to use the timer1 oscillator in place of the primary oscillator. also included is the sleep mode, offered by all pic devices, where all device clocks are stopped. 4.1 selecting power-managed modes selecting a power-managed mode requires two decisions: if the cpu is to be clocked or not and which clock source is to be used. the idlen bit (osccon<7>) controls cpu clocking, while the scs<1:0> bits (osccon<1:0>) select the clock source. the individual modes, bit settings, clock sources and affected modules are summarized in table 4-1. 4.1.1 clock sources the scs<1:0> bits allow the selection of one of three clock sources for power-managed modes. they are: the primary clock, as defined by the fosc<2:0> configuration bits the secondary clock (timer1 oscillator) the internal oscillator 4.1.2 entering power-managed modes switching from one power-managed mode to another begins by loading the osccon register. the scs<1:0> bits select the clock source and determine which run or idle mode is to be used. changing these bits causes an immediate switch to the new clock source, assuming that it is running. the switch may also be subject to clock transition delays. these are discussed in section 4.1.3 clock transitions and status indicators and subsequent sections. entry to the power-managed idle or sleep modes is triggered by the execution of a sleep instruction. the actual mode that results depends on the status of the idlen bit. depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. many transitions may be done by changing the oscillator select bits, or changing the idlen bit, prior to issuing a sleep instruction. if the idlen bit is already configured correctly, it may only be necessary to perform a sleep instruction to switch to the desired mode. table 4-1: power- managed modes mode osccon bits module clocking available clock and oscillator source idlen<7> (1) scs<1:0> cpu peripherals sleep 0 n/a off off none C all clocks are disabled pri_run n/a 10 clocked clocked primary C hs, ec, hspll, ecpll; this is the normal full-power execution mode sec_run n/a 01 clocked clocked secondary C timer1 oscillator rc_run n/a 11 clocked clocked internal oscillator pri_idle 11 0 off clocked primary C hs, ec, hspll, ecpll sec_idle 10 1 off clocked secondary C timer1 oscillator rc_idle 11 1 off clocked internal oscillator note 1: idlen reflects its value when the sleep instruction is executed. downloaded from: http:///
pic18f87j72 family ds39979a-page 36 preliminary ? 2010 microchip technology inc. 4.1.3 clock transitions and status indicators the length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. two bits indicate the current clock source and its status: osts (osccon<3>) and t1run (t1con<6>). in general, only one of these bits will be set while in a given power-managed mode. when the osts bit is set, the primary clock is providing the device clock. when the t1run bit is set, the timer1 oscillator is providing the clock. if neither of these bits is set, intrc is clocking the device. 4.1.4 multiple sleep commands the power-managed mode that is invoked with the sleep instruction is determined by the setting of the idlen bit at the time the instruction is executed. if another sleep instruction is executed, the device will enter the power-managed mode specified by idlen at that time. if idlen has changed, the device will enter the new power-managed mode specified by the new setting. 4.2 run modes in the run modes, clocks to both the core and peripherals are active. the difference between these modes is the clock source. 4.2.1 pri_run mode the pri_run mode is the normal, full-power execu- tion mode of the microcontroller. this is also the default mode upon a device reset unless two-speed start-up is enabled (see section 26.4 two-speed start-up for details). in this mode, the osts bit is set (see section 3.2 control registers ). 4.2.2 sec_run mode the sec_run mode is the compatible mode to the clock switching feature offered in other pic18 devices. in this mode, the cpu and peripherals are clocked from the timer1 oscillator. this gives users the option of lower power consumption while still using a high-accuracy clock source. sec_run mode is entered by setting the scs<1:0> bits to 01 . the device clock source is switched to the timer1 oscillator (see figure 4-1), the primary oscilla- tor is shut down, the t1run bit (t1con<6>) is set and the osts bit is cleared. note: executing a sleep instruction does not necessarily place the device into sleep mode. it acts as the trigger to place the controller into either the sleep mode, or one of the idle modes, depending on the setting of the idlen bit. note: the timer1 oscillator should already be running prior to entering sec_run mode. if the t1oscen bit is not set when the scs<1:0> bits are set to 01 , entry to sec_run mode will not occur. if the timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. in such situa- tions, initial oscillator operation is far from stable and unpredictable operation may result. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 37 pic18f87j72 family on transitions from sec_run mode to pri_run mode, the peripherals and cpu continue to be clocked from the timer1 oscillator while the primary clock is started. when the primary clock becomes ready, a clock switch back to the primary clock occurs (see figure 4-2). when the clock switch is complete, the t1run bit is cleared, the osts bit is set and the primary clock is providing the clock. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run. figure 4-1: transition timing for entry to sec_run mode figure 4-2: transition timing from sec_run mode to pri_run mode (hspll) q4 q3 q2 osc1 peripheral program q1 t1osi q1 counter clock cpu clock pc + 2 pc 123 n-1 n clock transition q4 q3 q2 q1 q3 q2 pc + 4 q1 q3 q4 osc1 peripheral program pc t1osi pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. scs<1:0> bits changed t pll (1) 12 n-1n clock osts bit set transition t ost (1) downloaded from: http:///
pic18f87j72 family ds39979a-page 38 preliminary ? 2010 microchip technology inc. 4.2.3 rc_run mode in rc_run mode, the cpu and peripherals are clocked from the internal oscillator; the primary clock is shut down. this mode provides the best power conser- vation of all the run modes while still executing code. it works well for user applications which are not highly timing-sensitive or do not require high-speed clocks at all times. this mode is entered by setting scs bits to 11 . when the clock source is switched to the intrc (see figure 4-3), the primary oscillator is shut down and the osts bit is cleared. on transitions from rc_run mode to pri_run mode, the device continues to be clocked from the intrc while the primary clock is started. when the primary clock becomes ready, a clock switch to the primary clock occurs (see figure 4-4). when the clock switch is complete, the osts bit is set and the primary clock is providing the device clock. the idlen and scs bits are not affected by the switch. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. figure 4-3: transition timing to rc_run mode figure 4-4: transition timing from rc_run mode to pri_run mode q4 q3 q2 osc1 peripheral program q1 intrc q1 counter clock cpu clock pc + 2 pc 123 n - 1n clock transition q4 q3 q2 q1 q3 q2 pc + 4 q1 q3 q4 osc1 peripheral program pc intrc pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. scs<1:0> bits changed t pll (1) 12 n-1n clock osts bit set transition t ost (1) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 39 pic18f87j72 family 4.3 sleep mode the power-managed sleep mode is identical to the leg- acy sleep mode offered in all other pic devices. it is entered by clearing the idlen bit (the default state on device reset) and executing the sleep instruction. this shuts down the selected oscillator (figure 4-5). all clock source status bits are cleared. entering the sleep mode from any other mode does not require a clock switch. this is because no clocks are needed once the controller has entered sleep. if the wdt is selected, the intrc source will continue to operate. if the timer1 oscillator is enabled, it will also continue to run. when a wake event occurs in sleep mode (by interrupt, reset or wdt time-out), the device will not be clocked until the clock source selected by the scs<1:0> bits becomes ready (see figure 4-6), or it will be clocked from the internal oscillator if either the two-speed start-up or the fail-safe clock monitor is enabled (see section 26.0 special features of the cpu ). in either case, the osts bit is set when the primary clock is providing the device clocks. the idlen and scs bits are not affected by the wake-up. 4.4 idle modes the idle modes allow the controllers cpu to be selectively shut down while the peripherals continue to operate. selecting a particular idle mode allows users to further manage power consumption. if the idlen bit is set to a 1 when a sleep instruction is executed, the peripherals will be clocked from the clock source selected using the scs<1:0> bits; however, the cpu will not be clocked. the clock source status bits are not affected. setting idlen and executing a sleep instruction provides a quick method of switching from a given run mode to its corresponding idle mode. if the wdt is selected, the intrc source will continue to operate. if the timer1 oscillator is enabled, it will also continue to run. since the cpu is not executing instructions, the only exits from any of the idle modes are by interrupt, wdt time-out or a reset. when a wake event occurs, cpu execution is delayed by an interval of t csd (parameter 38, table 29-11) while it becomes ready to execute code. when the cpu begins executing code, it resumes with the same clock source for the current idle mode. for example, when waking from rc_idle mode, the internal oscillator block will clock the cpu and peripherals (in other words, rc_run mode). the idlen and scs bits are not affected by the wake-up. while in any idle mode or the sleep mode, a wdt time-out will result in a wdt wake-up to the run mode currently specified by the scs<1:0> bits. figure 4-5: transition timing for entry to sleep mode figure 4-6: transition timing for wake from sleep (hspll) q4 q3 q2 osc1 peripheral sleep program q1 q1 counter clock cpu clock pc + 2 pc q3 q4 q1 q2 osc1 peripheral program pc pll clock q3 q4 output cpu clock q1 q2 q3 q4 q1 q2 clock counter pc + 6 pc + 4 q1 q2 q3 q4 wake event note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. t ost (1) t pll (1) osts bit set pc + 2 downloaded from: http:///
pic18f87j72 family ds39979a-page 40 preliminary ? 2010 microchip technology inc. 4.4.1 pri_idle mode this mode is unique among the three low-power idle modes, in that it does not disable the primary device clock. for timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to warm up or transition from another oscillator. pri_idle mode is entered from pri_run mode by setting the idlen bit and executing a sleep instruc- tion. if the device is in another run mode, set idlen first, then set the scs bits to 10 and execute sleep . although the cpu is disabled, the peripherals continue to be clocked from the primary clock source specified by the fosc<1:0> configuration bits. the osts bit remains set (see figure 4-7). when a wake event occurs, the cpu is clocked from the primary clock source. a delay of interval, t csd , is required between the wake event and when code execution starts. this is required to allow the cpu to become ready to execute instructions. after the wake-up, the osts bit remains set. the idlen and scs bits are not affected by the wake-up (see figure 4-8). 4.4.2 sec_idle mode in sec_idle mode, the cpu is disabled but the peripherals continue to be clocked from the timer1 oscillator. this mode is entered from sec_run by set- ting the idlen bit and executing a sleep instruction. if the device is in another run mode, set idlen first, then set scs<1:0> to 01 and execute sleep . when the clock source is switched to the timer1 oscillator, the primary oscillator is shut down, the osts bit is cleared and the t1run bit is set. when a wake event occurs, the peripherals continue to be clocked from the timer1 oscillator. after an interval of t csd , following the wake event, the cpu begins exe- cuting code being clocked by the timer1 oscillator. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run (see figure 4-8). figure 4-7: transition timing for entry to idle mode figure 4-8: transition timing for wake from idle to run mode note: the timer1 oscillator should already be running prior to entering sec_idle mode. if the t1oscen bit is not set when the sleep instruction is executed, the sleep instruction will be ignored and entry to sec_idle mode will not occur. if the timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. in such situations, initial oscillator operation is far from stable and unpredictable operation may result. q1 peripheral program pc pc + 2 osc1 q3 q4 q1 cpu clock clock counter q2 osc1 peripheral program pc cpu clock q1 q3 q4 clock counter q2 wake event t csd downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 41 pic18f87j72 family 4.4.3 rc_idle mode in rc_idle mode, the cpu is disabled but the periph- erals continue to be clocked from the internal oscillator. this mode allows for controllable power conservation during idle periods. from rc_run, this mode is entered by setting the idlen bit and executing a sleep instruction. if the device is in another run mode, first set idlen, then clear the scs bits and execute sleep . when the clock source is switched to the intrc, the primary oscillator is shut down and the osts bit is cleared. when a wake event occurs, the peripherals continue to be clocked from the intosc. after a delay of t csd , following the wake event, the cpu begins executing code being clocked by the intosc. the idlen and scs bits are not affected by the wake-up. the intosc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. 4.5 exiting idle and sleep modes an exit from sleep mode, or any of the idle modes, is triggered by an interrupt, a reset or a wdt time-out. this section discusses the triggers that cause exits from power-managed modes. the clocking subsystem actions are discussed in each of the power-managed mode sections (see section 4.2 run modes, section 4.3 sleep mode and section 4.4 idle modes ). 4.5.1 exit by interrupt any of the available interrupt sources can cause the device to exit from an idle mode, or the sleep mode, to a run mode. to enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the intcon or pie registers. the exit sequence is initiated when the corresponding interrupt flag bit is set. on all exits from idle or sleep modes, by interrupt, code execution branches to the interrupt vector if the gie/gieh bit (intcon<7>) is set. otherwise, code execution continues or resumes without branching (see section 9.0 interrupts ). a fixed delay of interval, t csd , following the wake event is required when leaving sleep and idle modes. this delay is required for the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. 4.5.2 exit by wdt time-out a wdt time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. if the device is not executing code (all idle modes and sleep mode), the time-out will result in an exit from the power-managed mode (see section 4.2 run modes and section 4.3 sleep mode ). if the device is executing code (all run modes), the time-out will result in a wdt reset (see section 26.2 watchdog timer (wdt) ). the watchdog timer and postscaler are cleared by one of the following events: executing a sleep or clrwdt instruction the loss of a currently selected clock source (if the fail-safe clock monitor is enabled) 4.5.3 exit by reset exiting an idle or sleep mode by reset automatically forces the device to run from the intrc. 4.5.4 exit without an oscillator start-up delay certain exits from power-managed modes do not invoke the ost at all. there are two cases: pri_idle mode, where the primary clock source is not stopped; and the primary clock source is either the ec or ecpll mode. in these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (pri_idle), or normally does not require an oscillator start-up delay (ec). however, a fixed delay of interval, t csd , following the wake event is still required when leaving sleep and idle modes to allow the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. downloaded from: http:///
pic18f87j72 family ds39979a-page 42 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 43 pic18f87j72 family 5.0 reset the pic18f87j72 family of devices differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation mclr reset during power-managed modes watchdog timer (wdt) reset (during execution) brown-out reset (bor) configuration mismatch (cm) reset instruction stack full reset stack underflow reset this section discusses resets generated by mclr , por and bor, and covers the operation of the various start-up timers. stack reset events are covered in section 6.1.4.4 stack full and underflow resets . wdt resets are covered in section 26.2 watchdog timer (wdt) . a simplified block diagram of the on-chip reset circuit is shown in figure 5-1. 5.1 rcon register device reset events are tracked through the rcon register (register 5-1). the lower five bits of the register indicate that a specific reset event has occurred. in most cases, these bits can only be set by the event and must be cleared by the application after the event. the state of these flag bits, taken together, can be read to indicate the type of reset that just occurred. this is described in more detail in section 5.7 reset state of registers . the rcon register also has a control bit for setting interrupt priority (ipen). interrupt priority is discussed in section 9.0 interrupts . figure 5-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd wdt time-out v dd rise detect pwrt intrc por pulse pwrt chip_reset 11-bit ripple counter brown-out reset (1) reset instruction stack pointer stack full/underflow reset sleep idle 65.5 ms (typical) note 1: the envreg pin must be tied high to enable brown-out re set. the brown-out reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. configuration word mismatch 32 ? s (typical) downloaded from: http:///
pic18f87j72 family ds39979a-page 44 preliminary ? 2010 microchip technology inc. register 5-1: rcon: re set control register r/w-0 u-0 r/w-1 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen c m ri to pd por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16xxxx compatibility mode) bit 6 unimplemented: read as 0 bit 5 cm : configuration mismatch (cm) flag bit 1 = a configuration mismatch has not occurred 0 = a configuration mismatch has occurred (must be set in software after a configuration mism atch reset occurs.) bit 4 ri : reset instruction flag bit 1 =the reset instruction was not executed (set by firmware only) 0 =the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = set by power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = set by power-up or by the clrwdt instruction 0 = set by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred (set by firmware only) 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred (set by firmware only) 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) note 1: it is recommended that the por bit be set after a power-on reset has been detected, so that subsequent power-on resets may be detected. 2: if the on-chip voltage regulator is disabled, bor remains 0 at all times. see section 5.4.1 detecting bor for more information. 3: brown-out reset is said to have occurred when bor is 0 and por is 1 (assuming that por was set to 1 by software immediately after a power-on reset). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 45 pic18f87j72 family 5.2 master clear (mclr ) the mclr pin provides a method for triggering a hard external reset of the device. a reset is generated by holding the pin low. pic18 extended microcontroller devices have a noise filter in the mclr reset path which detects and ignores small pulses. the mclr pin is not driven low by any internal resets, including the wdt. 5.3 power-on reset (por) a power-on reset condition is generated on-chip whenever v dd rises above a certain threshold. this allows the device to start in the initialized state when v dd is adequate for operation. to take advantage of the por circuitry, tie the mclr pin through a resistor (1 k ? to 10 k ? ) to v dd . this will eliminate external rc components usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (parameter d004). for a slow rise time, see figure 5-2. when the device starts normal operation (i.e., exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. power-on reset events are captured by the por bit (rcon<1>). the state of the bit is set to 0 whenever a power-on reset occurs; it does not change for any other reset event. por is not reset to 1 by any hardware event. to capture multiple events, the user manually resets the bit to 1 in software following any power-on reset. 5.4 brown-out reset (bor) the pic18f87j72 family of devices incorporates a simple bor function when the internal regulator is enabled (envreg pin is tied to v dd ). the voltage reg- ulator will trigger a brown-out reset when output of the regulator to the device core approaches the voltage at which the device is unable to run at full speed. the bor circuit also keeps the device in reset as v dd rises, until the regulators output level is sufficient for full-speed operation. once a bor has occurred, the power-up timer will keep the chip in reset for t pwrt (parameter 33). if v dd drops below the threshold for full-speed operation while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises to the point where regulator output is sufficient, the power-up timer will execute the additional time delay. figure 5-2: external power-on reset circuit (for slow v dd power-up) 5.4.1 detecting bor the bor bit always resets to 0 on any brown-out reset or power-on reset event. this makes it difficult to determine if a brown-out reset event has occurred just by reading the state of bor alone. a more reliable method is to simultaneously check the state of both por and bor . this assumes that the por bit is reset to 1 in software immediately after any power-on reset event. if bor is 0 while por is 1 , it can be reliably assumed that a brown-out reset event has occurred. if the voltage regulator is disabled, brown-out reset functionality is disabled. in this case, the bor bit cannot be used to determine a brown-out reset event. the bor bit is still cleared by a power-on reset event. 5.5 configuration mismatch (cm) the configuration mismatch (cm) reset is designed to detect, and attempt to recover from, random memory corrupting events. these include electrostatic discharge (esd) events that can cause widespread, single bit changes throughout the device and result in catastrophic failure. in pic18f87j72 family flash devices, the device configuration registers (located in the configuration memory space) are continuously monitored during operation by comparing their values to complimentary shadow registers. if a mismatch is detected between the two sets of registers, a cm reset automatically occurs. these events are captured by the cm bit (rcon<5>). the state of the bit is set to 0 whenever a cm event occurs. the bit does not change for any other reset event. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode, d, helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the devices electrical specification. 3: r1 ? 1 k ? will limit any current flowing into mclr from external capacitor, c, in the event of mclr /v pp pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr v dd pic18f87j72 downloaded from: http:///
pic18f87j72 family ds39979a-page 46 preliminary ? 2010 microchip technology inc. 5.6 power-up timer (pwrt) pic18f87j72 family devices incorporate an on-chip power-up timer (pwrt) to help regulate the power-on reset process. the pwrt is always enabled. the main function is to ensure that the device voltage is stable before code is executed. the power-up timer (pwrt) of the pic18f87j72 fam- ily devices is an 11-bit counter which uses the intrc source as the clock input. this yields an approximate time interval of 2048 x 32 ? s = 65.6 ms. while the pwrt is counting, the device is held in reset. the power-up time delay depends on the intrc clock and will vary from chip to chip due to temperature and process variation. see dc parameter 33 for details. 5.6.1 time-out sequence if enabled, the pwrt time-out is invoked after the por pulse has cleared. the total time-out will vary based on the status of the pwrt. figure 5-3, figure 5-4, figure 5-5 and figure 5-6 all depict time-out sequences on power-up with the power-up timer enabled. since the time-outs occur from the por pulse, if mclr is kept low long enough, the pwrt will expire. bringing mclr high will begin execution immediately (figure 5-5). this is useful for testing purposes, or to synchronize more than one pic18fxxxx device operating in parallel. figure 5-3: time-out sequence on power-up (mclr tied to v dd , v dd rise < t pwrt ) figure 5-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 t pwrt v dd mclr internal por pwrt time-out internal reset t pwrt v dd mclr internal por pwrt time-out internal reset downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 47 pic18f87j72 family figure 5-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 5-6: slow rise time (mclr tied to v dd , v dd rise > t pwrt ) v dd mclr internal por pwrt time-out internal reset t pwrt v dd mclr internal por pwrt time-out internal reset 0v 1v 3.3v t pwrt downloaded from: http:///
pic18f87j72 family ds39979a-page 48 preliminary ? 2010 microchip technology inc. 5.7 reset state of registers most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a reset state depending on the type of reset that occurred. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal operation. status bits from the rcon register, ri , to , pd , por and bor, are set or cleared differently in different reset situations, as indicated in table 5-1. these bits are used in software to determine the nature of the reset. table 5-2 describes the reset states for all of the special function registers. these are categorized by power-on and brown-out resets, master clear and wdt resets and wdt wake-ups. table 5-1: status bits, their significance and the initialization condition for rcon register condition program counter (1) rcon register stkptr register ri to pd por bor stkful stkunf power-on reset 0000h 11100 0 0 reset instruction 0000h 0uuuu u u brown-out reset 0000h 111u0 u u mclr during power-managed run modes 0000h u1uuu u u mclr during power-managed idle modes and sleep mode 0000h u10uu u u wdt time-out during full power or power-managed run modes 0000h u0uuu u u mclr during full power execution 0000h uuuuu u u stack full reset (stvren = 1 ) 0000h uuuuu 1 u stack underflow reset (stvren = 1 ) 0000h uuuuu u 1 stack underflow error (not an actual reset, stvren = 0 ) 0000h uuuuu u 1 wdt time-out during power-managed idle or sleep modes pc + 2 u00uu u u interrupt exit from power-managed modes pc + 2 uu0uu u u legend: u = unchanged note 1: when the wake-up is due to an interrupt and the gieh or giel bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 49 pic18f87j72 family table 5-2: initialization conditions for all registers register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt tosu pic18f8xj72 ---0 0000 ---0 0000 ---0 uuuu (1) tosh pic18f8xj72 0000 0000 0000 0000 uuuu uuuu (1) tosl pic18f8xj72 0000 0000 0000 0000 uuuu uuuu (1) stkptr pic18f8xj72 uu-0 0000 00-0 0000 uu-u uuuu (1) pclatu pic18f8xj72 ---0 0000 ---0 0000 ---u uuuu pclath pic18f8xj72 0000 0000 0000 0000 uuuu uuuu pcl pic18f8xj72 0000 0000 0000 0000 pc + 2 (2) tblptru pic18f8xj72 --00 0000 --00 0000 --uu uuuu tblptrh pic18f8xj72 0000 0000 0000 0000 uuuu uuuu tblptrl pic18f8xj72 0000 0000 0000 0000 uuuu uuuu tablat pic18f8xj72 0000 0000 0000 0000 uuuu uuuu prodh pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu prodl pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu intcon pic18f8xj72 0000 000x 0000 000u uuuu uuuu (3) intcon2 pic18f8xj72 1111 1111 1111 1111 uuuu uuuu ( 3) intcon3 pic18f8xj72 1100 0000 1100 0000 uuuu uuuu (3) indf0 pic18f8xj72 n/a n/a n/a postinc0 pic18f8xj72 n/a n/a n/a postdec0 pic18f8xj72 n/a n/a n/a preinc0 pic18f8xj72 n/a n/a n/a plusw0 pic18f8xj72 n/a n/a n/a fsr0h pic18f8xj72 ---- xxxx ---- uuuu ---- uuuu fsr0l pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu wreg pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu indf1 pic18f8xj72 n/a n/a n/a postinc1 pic18f8xj72 n/a n/a n/a postdec1 pic18f8xj72 n/a n/a n/a preinc1 pic18f8xj72 n/a n/a n/a plusw1 pic18f8xj72 n/a n/a n/a legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0 , q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 5-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as 0 . downloaded from: http:///
pic18f87j72 family ds39979a-page 50 preliminary ? 2010 microchip technology inc. fsr1h pic18f8xj72 ---- xxxx ---- uuuu ---- uuuu fsr1l pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu bsr pic18f8xj72 ---- 0000 ---- 0000 ---- uuuu indf2 pic18f8xj72 n/a n/a n/a postinc2 pic18f8xj72 n/a n/a n/a postdec2 pic18f8xj72 n/a n/a n/a preinc2 pic18f8xj72 n/a n/a n/a plusw2 pic18f8xj72 n/a n/a n/a fsr2h pic18f8xj72 ---- xxxx ---- uuuu ---- uuuu fsr2l pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu status pic18f8xj72 ---x xxxx ---u uuuu ---u uuuu tmr0h pic18f8xj72 0000 0000 0000 0000 uuuu uuuu tmr0l pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu t0con pic18f8xj72 1111 1111 1111 1111 uuuu uuuu osccon pic18f8xj72 0110 q000 0110 q000 uuuu quuu lcdreg pic18f8xj72 -011 1100 -011 1000 -uuu uuuu wdtcon pic18f8xj72 0--- ---0 0--- ---0 u--- ---u rcon (4) pic18f8xj72 0-11 11q0 0-0q qquu u-uu qquu tmr1h pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu t1con pic18f8xj72 0000 0000 u0uu uuuu uuuu uuuu tmr2 pic18f8xj72 0000 0000 0000 0000 uuuu uuuu pr2 pic18f8xj72 1111 1111 1111 1111 1111 1111 t2con pic18f8xj72 -000 0000 -000 0000 -uuu uuuu sspbuf pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu sspadd pic18f8xj72 0000 0000 0000 0000 uuuu uuuu sspstat pic18f8xj72 0000 0000 0000 0000 uuuu uuuu sspcon1 pic18f8xj72 0000 0000 0000 0000 uuuu uuuu sspcon2 pic18f8xj72 0000 0000 0000 0000 uuuu uuuu table 5-2: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0 , q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 5-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as 0 . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 51 pic18f87j72 family adresh pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu adresl pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 pic18f8xj72 0-00 0000 0-00 0000 u-uu uuuu adcon1 pic18f8xj72 0-00 0000 0-00 0000 u-uu uuuu adcon2 pic18f8xj72 0-00 0000 0-00 0000 u-uu uuuu lcddata4 pic18f8xj72 ---- ---x ---- ---u ---- ---u lcddata3 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata2 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata1 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata0 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcdse4 pic18f8xj72 ---- ---0 ---- ---u ---- ---u lcdse3 pic18f8xj72 0000 0000 uuuu uuuu uuuu uuuu lcdse2 pic18f8xj72 0000 0000 uuuu uuuu uuuu uuuu lcdse1 pic18f8xj72 0000 0000 uuuu uuuu uuuu uuuu cvrcon pic18f8xj72 0000 0000 0000 0000 uuuu uuuu cmcon pic18f8xj72 0000 0111 0000 0111 uuuu uuuu tmr3h pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu tmr3l pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu t3con pic18f8xj72 0000 0000 uuuu uuuu uuuu uuuu spbrg1 pic18f8xj72 0000 0000 0000 0000 uuuu uuuu rcreg1 pic18f8xj72 0000 0000 0000 0000 uuuu uuuu txreg1 pic18f8xj72 0000 0000 0000 0000 uuuu uuuu txsta1 pic18f8xj72 0000 0010 0000 0010 uuuu uuuu rcsta1 pic18f8xj72 0000 000x 0000 000x uuuu uuuu lcdps pic18f8xj72 0000 0000 0000 0000 uuuu uuuu lcdse0 pic18f8xj72 0000 0000 uuuu uuuu uuuu uuuu lcdcon pic18f8xj72 000- 0000 000- 0000 uuu- uuuu eecon2 pic18f8xj72 ---- ---- ---- ---- ---- ---- eecon1 pic18f8xj72 ---0 x00- ---0 u00- ---0 u00- table 5-2: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0 , q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 5-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as 0 . downloaded from: http:///
pic18f87j72 family ds39979a-page 52 preliminary ? 2010 microchip technology inc. ipr3 pic18f8xj72 -111 1111 -111 1111 -uuu 1111 pir3 pic18f8xj72 -000 0000 -000 0000 -uuu 0000 (3) pie3 pic18f8xj72 -000 0000 -000 0000 -uuu 0000 ipr2 pic18f8xj72 11-- 111- 11-- 111- uu-- uuu- pir2 pic18f8xj72 00-- 000- 00-- 000- uu-- uuu- (3) pie2 pic18f8xj72 00-- 000- 00-- 000- uu-- uuu- ipr1 pic18f8xj72 -111 1-11 -111 1-11 -uuu u-uu pir1 pic18f8xj72 -000 0-00 -000 0-00 -uuu u-uu (3) pie1 pic18f8xj72 -000 0-00 -000 0-00 -uuu u-uu osctune pic18f8xj72 0000 0000 0000 0000 uuuu uuuu trisg pic18f8xj72 0001 1111 0001 1111 uuuu uuuu trisf pic18f8xj72 1111 111- 1111 111- uuuu uuu- trise pic18f8xj72 1111 1-11 1111 1-11 uuuu u-uu trisd pic18f8xj72 1111 1111 1111 1111 uuuu uuuu trisc pic18f8xj72 1111 1111 1111 1111 uuuu uuuu trisb pic18f8xj72 1111 1111 1111 1111 uuuu uuuu trisa (5) pic18f8xj72 1111 1111 (5) 1111 1111 (5) uuuu uuuu (5) latg pic18f8xj72 00-x xxxx 00-u uuuu uu-u uuuu latf pic18f8xj72 xxxx xxx- uuuu uuu- uuuu uuu- late pic18f8xj72 xxxx x-xx uuuu u-uu uuuu u-uu latd pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu latc pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu latb pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lata (5) pic18f8xj72 xxxx xxxx (5) uuuu uuuu (5) uuuu uuuu (5) portg pic18f8xj72 000x xxxx 000u uuuu 000u uuuu portf pic18f8xj72 xxxx xxx- uuuu uuu- uuuu uuu- porte pic18f8xj72 xxxx x-xx uuuu u-uu uuuu u-uu portd pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu portc pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu portb pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu porta (5) pic18f8xj72 xx0x 0000 (5) uu0u 0000 (5) uuuu uuuu (5) table 5-2: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0 , q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 5-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as 0 . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 53 pic18f87j72 family spbrgh1 pic18f8xj72 0000 0000 0000 0000 uuuu uuuu baudcon1 pic18f8xj72 0100 0-00 0100 0-00 uuuu u-uu lcddata22 pic18f8xj72 ---- ---x ---- ---u ---- ---u lcddata22 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata21 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata20 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata19 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata18 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata16 pic18f8xj72 ---- ---x ---- ---u ---- ---u lcddata16 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata15 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata14 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata13 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata12 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata10 pic18f8xj72 ---- ---x ---- ---u ---- ---u lcddata10 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata9 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata8 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata7 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu lcddata6 pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con pic18f8xj72 --00 0000 --00 0000 --uu uuuu ccpr2h pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con pic18f8xj72 --00 0000 --00 0000 --uu uuuu table 5-2: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0 , q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 5-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as 0 . downloaded from: http:///
pic18f87j72 family ds39979a-page 54 preliminary ? 2010 microchip technology inc. spbrg2 pic18f8xj72 0000 0000 0000 0000 uuuu uuuu rcreg2 pic18f8xj72 0000 0000 0000 0000 uuuu uuuu txreg2 pic18f8xj72 0000 0000 0000 0000 uuuu uuuu txsta2 pic18f8xj72 0000 -010 0000 -010 uuuu -uuu rcsta2 pic18f8xj72 0000 000x 0000 000x uuuu uuuu rtccfg pic18f8xj72 0-00 0000 0-00 0000 u-uu uuuu rtccal pic18f8xj72 0000 0000 0000 0000 uuuu uuuu rtcvalh pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu rtcvall pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu alrmcfg pic18f8xj72 0000 0000 0000 0000 uuuu uuuu alrmrpt pic18f8xj72 0000 0000 0000 0000 uuuu uuuu alrmvalh pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu alrmvall pic18f8xj72 xxxx xxxx uuuu uuuu uuuu uuuu ctmuconh pic18f8xj72 0-00 0000 0-00 0000 u-uu uuuu ctmuconl pic18f8xj72 0000 0000 0000 0000 uuuu uuuu ctmuiconh pic18f8xj72 0000 0000 0000 0000 uuuu uuuu padcfg1 pic18f8xj72 ---- -00- ---- -00- ---- -uu- table 5-2: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0 , q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 5-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as 0 . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 55 pic18f87j72 family 6.0 memory organization there are two types of memory in pic18 flash microcontroller devices: program memory data ram as harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. additional detailed information on the operation of the flash program memory is provided in section 7.0 flash program memory . 6.1 program memory organization pic18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-mbyte program memory space. accessing a location between the upper boundary of the physically implemented memory and the 2-mbyte address will return all 0 s (a nop instruction). the pic18f87j72 family has a flash program memory size of 128 kbytes (65,536 single-word instructions). the program memory maps for individual family members are shown in figure 6-1. figure 6-1: memory maps for pic18f87j72 family devices note: sizes of memory areas are not to scale. sizes of program memory areas are enhanced to show detail. unimplemented read as 0 unimplemented read as 0 000000h 1fffffh 01ffffh 00ffffh pc<20:0> stack level 1 ? stack level 31 ?? call, callw, rcall, return, retfie, retlw, 21 user memory space on-chip memory addulnk, subulnk config. words config. words pic18f86j72 pic18f87j72 on-chip memory downloaded from: http:///
pic18f87j72 family ds39979a-page 56 preliminary ? 2010 microchip technology inc. 6.1.1 hard memory vectors all pic18 devices have a total of three hard-coded return vectors in their program memory space. the reset vector address is the default value to which the program counter returns on all device resets; it is located at 0000h. pic18 devices also have two interrupt vector addresses for the handling of high-priority and low-priority interrupts. the high-priority interrupt vector is located at 0008h and the low-priority interrupt vector is at 0018h. their locations in relation to the program memory map are shown in figure 6-2. figure 6-2: hard vector and configuration word locations for pic18f87j72 family family devices 6.1.2 flash configuration words because pic18f87j72 family devices do not have per- sistent configuration memory, the top four words of on-chip program memory are reserved for configuration information. on reset, the configuration information is copied into the configuration registers. the configuration words are stored in their program memory location in numerical order, starting with the lower byte of config1 at the lowest address and end- ing with the upper byte of config4. for these devices, only configuration words, config1 through config3, are used; config4 is reserved. the actual addresses of the flash configuration word for devices in the pic18f87j72 family are shown in table 6-1. their location in the memory map is shown with the other memory vectors in figure 6-2. additional details on the device configuration words are provided in section 26.1 configuration bits . table 6-1: flash configuration word for pic18f87j72 family devices reset vector low-priority interrupt vector 0000h0018h on-chip program memory high-priority interrupt vector 0008h 1fffffh (top of memory) (top of memory-7) flash configuration words read 0 legend: (top of memory) represents upper boundary of on-chip program memory space (see figure 6-1 for device-specific values). shaded area represents unimplemented memory. areas are not shown to scale. device program memory (kbytes) configuration word addresses pic18f86j72 64 fff8h to ffffh pic18f87j72 128 1fff8h to 1ffffh downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 57 pic18f87j72 family 6.1.3 program counter the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21 bits wide and is contained in three separate 8-bit registers. the low byte, known as the pcl register, is both readable and writable. the high byte, or pch register, contains the pc<15:8> bits; it is not directly readable or writable. updates to the pch register are performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits; it is also not directly readable or writable. updates to the pcu register are performed through the pclatu register. the contents of pclath and pclatu are transferred to the program counter by any operation that writes pcl. similarly, the upper two bytes of the program counter are transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 6.1.6.1 computed goto ). the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the least significant bit (lsb) of pcl is fixed to a value of 0 . the pc increments by 2 to address sequential instructions in the program memory. the call , rcall , goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. 6.1.4 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc is pushed onto the stack when a call or rcall instruc- tion is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a return , retlw or a retfie instruction (and on addulnk and subulnk instructions if the extended instruction set is enabled). pclatu and pclath are not affected by any of the return or call instructions. the stack operates as a 31-word by 21-bit ram and a 5-bit stack pointer, stkptr. the stack space is not part of either program or data space. the stack pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of-stack special function registers. data can also be pushed to, or popped from the stack, using these registers. a call type instruction causes a push onto the stack. the stack pointer is first incremented and the location pointed to by the stack pointer is written with the contents of the pc (already pointing to the instruction following the call ). a return type instruction causes a pop from the stack. the contents of the location pointed to by the stkptr are transferred to the pc and then the stack pointer is decremented. the stack pointer is initialized to 00000 after all resets. there is no ram associated with the location corresponding to a stack pointer value of 00000 ; this is only a reset value. status bits indicate if the stack is full, has overflowed or has underflowed. 6.1.4.1 top-of-stack access only the top of the return address stack (tos) is readable and writable. a set of three registers, tosu:tosh:tosl, holds the contents of the stack location pointed to by the stkptr register (figure 6-3). this allows users to implement a software stack if necessary. after a call , rcall or interrupt (and addulnk and subulnk instructions if the extended instruction set is enabled), the software can read the pushed value by reading the tosu:tosh:tosl registers. these values can be placed on a user-defined software stack. at return time, the software can return these values to tosu:tosh:tosl and do a return. the user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. figure 6-3: return address stack and associated registers 00011 001a34h 11111 11110 11101 00010 00001 00000 00010 return address stack <20:0> top-of-stack 000d58h tosl tosh tosu 34h 1ah 00h stkptr<4:0> top-of-stack registers stack pointer downloaded from: http:///
pic18f87j72 family ds39979a-page 58 preliminary ? 2010 microchip technology inc. 6.1.4.2 return stack pointer (stkptr) the stkptr register (register 6-1) contains the stack pointer value, the stkful (stack full) status bit and the stkunf (stack underflow) status bits. the value of the stack pointer can be 0 through 31. the stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. on reset, the stack pointer value will be zero. the user may read and write the stack pointer value. this feature can be used by a real-time operating system (rtos) for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit is cleared by software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack over- flow reset enable) configuration bit. (refer to section 26.1 configuration bits for a description of the device configuration bits.) if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit and reset the device. the stkful bit will remain set and the stack pointer will be set to zero. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. any additional pushes will not overwrite the 31st push and the stkptr will remain at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and set the stkunf bit while the stack pointer remains at zero. the stkunf bit will remain set until cleared by software or until a por occurs. 6.1.4.3 push and pop instructions since the top-of-stack is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execu- tion, is a desirable feature. the pic18 instruction set includes two instructions, push and pop , that permit the tos to be manipulated under software control. tosu, tosh and tosl can be modified to place data or a return address on the stack. the push instruction places the current pc value onto the stack. this increments the stack pointer and loads the current pc value onto the stack. the pop instruction discards the current tos by decrementing the stack pointer. the previous value pushed onto the stack then becomes the tos value. note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appropriate actions can be taken. this is not the same as a reset, as the contents of the sfrs are not affected. register 6-1: stkptr: stack pointer register r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful (1) stkunf (1) sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 stkful: stack full flag bit (1) 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf: stack underflow flag bit (1) 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented: read as 0 bit 4-0 sp<4:0>: stack pointer location bits note 1: bit 7 and bit 6 are cleared by user software or by a por. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 59 pic18f87j72 family 6.1.4.4 stack full and underflow resets device resets on stack overflow and stack underflow conditions are enabled by setting the stvren bit in configuration register 1l. when stvren is set, a full or underflow condition will set the appropriate stkful or stkunf bit and then cause a device reset. when stvren is cleared, a full or underflow condition will set the appropriate stkful or stkunf bit, but not cause a device reset. the stkful or stkunf bits are cleared by the user software or a power-on reset. 6.1.5 fast register stack a fast register stack is provided for the status, wreg and bsr registers to provide a fast return option for interrupts. this stack is only one level deep and is neither readable nor writable. it is loaded with the current value of the corresponding register when the processor vectors for an interrupt. all interrupt sources will push values into the stack registers. the values in the registers are then loaded back into the working registers if the retfie , fast instruction is used to return from the interrupt. if both low and high-priority interrupts are enabled, the stack registers cannot be used reliably to return from low-priority interrupts. if a high-priority interrupt occurs while servicing a low-priority interrupt, the stack register values stored by the low-priority interrupt will be overwritten. in these cases, users must save the key registers in software during a low-priority interrupt. if interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a call label , fast instruction must be executed to save the status, wreg and bsr registers to the fast register stack. a return , fast instruction is then executed to restore these registers from the fast register stack. example 6-1 shows a source code example that uses the fast register stack during a subroutine call and return. example 6-1: fast register stack code example 6.1.6 look-up tables in program memory there may be programming situations that require the creation of data structures, or look-up tables, in program memory. for pic18 devices, look-up tables can be implemented in two ways: computed goto table reads 6.1.6.1 computed goto a computed goto is accomplished by adding an offset to the program counter. an example is shown in example 6-2. a look-up table can be formed with an addwf pcl instruction and a group of retlw nn instructions. the w register is loaded with an offset into the table before executing a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw nn instructions that returns the value nn to the calling function. the offset value (in wreg) specifies the number of bytes that the program counter should advance and should be multiples of 2 (lsb = 0 ). in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. example 6-2: computed goto using an offset value 6.1.6.2 table reads a better method of storing data in program memory allows two bytes of data to be stored in each instruction location. look-up table data may be stored, two bytes per program word, while programming. the table pointer (tblptr) specifies the byte address and the table latch (tablat) contains the data that is read from the program memory. data is transferred from program memory, one byte at a time. table read operation is discussed further in section 7.1 table reads and table writes . call sub1, fast ;status, wreg, bsr ;saved in fast register;stack ?? sub1 ?? return fast ;restore values saved ;in fast register stack movf offset, w call table org nn00h table addwf pcl retlw nnh retlw nnh retlw nnh . . . downloaded from: http:///
pic18f87j72 family ds39979a-page 60 preliminary ? 2010 microchip technology inc. 6.2 pic18 instruction cycle 6.2.1 clocking scheme the microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (q1, q2, q3 and q4). internally, the program counter is incremented on every q1; the instruction is fetched from the program memory and latched into the instruction register (ir) during q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 6-4. 6.2.2 instruction flow/pipelining an instruction cycle consists of four q cycles, q1 through q4. the instruction fetch and execute are pipe- lined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 6-3). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 6-4: clock/instruction cycle example 6-3: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1q2 q3 q4 pc osc2/clko (rc mode) pc pc + 2 pc + 4 fetch inst (pc) execute inst (pc C 2) fetch inst (pc + 2) execute inst (pc) fetch inst (pc + 4) execute inst (pc + 2) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles sin ce the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush ( nop ) 5. instruction @ address sub_1 fetch sub_1 execute sub_1 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 61 pic18f87j72 family 6.2.3 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte (lsb) of an instruction word is always stored in a program memory location with an even address (lsb = 0 ). to maintain alignment with instruction boundaries, the pc incre- ments in steps of 2 and the lsb will always read 0 (see section 6.1.3 program counter ). figure 6-5 shows an example of how instruction words are stored in the program memory. the call and goto instructions have the absolute program memory address embedded into the instruc- tion. since instructions are always stored on word boundaries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in figure 6-5 shows how the instruction, goto 0006h , is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a branch instruction represents the number of single-word instructions that the pc will be offset by. section 27.0 instruction set summary provides further details of the instruction set. figure 6-5: instructions in program memory 6.2.4 two-word instructions the standard pic18 instruction set has four two-word instructions: call , movff , goto and lsfr . in all cases, the second word of the instructions always has 1111 as its four most significant bits; the other 12 bits are literal data, usually a data memory address. the use of 1111 in the 4 msbs of an instruction specifies a special form of nop . if the instruction is executed in proper sequence C immediately after the first word C the data in the second word is accessed and used by the instruction sequence. if the first word is skipped for some reason and the second word is executed by itself, a nop is executed instead. this is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the pc. example 6-4 shows how this works. example 6-4: two-word instructions word address lsb = 1 lsb = 0 ? program memory byte locations ? ? 000000h000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 0006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h000014h note: see section 6.5 program memory and the extended instruction set for information on two-word instructions in the extended instruction set. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, skip this word 1111 0100 0101 0110 ; execute this word as a nop 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 addwf reg3 ; continue code downloaded from: http:///
pic18f87j72 family ds39979a-page 62 preliminary ? 2010 microchip technology inc. 6.3 data memory organization the data memory in pic18 devices is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4,096 bytes of data memory. the memory space is divided into as many as 16 banks that contain 256 bytes each. pic18f86j72 and pic18f87j72 devices implement all 16 complete banks, for a total of 4 kbytes. figure 6-6 and figure 6-7 show the data memory organization for the devices. the data memory contains special function registers (sfrs) and general purpose registers (gprs). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratchpad operations in the users application. any read of an unimplemented location will read as 0 s. the instruction set and architecture allow operations across all banks. the entire data memory may be accessed by direct, indirect or indexed addressing modes. addressing modes are discussed later in this section. to ensure that commonly used registers (select sfrs and select gprs) can be accessed in a single cycle, pic18 devices implement an access bank. this is a 256-byte memory space that provides fast access to select sfrs and the lower portion of gpr bank 0 with- out using the bsr. section 6.3.2 access bank provides a detailed description of the access ram. 6.3.1 bank select register large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. ideally, this means that an entire address does not need to be provided for each read or write operation. for pic18 devices, this is accom- plished with a ram banking scheme. this divides the memory space into 16 contiguous banks of 256 bytes. depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit bank pointer. most instructions in the pic18 instruction set make use of the bank pointer, known as the bank select register (bsr). this sfr holds the 4 most significant bits of a locations address; the instruction itself includes the 8 least significant bits. only the four lower bits of the bsr are implemented (bsr<3:0>). the upper four bits are unused; they will always read 0 and cannot be written to. the bsr can be loaded directly by using the movlb instruction. the value of the bsr indicates the bank in data memory. the 8 bits in the instruction show the location in the bank and can be thought of as an offset from the banks lower boundary. the relationship between the bsrs value and the bank division in data memory is shown in figure 6-7. since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. for example, writing what should be program data to an 8-bit address of f9h while the bsr is 0fh, will end up resetting the program counter. while any bank can be selected, only those banks that are actually implemented can be read or written to. writes to unimplemented banks are ignored, while reads from unimplemented banks will return 0 s. even so, the status register will still be affected as if the operation was successful. the data memory map in figure 6-6 indicates which banks are implemented. in the core pic18 instruction set, only the movff instruction fully specifies the 12-bit address of the source and target registers. this instruction ignores the bsr completely when it executes. all other instructions include only the low-order address as an operand and must use either the bsr or the access bank to locate their target registers. note: the operation of some aspects of data memory are changed when the pic18 extended instruction set is enabled. see section 6.6 data memory and the extended instruction set for more information. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 63 pic18f87j72 family figure 6-6: data memory map for pic18f86j72 and pic18f87j72 devices 00h 5fh 60h ffh access bank when a = 0 : the bsr is ignored and the access bank is used. the first 96 bytes are general purpose ram (from bank 0). the second 160 bytes are special function registers (from bank 15). when a = 1 : the bsr specifies the bank used by the instruction. access ram high access ram low (sfrs) bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1111 060h 05fh f60h fffh f5fh f00h effh 1ffh 100h 0ffh 000h access ram ffh 00h ffh 00h ffh 00h gpr gpr sfr bank 2 = 0010 2ffh 200h bank 3 ffh 00h gpr ffh = 0011 gpr (1) gpr gprgpr gpr gpr 4ffh 400h 5ffh 500h 3ffh 300h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h 00h = 0110 = 0111 = 0101 = 0100 bank 4 bank 5 bank 6 bank 7 bank 8 = 1110 6ffh 600h 7ffh 700h 800h bank 9 bank 10 bank 11 bank 12 bank 13 8ffh 900h 9ffh a00h affh b00h bffh c00h cffh d00h dffh e00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h gpr gpr gpr gpr gpr gpr gpr note 1: addresses, f5ah through f5fh, are also used by sfrs, but are not part of the access ram. users must always use the complete address, or load the proper sbr value, to access these registers. = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 downloaded from: http:///
pic18f87j72 family ds39979a-page 64 preliminary ? 2010 microchip technology inc. figure 6-7: use of the bank select register (direct addressing) 6.3.2 access bank while the use of the bsr with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. otherwise, data may be read from, or written to, the wrong location. this can be disastrous if a gpr is the intended target of an oper- ation, but an sfr is written to instead. verifying and/or changing the bsr for each read or write to data memory can become very inefficient. to streamline access for the most commonly used data memory locations, the data memory is configured with an access bank, which allows users to access a mapped block of memory without specifying a bsr. the access bank consists of the first 96 bytes of memory (00h-5fh) in bank 0 and the last 160 bytes of memory (60h-ffh) in bank 15. the lower half is known as the access ram and is composed of gprs. the upper half is where the devices sfrs are mapped. these two areas are mapped contiguously in the access bank and can be addressed in a linear fashion by an 8-bit address (figure 6-6). the access bank is used by core pic18 instructions that include the access ram bit (the a parameter in the instruction). when a is equal to 1 , the instruction uses the bsr and the 8-bit address included in the opcode for the data memory address. when a is 0 , however, the instruction is forced to use the access bank address map; the current value of the bsr is ignored entirely. using this forced addressing allows the instruction to operate on a data address in a single cycle without updating the bsr first. for 8-bit addresses of 60h and above, this means that users can evaluate and operate on sfrs more efficiently. the access ram below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. access ram also allows for faster and more code efficient context saving and switching of variables. the mapping of the access bank is slightly different when the extended instruction set is enabled (xinst configuration bit = 1 ). this is discussed in more detail in section 6.6.3 mapping the access bank in indexed literal offset mode . 6.3.3 general purpose register file pic18 devices may have banked memory in the gpr area. this is data ram which is available for use by all instructions. gprs start at the bottom of bank 0 (address 000h) and grow upwards towards the bottom of the sfr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. note 1: the access ram bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 2: the movff instruction embeds the entire 12-bit address in the instruction. data memory bank select (2) 7 0 from opcode (2) 0000 000h100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh bank 3 through bank 13 0010 11111111 7 0 bsr (1) 11111111 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 65 pic18f87j72 family 6.3.4 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. sfrs start at the top of data memory (fffh) and extend downward to occupy more than the top half of bank 15 (f60h to fffh). a list of these registers is given in table 6-2 and table 6-3. the sfrs can be classified into two sets: those associated with the core device functionality (alu, resets and interrupts) and those related to the peripheral functions. the reset and interrupt registers are described in their respective chapters, while the alus status register is described later in this section. registers related to the operation of the peripheral features are described in t he chapter for that peripheral. the sfrs are typically distributed among the peripherals whose functions they control. unused sfr locations are unimplemented and read as 0 s. table 6-2: special function register map for pic18f87j72 family devices addr. name addr. name addr. name addr. name addr. name addr. name fffh tosu fdfh indf2 (1) fbfh lcddata4 f9fh ipr1 f7fh spbrgh1 f5fh rtccfg ffeh tosh fdeh postinc2 (1) fbeh lcddata3 f9eh pir1 f7eh baudcon1 f5eh rtccal ffdh tosl fddh postdec2 (1) fbdh lcddata2 f9dh pie1 f7dh (2) f5dh rtcvalh ffch stkptr fdch preinc2 (1) fbch lcddata1 f9ch (2) f7ch lcddata22 f5ch rtcvall ffbh pclatu fdbh plusw2 (1) fbbh lcddata0 f9bh osctune f7bh lcddata21 f5bh alrmcfg ffah pclath fdah fsr2h fbah (2) f9ah trisj f7ah lcddata20 f5ah alrmrpt ff9h pcl fd9h fsr2l fb9h lcdse4 f99h trish f79h lcddata19 f59h alrmvalh ff8h tblptru fd8h status fb8h lcdse3 f98h trisg f78h lcddata18 f58h alrmvall ff7h tblptrh fd7h tmr0h fb7h lcdse2 f97h trisf f77h (2) f57h ctmuconh ff6h tblptrl fd6h tmr0l fb6h lcdse1 f96h trise f76h lcddata16 f56h ctmuconl ff5h tablat fd5h t0con fb5h cvrcon f95h trisd f75h lcddata15 f55h ctmuiconh ff4h prodh fd4h (2) fb4h cmcon f94h trisc f74h lcddata14 f54h padcfg1 ff3h prodl fd3h osccon fb3h tmr3h f93h trisb f73h lcddata13 ff2h intcon fd2h lcdreg fb2h tmr3l f92h trisa f72h lcddata12 ff1h intcon2 fd1h wdtcon fb1h t3con f91h latj f71h (2) ff0h intcon3 fd0h rcon fb0h (2) f90h lath f70h lcddata10 fefh indf0 (1) fcfh tmr1h fafh spbrg1 f8fh latg f6fh lcddata9 feeh postinc0 (1) fceh tmr1l faeh rcreg1 f8eh latf f6eh lcddata8 fedh postdec0 (1) fcdh t1con fadh txreg1 f8dh late f6dh lcddata7 fech preinc0 (1) fcch tmr2 fach txsta1 f8ch latd f6ch lcddata6 febh plusw0 (1) fcbh pr2 fabh rcsta1 f8bh latc f6bh (2) feah fsr0h fcah t2con faah lcdps f8ah latb f6ah ccpr1h fe9h fsr0l fc9h sspbuf fa9h lcdse0 f89h lata f69h ccpr1l fe8h wreg fc8h sspadd fa8h lcdcon f88h portj f68h ccp1con fe7h indf1 (1) fc7h sspstat fa7h eecon2 f87h porth f67h ccpr2h fe6h postinc1 (1) fc6h sspcon1 fa6h eecon1 f86h portg f66h ccpr2l fe5h postdec1 (1) fc5h sspcon2 fa5h ipr3 f85h portf f65h ccp2con fe4h preinc1 (1) fc4h adresh fa4h pir3 f84h porte f64h spbrg2 fe3h plusw1 (1) fc3h adresl fa3h pie3 f83h portd f63h rcreg2 fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc f62h txreg2 fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb f61h txsta2 fe0h bsr fc0h adcon2 fa0h pie2 f80h porta f60h rcsta2 note 1: this is not a physical register. 2: unimplemented registers are read as 0 . downloaded from: http:///
pic18f87j72 family ds39979a-page 66 preliminary ? 2010 microchip technology inc. table 6-3: pic18f87j72 family register file summary file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page tosu top-of-stack upper byte (tos<20:16>) ---0 0000 49, 57 tosh top-of-stack high byte (tos<15:8>) 0000 0000 49, 57 tosl top-of-stack low byte (tos<7:0>) 0000 0000 49, 57 stkptr stkful stkunf return stack pointer uu-0 0000 49, 58 pclatu b i t 2 1 (1) holding register for pc<20:16> ---0 0000 49, 57 pclath holding register for pc<15:8> 0000 0000 49, 57 pcl pc low byte (pc<7:0>) 0000 0000 49, 57 tblptru bit 21 program memory table pointer upper byte (tblptr<20:16>) --00 0000 49, 80 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 49, 80 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 49, 80 tablat program memory table latch 0000 0000 49, 80 prodh product register high byte xxxx xxxx 49, 87 prodl product register low byte xxxx xxxx 49, 87 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 49, 91 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 1111 1111 49, 92 intcon3 int2ip int1ip int3ie int 2ie int1ie int3if int2if int1if 1100 0000 49, 93 indf0 uses contents of fsr0 to address data memory C value of fsr0 not changed (not a physical register) n/a 49, 72 postinc0 uses contents of fsr0 to address data memory C value of fsr0 post-incremented (not a physica l register) n/a 49, 73 postdec0 uses contents of fsr0 to address data memory C value of fsr0 post-decremented (not a physical regis ter) n/a 49, 73 preinc0 uses contents of fsr0 to address data memory C value of fsr0 pre-incremented (not a physical register) n/a 49, 73 plusw0 uses contents of fsr0 to address data memory C value of fsr0 pre-incremented (not a physical register) C value of fsr0 offset by w n/a 49, 73 fsr0h indirect data memory address pointer 0 high byte ---- xxxx 49, 72 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx 49, 72 wreg working register xxxx xxxx 49 indf1 uses contents of fsr1 to address data memory C value of fsr1 not changed (not a physical register) n/a 49, 72 postinc1 uses contents of fsr1 to address data memory C value of fsr1 post-incremented (not a physica l register) n/a 49, 73 postdec1 uses contents of fsr1 to address data memory C value of fsr1 post-decremented (not a physical regis ter) n/a 49, 73 preinc1 uses contents of fsr1 to address data memory C value of fsr1 pre-incremented (not a physical register) n/a 49, 73 plusw1 uses contents of fsr1 to address data memory C value of fsr1 pre-incremented (not a physical register) C value of fsr1 offset by w n/a 49, 73 fsr1h indirect data memory address pointer 1 high byte ---- xxxx 50, 72 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx 50, 72 bsr bank select register ---- 0000 50, 62 indf2 uses contents of fsr2 to address data memory C value of fsr2 not changed (not a physical register) n/a 50, 72 postinc2 uses contents of fsr2 to address data memory C value of fsr2 post-incremented (not a physica l register) n/a 50, 73 postdec2 uses contents of fsr2 to address data memory C value of fsr2 post-decremented (not a physical regis ter) n/a 50, 73 preinc2 uses contents of fsr2 to address data memory C value of fsr2 pre-incremented (not a physical register) n/a 50, 73 plusw2 uses contents of fsr2 to address data memory C value of fsr2 pre-incremented (not a physical register) C value of fsr2 offset by w n/a 50, 73 fsr2h indirect data memory address pointer 2 high byte ---- xxxx 50, 72 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx 50, 72 status no vzd cc ---x xxxx 50, 70 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify note 1: bit 21 of the pc is only available in test mode and serial programming modes. 2: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. see section 18.4.3.2 address masking for details. 3: the pllen bit is only available in specific oscillator configurations; ot herwise, it is disabled and reads as 0 . see section 3.4.3 pll frequency multiplier for details. 4: ra<7:6> and their associated latch and direction bits are configured as port pins only when the internal osc illator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as 0 . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 67 pic18f87j72 family tmr0h timer0 register high byte 0000 0000 50, 125 tmr0l timer0 register low byte xxxx xxxx 50, 125 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 50, 123 osccon idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 0110 q000 26, 50 lcdreg cpen bias2 bias1 bias0 mode13 cksel1 cksel0 -011 1100 50, 173 wdtcon regslp s w d t e n 0--- ---0 50, 326 rcon ipen c m ri to pd por bor 0-11 11q0 44, 50 tmr1h timer1 register high byte xxxx xxxx 50, 131 tmr1l timer1 register low byte xxxx xxxx 50, 131 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 50, 127 tmr2 timer2 register 0000 0000 50, 134 pr2 timer2 period register 1111 1111 50, 134 t2con t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 -000 0000 50, 133 sspbuf mssp receive buffer/transmit register xxxx xxxx 50, 203, 238 sspadd mssp address register in i 2 c? slave mode. mssp1 baud rate reload register in i 2 c master mode. 0000 0000 50, 238 sspstat smp cke d/a psr / w ua bf 0000 0000 50, 196, 205 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 50, 197, 206 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 50, 207, 208 gcen ackstat admsk5 (2) admsk4 (2) admsk3 (2) admsk2 (2) admsk1 (2) sen adresh a/d result register high byte xxxx xxxx 51, 281 adresl a/d result register low byte xxxx xxxx 51, 281 adcon0 adcal chs3 chs2 chs1 chs0 go/done adon 0-00 0000 51, 273 adcon1 trigsel vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0-00 0000 51, 274 adcon2 adfm acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 51, 275 lcddata4 s32c0 xxxx xxxx 51, 171 lcddata3 s31c0 s30c0 s29c0 s28c0 s27c0 s26c0 s25c0 s24c0 xxxx xxxx 51, 171 lcddata2 s23c0 s22c0 s21c0 s20c0 s19c0 s18c0 s17c0 s16c0 xxxx xxxx 51, 171 lcddata1 s15c0 s14c0 s13c0 s12c0 s11c0 s10c0 s09c0 s08c0 xxxx xxxx 51, 171 lcddata0 s07c0 s06c0 s05c0 s04c0 s03c0 s02c0 s01c0 s00c0 xxxx xxxx 51, 171 lcdse4 s e 3 2 0000 0000 51, 171 lcdse3 se31 se30 se29 se28 se27 se26 se25 se24 0000 0000 51, 171 lcdse2 se23 se22 se21 se20 se19 se18 se17 se16 0000 0000 51, 171 lcdse1 se15 se14 se13 se12 se11 se10 se09 se08 0000 0000 51, 171 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 51, 299 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 51, 293 tmr3h timer3 register high byte xxxx xxxx 51, 137 tmr3l timer3 register low byte xxxx xxxx 51, 137 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 51, 135 table 6-3: pic18f87j72 family register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify note 1: bit 21 of the pc is only available in test mode and serial programming modes. 2: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. see section 18.4.3.2 address masking for details. 3: the pllen bit is only available in specific oscillator configurations; ot herwise, it is disabled and reads as 0 . see section 3.4.3 pll frequency multiplier for details. 4: ra<7:6> and their associated latch and direction bits are configured as port pins only when the internal osc illator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as 0 . downloaded from: http:///
pic18f87j72 family ds39979a-page 68 preliminary ? 2010 microchip technology inc. spbrg1 eusart baud rate generator low byte 0000 0000 51, 243 rcreg1 eusart receive register 0000 0000 51, 251 txreg1 eusart transmit register 0000 0000 51, 249 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 51, 240 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 51, 241 lcdps wft biasmd lcda wa lp3 lp2 lp1 lp0 0000 0000 51, 169 lcdse0 se07 se06 se05 se04 se03 se02 se01 se00 0000 0000 51, 170 lcdcon lcden slpen werr cs1 cs0 lmux1 lmux0 000- 0000 51, 168 eecon2 eeprom control register 2 (not a physical register) ---- ---- 51, 78 eecon1 wprog free wrerr wren wr --00 x00- 51, 78 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip -111 1111 52, 102 pir3 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif -000 0000 52, 96 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie -000 0000 52, 99 ipr2 oscfip cmip bclip lvdip tmr3ip 11-- 111- 52, 101 pir2 oscfif cmif b c l i fl v d i ft m r 3 i f 00-- 000- 52, 95 pie2 oscfie cmie bclie lvdie tmr3ie 00-- 000- 52, 98 ipr1 adip rc1ip tx1ip sspip tmr2ip tmr1ip -111 1-11 52, 100 pir1 adif rc1if tx1if sspif tmr2if tmr1if -000 0-00 52, 94 pie1 adie rc1ie tx1ie sspie tmr2ie tmr1ie -000 0-00 52, 97 osctune intsrc pllen (3) tun5 tun4 tun3 tun2 tun1 tun0 0000 0000 27, 52 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 0001 1111 52, 122 t r i s f t r i s f 7t r i s f 6t r i s f 5t r i s f 4t r i s f 3t r i s f 2t r i s f 1 1111 111- 52, 120 trise trise7 trise6 trise5 trise4 trise3 trise1 trise0 1111 1-11 52, 117 t r i s d t r i s d 7t r i s d 6t r i s d 5t r i s d 4t r i s d 3t r i s d 2t r i s d 1t r i s d 0 1111 1111 52, 115 t r i s c t r i s c 7t r i s c 6t r i s c 5t r i s c 4t r i s c 3t r i s c 2t r i s c 1t r i s c 0 1111 1111 52, 113 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 52, 110 trisa trisa7 (4) trisa6 (4) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 52, 107 latg u2od u1od latg4 latg3 latg2 latg1 latg0 00-x xxxx 52, 122 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 xxxx xxx- 52, 120 late late7 late6 late5 late4 late3 l a t e 1l a t e 0 xxxx x-xx 52, 117 latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx xxxx 52, 115 latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 xxxx xxxx 52, 113 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx xxxx 52, 110 lata lata7 (4) lata6 (4) lata5 lata4 lata3 lata2 lata1 lata0 xxxx xxxx 52, 107 portg rdpu repu rjpu (2) r g 4r g 3r g 2r g 1r g 0 000x xxxx 52, 122 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 xxxx xxx- 52, 120 porte re7 re6 re5 re4 re3 r e 1r e 0 xxxx x-xx 52, 117 portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx 52, 115 portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx 52, 113 portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx 52, 110 porta ra7 (4) ra6 (4) r a 5r a 4r a 3r a 2r a 1r a 0 xx0x 0000 52, 107 table 6-3: pic18f87j72 family register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify note 1: bit 21 of the pc is only available in test mode and serial programming modes. 2: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. see section 18.4.3.2 address masking for details. 3: the pllen bit is only available in specific oscillator configurations; ot herwise, it is disabled and reads as 0 . see section 3.4.3 pll frequency multiplier for details. 4: ra<7:6> and their associated latch and direction bits are configured as port pins only when the internal osc illator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as 0 . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 69 pic18f87j72 family spbrgh1 eusart baud rate generator high byte 0000 0000 53, 243 baudcon1 abdovf rcmt rxdtp txckp brg16 w u ea b d e n 0100 0-00 53, 242 lcddata22 s32c3 xxxx xxxx 53, 171 lcddata21 s31c3 s30c3 s29c3 s28c3 s27c3 s26c3 s25c3 s24c3 xxxx xxxx 53, 171 lcddata20 s23c3 s22c3 s21c3 s20c3 s19c3 s18c3 s17c3 s16c3 xxxx xxxx 53, 171 lcddata19 s15c3 s14c3 s13c3 s12c3 s11c3 s10c3 s09c3 s08c3 xxxx xxxx 53, 171 lcddata18 s07c3 s06c3 s05c3 s04c3 s03c3 s02c3 s01c3 s00c3 xxxx xxxx 53, 171 lcddata16 s32c2 xxxx xxxx 53, 171 lcddata15 s31c2 s30c2 s29c2 s28c2 s27c2 s26c2 s25c2 s24c2 xxxx xxxx 53, 171 lcddata14 s23c2 s22c2 s21c2 s20c2 s19c2 s18c2 s17c2 s16c2 xxxx xxxx 53, 171 lcddata13 s15c2 s14c2 s13c2 s12c2 s11c2 s10c2 s09c2 s08c2 xxxx xxxx 53, 171 lcddata12 s07c2 s06c2 s05c2 s04c2 s03c2 s02c2 s01c2 s00c2 xxxx xxxx 53, 171 lcddata10 s32c1 xxxx xxxx 53, 171 lcddata9 s31c1 s30c1 s29c1 s28c1 s27c1 s26c1 s25c1 s24c1 xxxx xxxx 53, 171 lcddata8 s23c1 s22c1 s21c1 s20c1 s19c1 s18c1 s17c1 s16c1 xxxx xxxx 53, 171 lcddata7 s15c1 s14c1 s13c1 s12c1 s11c1 s10c1 s09c1 s08c1 xxxx xxxx 53, 171 lcddata6 s07c1 s06c1 s05c1 s04c1 s03c1 s02c1 s01c1 s00c1 xxxx xxxx 53, 171 ccpr1h capture/compare/pwm register 1 high byte xxxx xxxx 53, 158 ccpr1l capture/compare/pwm register 1 low byte xxxx xxxx 53, 158 ccp1con dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 53, 157 ccpr2h capture/compare/pwm register 2 high byte xxxx xxxx 53, 158 ccpr2l capture/compare/pwm register 2 low byte xxxx xxxx 53, 158 ccp2con dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 53, 157 spbrg2 ausart baud rate generator register 0000 0000 54, 262 rcreg2 ausart receive register 0000 0000 54, 267 txreg2 ausart transmit register 0000 0000 54, 265 txsta2 csrc tx9 txen sync brgh trmt tx9d 0000 -010 54, 260 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 54, 261 rtccfg rtcen rtcwren rtcsync halfsec rtcoe rtcptr1 rtcptr0 0-00 0000 54, 141 rtccal cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 0000 0000 54, 142 rtcvalh rtcc value high register window based on rtcptr<1:0> xxxx xxxx 54, 144 rtcvall rtcc value low register window based on rtcptr<1:0> xxxx xxxx 54, 144 alrmcfg alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 0000 0000 54, 143 alrmrpt arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 0000 0000 54, 144 alrmvalh alarm value high register window based on alrmptr<1:0> xxxx xxxx 54, 147 alrmvall alarm value low register window based on alrmptr<1:0> xxxx xxxx 54, 147 ctmuconh ctmuen ctmusidl tgen edgen edgseqen idissen cttrig 0-00 0000 54, 315 ctmuconl edg2pol edg2sel1 edg2sel0 edg1pol edg1sel1 edg1sel0 edg2stat e dg1stat 0000 0000 54, 316 ctmuicon itrim5 itrim4 itrim3 itrim2 itrim1 itrim0 irng1 irng0 0000 0000 54, 317 padcfg1 rtsecsel1 rtsecsel0 ---- -00- 54, 142 table 6-3: pic18f87j72 family register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify note 1: bit 21 of the pc is only available in test mode and serial programming modes. 2: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. see section 18.4.3.2 address masking for details. 3: the pllen bit is only available in specific oscillator configurations; ot herwise, it is disabled and reads as 0 . see section 3.4.3 pll frequency multiplier for details. 4: ra<7:6> and their associated latch and direction bits are configured as port pins only when the internal osc illator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as 0 . downloaded from: http:///
pic18f87j72 family ds39979a-page 70 preliminary ? 2010 microchip technology inc. 6.3.5 status register the status register, shown in register 6-2, contains the arithmetic status of the alu. the status register can be the operand for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc, c, ov or n bits, then the write to these five bits is disabled. these bits are set or cleared according to the device logic. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will set the z bit but leave the other bits unchanged. the status register then reads back as 000u u1uu . it is recom- mended, therefore, that only bcf, bsf, swapf, movff and movwf instructions are used to alter the status register because these instructions do not affect the z, c, dc, ov or n bits in the status register. for other instructions not affecting any status bits, see the instruction set summaries in table 27-2 and table 27-3. note: the c and dc bits operate as a borrow and digit borrow bit respectively, in subtraction. register 6-2: status register u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x no vzd c (1) c (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as 0 bit 4 n: negative bit this bit is used for signed arithmetic (2s complement). it indicates whether the result was negative (alu msb = 1 ). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2s complement). it indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit (1) for addwf, addlw, sublw and subwf instructions: 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (2) for addwf, addlw, sublw and subwf instructions: 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow, the polarity is reversed. a subtraction is ex ecuted by adding the 2s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with eit her bit 4 or bit 3 of the source register. 2: for borrow, the polarity is reversed. a subtraction is executed by adding the 2s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low-order bit of the source register. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 71 pic18f87j72 family 6.4 data addressing modes while the program memory can be addressed in only one way C through the program counter C information in the data memory space can be addressed in several ways. for most instructions, the addressing mode is fixed. other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. the addressing modes are: inherent literal direct indirect an additional addressing mode, indexed literal offset, is available when the extended instruction set is enabled (xinst configuration bit = 1 ). its operation is discussed in greater detail in section 6.6.1 indexed addressing with literal offset . 6.4.1 inherent and literal addressing many pic18 control instructions do not need any argument at all; they either perform an operation that globally affects the device, or they operate implicitly on one register. this addressing mode is known as inherent addressing. examples include sleep , reset and daw . other instructions work in a similar way, but require an additional explicit argument in the opcode. this is known as literal addressing mode, because they require some literal value as an argument. examples include addlw and movlw , which respectively, add or move a literal value to the w register. other examples include call and goto , which include a 20-bit program memory address. 6.4.2 direct addressing direct addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. the options are specified by the arguments accompanying the instruction. in the core pic18 instruction set, bit-oriented and byte-oriented instructions use some version of direct addressing by default. all of these instructions include some 8-bit literal address as their least significant byte. this address specifies either a register address in one of the banks of data ram ( section 6.3.3 general purpose register file ) or a location in the access bank ( section 6.3.2 access bank ) as the data source for the instruction. the access ram bit, a, determines how the address is interpreted. when a is 1 , the contents of the bsr ( section 6.3.1 bank select register ) are used with the address to determine the complete 12-bit address of the register. when a is 0 , the address is interpreted as being a register in the access bank. addressing that uses the access ram is sometimes also known as direct forced addressing mode. a few instructions, such as movff , include the entire 12-bit address (either source or destination) in their opcodes. in these cases, the bsr is ignored entirely. the destination of the operations results is determined by the destination bit, d. when d is 1 , the results are stored back in the source register, overwriting its origi- nal contents. when d is 0 , the results are stored in the w register. instructions without the d argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the w register. 6.4.3 indirect addressing indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction. this is done by using file select registers (fsrs) as pointers to the locations to be read or written to. since the fsrs are themselves located in ram as special function registers, they can also be directly manipulated under program control. this makes fsrs very useful in implementing data structures such as tables and arrays in data memory. the registers for indirect addressing are also implemented with indirect file operands (indfs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. this allows for efficient code using loops, such as the example of clearing an entire ram bank in example 6-5. it also enables users to perform indexed addressing and other stack pointer operations for program memory in data memory. example 6-5: how to clear ram (bank 1) using indirect addressing note: the execution of some instructions in the core pic18 instruction set are changed when the pic18 extended instruction set is enabled. see section 6.6 data memory and the extended instruction set for more information. lfsr fsr0, 100h ; next clrf postinc0 ; clear indf ; register then ; inc pointer btfss fsr0h, 1 ; all done with ; bank1? bra next ; no, clear next continue ; yes, continue downloaded from: http:///
pic18f87j72 family ds39979a-page 72 preliminary ? 2010 microchip technology inc. 6.4.3.1 fsr registers and the indf operand at the core of indirect addressing are three sets of registers: fsr0, fsr1 and fsr2. each represents a pair of 8-bit registers, fsrnh and fsrnl. the four upper bits of the fsrnh register are not used, so each fsr pair holds a 12-bit value. this represents a value that can address the entire range of the data memory in a linear fashion. the fsr register pairs, then, serve as pointers to data memory locations. indirect addressing is accomplished with a set of indi- rect file operands, indf0 through indf2. these can be thought of as virtual registers: they are mapped in the sfr space but are not physically implemented. reading or writing to a particular indf register actually accesses its corresponding fsr register pair. a read from indf1, for example, reads the data at the address indicated by fsr1h:fsr1l. instructions that use the indf registers as operands actually use the contents of their corresponding fsr as a pointer to the instruc- tions target. the indf operand is just a convenient way of using the pointer. because indirect addressing uses a full 12-bit address, data ram banking is not necessary. thus, the current contents of the bsr and the access ram bit have no effect on determining the target address. figure 6-8: indirect addressing fsr1h:fsr1l 0 7 data memory 000h100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 bank 3 through bank 13 addwf, indf1, 1 0 7 using an instruction with one of the indirect addressing registers as the operand.... ...uses the 12-bit address stored in the fsr pair associated with that register.... ...to determine the data memory location to be used in that operation. in this case, the fsr1 pair contains fcch. this means the contents of location, fcch, will be added to that of the w register and stored back in fcch. xxxx 1111 11001100 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 73 pic18f87j72 family 6.4.3.2 fsr registers and postinc, postdec, preinc and plusw in addition to the indf operand, each fsr register pair also has four additional indirect operands. like indf, these are virtual registers that cannot be indirectly read or written to. accessing these registers actually accesses the associated fsr register pair, but also performs a specific action on its stored value. they are: postdec: accesses the fsr value, then automatically decrements it by 1 afterwards postinc: accesses the fsr value, then automatically increments it by 1 afterwards preinc: increments the fsr value by 1 , then uses it in the operation plusw: adds the signed value of the w register (range of -127 to 128) to that of the fsr and uses the new value in the operation in this context, accessing an indf register uses the value in the fsr registers without changing them. similarly, accessing a plusw register gives the fsr value offset by the value in the w register; neither value is actually changed in the operation. accessing the other virtual registers changes the value of the fsr registers. operations on the fsrs with postdec, postinc and preinc affect the entire register pair; that is, roll- overs of the fsrnl register from ffh to 00h carry over to the fsrnh register. on the other hand, results of these operations do not change the value of any flags in the status register (e.g., z, n, ov, etc.). the plusw register can be used to implement a form of indexed addressing in the data memory space. by manipulating the value in the w register, users can reach addresses that are fixed offsets from pointer addresses. in some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 6.4.3.3 operations by fsrs on fsrs indirect addressing operations that target other fsrs or virtual registers represent special cases. for example, using an fsr to point to one of the virtual registers will not result in successful operations. as a specific case, assume that the fsr0h:fsr0l regis- ters contain fe7h, the address of indf1. attempts to read the value of the indf1, using indf0 as an operand, will return 00h. attempts to write to indf1, using indf0 as the operand, will result in a nop . on the other hand, using the virtual registers to write to an fsr pair may not occur as planned. in these cases, the value will be written to the fsr pair but without any incrementing or decrementing. thus, writing to indf2 or postdec2 will write the same value to the fsr2h:fsr2l. since the fsrs are physical registers mapped in the sfr space, they can be manipulated through all direct operations. users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. similarly, operations by indirect addressing are gener- ally permitted on all other sfrs. users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 6.5 program memory and the extended instruction set the operation of program memory is unaffected by the use of the extended instruction set. enabling the extended instruction set adds five additional two-word commands to the existing pic18 instruction set: addfsr , callw , movsf , movss and subfsr . these instructions are executed as described in section 6.2.4 two-word instructions . downloaded from: http:///
pic18f87j72 family ds39979a-page 74 preliminary ? 2010 microchip technology inc. 6.6 data memory and the extended instruction set enabling the pic18 extended instruction set (xinst configuration bit = 1 ) significantly changes certain aspects of data memory and its addressing. specifically, the use of the access bank for many of the core pic18 instructions is different. this is due to the introduction of a new addressing mode for the data memory space. this mode also alters the behavior of indirect addressing using fsr2 and its associated operands. what does not change is just as important. the size of the data memory space is unchanged, as well as its linear addressing. the sfr map remains the same. core pic18 instructions can still operate in both direct and indirect addressing mode; inherent and literal instructions do not change at all. indirect addressing with fsr0 and fsr1 also remains unchanged. 6.6.1 indexed addressing with literal offset enabling the pic18 extended instruction set changes the behavior of indirect addressing using the fsr2 register pair and its associated file operands. under the proper conditions, instructions that use the access bank C that is, most bit-oriented and byte-oriented instructions C can invoke a form of indexed addressing using an offset specified in the instruction. this special addressing mode is known as indexed addressing with literal offset, or indexed literal offset mode. when using the extended instruction set, this addressing mode requires the following: the use of the access bank is forced (a = 0 ); and the file address argument is less than or equal to 5fh. under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the bsr in direct addressing) or as an 8-bit address in the access bank. instead, the value is interpreted as an offset value to an address pointer specified by fsr2. the offset and the contents of fsr2 are added to obtain the target address of the operation. 6.6.2 instructions affected by indexed literal offset mode any of the core pic18 instructions that can use direct addressing are potentially affected by the indexed literal offset addressing mode. this includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard pic18 instruction set. instruc- tions that only use inherent or literal addressing modes are unaffected. additionally, byte-oriented and bit-oriented instructions are not affected if they use the access bank (access ram bit is 1 ) or include a file address of 60h or above. instructions meeting these criteria will continue to execute as before. a comparison of the different possible addressing modes when the extended instruction set is enabled is shown in figure 6-9. those who desire to use byte-oriented or bit-oriented instructions in the indexed literal offset mode should note the changes to assembler syntax for this mode. this is described in more detail in section 27.2.1 extended instruction syntax . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 75 pic18f87j72 family figure 6-9: comparing addressing options for bit-oriented and byte-oriented instructions (extended instruction set enabled) example instruction: addwf, f, d, a (opcode: 0010 01da ffff ffff ) when a = 0 and f ? 60h: the instruction executes in direct forced mode. f is interpreted as a location in the access ram between 060h and fffh. this is the same as locations, f60h to fffh (bank 15), of data memory. locations below 060h are not available in this addressing mode. when a = 0 and f ??? 5fh: the instruction executes in indexed literal offset mode. f is interpreted as an offset to the address value in fsr2. the two are added together to obtain the address of the target register for the instruction. the address can be anywhere in the data memory space. note that in this mode, the correct syntax is now: addwf [k], d where k is the same as f. when a = 1 (all values of f): the instruction executes in direct mode (also known as direct long mode). f is interpreted as a location in one of the 16 banks of the data memory space. the bank is designated by the bank select register (bsr). the address can be in any implemented bank in the data memory space. 000h 060h 100h f00h f40h fffh valid range 00h 60h ffh data memory access ram bank 0 bank 1 through bank 14 bank 15 sfrs 000h 060h 100h f00h f40h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs fsr2h fsr2l ffffffff 001001da ffffffff 001001da 000h 060h 100h f00h f40h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs for f bsr 00000000 downloaded from: http:///
pic18f87j72 family ds39979a-page 76 preliminary ? 2010 microchip technology inc. 6.6.3 mapping the access bank in indexed literal offset mode the use of indexed literal offset addressing mode effectively changes how the lower part of access ram (00h to 5fh) is mapped. rather than containing just the contents of the bottom part of bank 0, this mode maps the contents from bank 0 and a user-defined window that can be located anywhere in the data memory space. the value of fsr2 establishes the lower bound- ary of the addresses mapped into the window, while the upper boundary is defined by fsr2 plus 95 (5fh). addresses in the access ram above 5fh are mapped as previously described (see section 6.3.2 access bank ). an example of access bank remapping in this addressing mode is shown in figure 6-10. remapping of the access bank applies only to opera- tions using the indexed literal offset mode. operations that use the bsr (access ram bit is 1 ) will continue to use direct addressing as before. any indirect or indexed addressing operation that explicitly uses any of the indirect file operands (including fsr2) will con- tinue to operate as standard indirect addressing. any instruction that uses the access bank, but includes a register address of greater than 05fh, will use direct addressing and the normal access bank map. 6.6.4 bsr in indexed literal offset mode although the access bank is remapped when the extended instruction set is enabled, the operation of the bsr remains unchanged. direct addressing, using the bsr to select the data memory bank, operates in the same manner as previously described. figure 6-10: remapping the access bank with indexed literal offset addressing data memory 000h100h 200h f60h f00h fffh bank 1 bank 15 bank 2 through bank 14 sfrs 05fh addwf f, d, a fsr2h:fsr2l = 120h locations in the region from the fsr2 pointer (120h) to the pointer plus 05fh (17fh) are mapped to the bottom of the access ram (000h-05fh). special function registers at f60h through fffh are mapped to 60h through ffh, as usual. bank 0 addresses below 5fh are not available in this mode. they can still be addressed by using the bsr. access bank 00hffh bank 0 sfrs bank 1 window not accessible window example situation: 120h 17fh 5fh 60h downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 77 pic18f87j72 family 7.0 flash program memory the flash program memory is readable, writable and erasable during normal operation over the entire v dd range. a read from program memory is executed on one byte at a time. a write to program memory is executed on blocks of 64 bytes at a time or two bytes at a time. pro- gram memory is erased in blocks of 1,024 bytes at a time. a bulk erase operation may not be issued from user code. writing or erasing program memory will cease instruction fetches until the operation is complete. the program memory cannot be accessed during the write or erase, therefore, code cannot execute. an internal programming timer terminates program memory writes and erases. a value written to program memory does not need to be a valid instruction. executing a program memory location that forms an invalid instruction results in a nop . 7.1 table reads and table writes in order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data ram: table read ( tblrd ) table write ( tblwt ) the program memory space is 16 bits wide, while the data ram space is 8 bits wide. table reads and table writes move data between these two memory spaces through an 8-bit register (tablat). table read operations retrieve data from program memory and place it into the data ram space. figure 7-1 shows the operation of a table read with program memory and data ram. table write operations store data from the data memory space into holding registers in program memory. the procedure to write the contents of the holding registers into program memory is detailed in section 7.5 writing to flash program memory . figure 7-2 shows the operation of a table write with program memory and data ram. table operations work with byte entities. a table block containing data, rather than program instructions, is not required to be word-aligned. therefore, a table block can start and end at any byte address. if a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. figure 7-1: table read operation table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer register points to a byte in program memory. program memory (tblptr) downloaded from: http:///
pic18f87j72 family ds39979a-page 78 preliminary ? 2010 microchip technology inc. figure 7-2: table write operation 7.2 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include the: eecon1 register eecon2 register tablat register tblptr registers 7.2.1 eecon1 and eecon2 registers the eecon1 register (register 7-1) is the control register for memory accesses. the eecon2 register is not a physical register; it is used exclusively in the memory write and erase sequences. reading eecon2 will read all 0 s. the wprog bit, when set, allows the user to program a single word (two bytes) upon the execution of the wr command. if this bit is cleared, the wr command programs a block of 64 bytes. the free bit, when set, will allow a program memory erase operation. when free is set, the erase operation is initiated on the next wr command. when free is clear, only writes are enabled. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set in hardware when the wr bit is set and cleared when the internal programming timer expires and the write operation is complete. the wr control bit initiates write operations. the bit cannot be cleared, only set, in software. it is cleared in hardware at the completion of the write operation. table pointer (1) table latch (8-bit) tblptrh tblptrl tablat program memory (tblptr) tblptru instruction: tblwt * note 1: table pointer actually points to one of 64 holding r egisters, the address of which is determined by tblptrl<5:0>. the process for physically writing dat a to the program memory array is discussed in section 7.5 writing to flash program memory . holding registers program memory note: during normal operation, the wrerr is read as 1 . this can indicate that a write operation was prematurely terminated by a reset, or a write operation was attempted improperly. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 79 pic18f87j72 family register 7-1: eecon1: eepr om control register 1 u-0 u-0 r/w-0 r/w-0 r/w-x r/w-0 r/s-0 u-0 wprog free wrerr (1) wren wr bit 7 bit 0 legend: s = settable bit (cannot be cleared in software) r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5 wprog: one word-wide program bit 1 = program 2 bytes on the next wr command 0 = program 64 bytes on the next wr command bit 4 free: flash erase enable bit 1 = performs an erase operation on the next wr command (cleared by completion of erase operation) 0 = perform write only bit 3 wrerr: flash program error flag bit (1) 1 = a write operation is prematurely terminated (any reset during self-timed programming in normal operation or an improper write attempt) 0 = the write operation completed bit 2 wren: flash program write enable bit 1 = allows write cycles to flash program memory 0 = inhibits write cycles to flash program memory bit 1 wr: write control bit 1 = initiates a program memory erase cycle or write cycle (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle is complete bit 0 unimplemented: read as 0 note 1: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. downloaded from: http:///
pic18f87j72 family ds39979a-page 80 preliminary ? 2010 microchip technology inc. 7.2.2 table latch register (tablat) the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch register is used to hold 8-bit data during data transfers between program memory and data ram. 7.2.3 table pointer register (tblptr) the table pointer (tblptr) register addresses a byte within the program memory. the tblptr is comprised of three sfr registers: table pointer upper byte, table pointer high byte and table pointer low byte (tblptru:tblptrh:tblptrl). these three regis- ters join to form a 22-bit wide pointer. the low-order 21 bits allow the device to address up to 2 mbytes of program memory space. the 22nd bit allows access to the device id, the user id and the configuration bits. the table pointer register, tblptr, is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways based on the table operation. these operations are shown in table 7-1. these operations on the tblptr only affect the low-order 21 bits. 7.2.4 table pointer boundaries tblptr is used in reads, writes and erases of the flash program memory. when a tblrd is executed, all 22 bits of the tblptr determine which byte is read from program memory into tablat. when a tblwt is executed, the seven lsbs of the table pointer register (tblptr<6:0>) determine which of the 64 program memory holding registers is written to. when the timed write to program memory begins (via the wr bit), the 12 msbs of the tblptr (tblptr<21:10>) determine which program memory block of 1,024 bytes is written to. for more detail, see section 7.5 writing to flash program memory . when an erase of program memory is executed, the 12 msbs of the table pointer register point to the 1,024-byte block that will be erased. the least significant bits are ignored. figure 7-3 describes the relevant boundaries of tblptr based on flash program memory operations. table 7-1: table pointer operations with tblrd and tblwt instructions figure 7-3: table pointer boundaries based on operation example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write 21 16 15 87 0 erase: tblptr<20:10> table write: tblptr<20:6> table read: tblptr<21:0> tblptrl tblptrh tblptru downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 81 pic18f87j72 family 7.3 reading the flash program memory the tblrd instruction is used to retrieve data from program memory and places it into data ram. table reads from program memory are performed one byte at a time. tblptr points to a byte address in program space. executing tblrd places the byte pointed to into tablat. in addition, tblptr can be modified automatically for the next table read operation. the internal program memory is typically organized by words. the least significant bit of the address selects between the high and low bytes of the word. figure 7-4 shows the interface between the internal program memory and the tablat. figure 7-4: reads from flash program memory example 7-1: reading a flash program memory word (even byte address) program memory (odd byte address) tblrd tablat tblptr = xxxxx1 fetch instruction register (ir) read register tblptr = xxxxx0 movlwcode_addr_upper ; load tblptr with the base movwftblptru ; address of the word movlwcode_addr_high movwftblptrh movlwcode_addr_low movwftblptrl read_word tblrd*+ ; read into tablat and increment movf tablat, w ; get data movwfword_even tblrd*+ ; read into tablat and increment movf tablat, w ; get data movwfword_odd downloaded from: http:///
pic18f87j72 family ds39979a-page 82 preliminary ? 2010 microchip technology inc. 7.4 erasing flash program memory the minimum erase block is 512 words or 1,024 bytes. only through the use of an external programmer, or through icsp control, can larger blocks of program memory be bulk erased. word erase in the flash array is not supported. when initiating an erase sequence from the micro- controller itself, a block of 1,024 bytes of program memory is erased. the most significant 12 bits of the tblptr<21:10> point to the block being erased. tblptr<9:0> are ignored. the eecon1 register commands the erase operation. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. for protection, the write initiate sequence for eecon2 must be used. a long write is necessary for erasing the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. 7.4.1 flash program memory erase sequence the sequence of events for erasing a block of internal program memory location is: 1. load table pointer register with the address being erased. 2. set the wren and free bits (eecon1<2,4>) to enable the erase operation. 3. disable interrupts. 4. write 55h to eecon2. 5. write 0aah to eecon2. 6. set the wr bit. this will begin the erase cycle. 7. the cpu will stall for duration of the erase for t ie (see parameter d133b). 8. re-enable interrupts. example 7-2: erasing flash program memory movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase bsf eecon1, wren bsf eecon1, free ; enable erase operation bcf intcon, gie ; disable interrupts required movlw 55h sequence movwf eecon2 ; write 55h movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 83 pic18f87j72 family 7.5 writing to flash program memory the programming block is 32 words or 64 bytes. programming one word or two bytes at a time is also supported. table writes are used internally to load the holding registers needed to program the flash memory. there are 64 holding registers used by the table writes for programming. since the table latch (tablat) is only a single byte, the tblwt instruction may need to be executed 64 times for each programming operation (if wprog = 0 ). all of the table write operations will essentially be short writes because only the holding registers are written. at the end of updating the 64 holding registers, the eecon1 register must be written to in order to start the programming operation with a long write. the long write is necessary for programming the inter- nal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. the on-chip timer controls the write time. the write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. figure 7-5: table writes to flash program memory 7.5.1 flash program memory write sequence the sequence of events for programming an internal program memory location should be: 1. read 1,024 bytes into ram. 2. update data values in ram as necessary. 3. load table pointer register with the address being erased. 4. execute the erase procedure. 5. load table pointer register with the address of the first byte being written, minus 1. 6. write the 64 bytes into the holding registers with auto-increment. 7. set the wren bit (eecon1<2>) to enable byte writes. 8. disable interrupts. 9. write 55h to eecon2. 10. write 0aah to eecon2. 11. set the wr bit. this will begin the write cycle. 12. the cpu will stall for the duration of the write for t iw (parameter d133a). 13. re-enable interrupts. 14. repeat steps 6 through 13 until all 1,024 bytes are written to program memory. 15. verify the memory (table read). an example of the required code is shown in example 7-3 on the following page. note 1: unlike previous pic18 flash devices, members of the pic18f87j72 family do not reset the holding registers after a write occurs. the holding registers must be cleared or overwritten before a programming sequence. 2: to maintain the endurance of the program memory cells, each flash byte should not be programmed more than one time between erase operations. before attempting to modify the contents of the target cell a second time, an erase of the target, or a bulk erase of the entire memory, must be performed. tblptr = xxxx3f tblptr = xxxxx1 tblptr = xxxxx0 tblptr = xxxxx2 program memory holding register holding register holding register holding register 8 8 8 8 tablat write register note: before setting the wr bit, the table pointer address needs to be within the intended address range of the 64 bytes in the holding register. downloaded from: http:///
pic18f87j72 family ds39979a-page 84 preliminary ? 2010 microchip technology inc. example 7-3: writing to flash program memory movlw code_addr_upper ; load tblptr with the base address movwf tblptru ; of the memory block, minus 1 movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase_block bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable erase operation bcf intcon, gie ; disable interrupts movlw 55h movwf eecon2 ; write 55h movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts movlw d'16' movwf write_counter ; need to write 16 blocks of 64 to write ; one erase block of 1024 restart_buffer movlw d'64' movwf counter movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l fill_buffer ... ; read the new data from i2c, spi, ; psp, usart, etc. write_buffer movlw d64 ; number of bytes in holding register movwf counter write_byte_to_hregs movff postinc0, wreg ; get low byte of buffer data movwf tablat ; present data to table latch tblwt+* ; write data, perform a short write ; to internal tblwt holding register. decfsz counter ; loop until buffers are full bra write_byte_to_hregs program_memory bsf eecon1, wren ; enable write to memory bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start program (cpu stall) bsf intcon, gie ; re-enable interrupts bcf eecon1, wren ; disable write to memory decfsz write_counter ; done with one write cycle bra restart_buffer ; if not done replacing the erase block downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 85 pic18f87j72 family 7.5.2 flash program memory write sequence (word programming). the pic18f87j72 family of devices has a feature that allows programming a single word (two bytes). this feature is enabled when the wprog bit is set. if the memory location is already erased, the following sequence is required to enable this feature: 1. load the table pointer register with the address of the data to be written 2. write the 2 bytes into the holding registers and perform a table write 3. set wprog to enable single-word write. 4. set wren to enable write to memory. 5. disable interrupts. 6. write 55h to eecon2. 7. write 0aah to eecon2. 8. set the wr bit. this will begin the write cycle. 9. the cpu will stall for duration of the write for t iw (see parameter d133a). 10. re-enable interrupts. example 7-4: single-word write to flash program memory movlw code_addr_upper ; load tblptr with the base address movwf tblptru movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl movlw data0 movwf tablat tblwt*+ movlw data1 movwf tablat tblwt* program_memory bsf eecon1, wprog ; enable single word write bsf eecon1, wren ; enable write to memory bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start program (cpu stall) bsf intcon, gie ; re-enable interrupts bcf eecon1, wprog ; disable single word write bcf eecon1, wren ; disable write to memory downloaded from: http:///
pic18f87j72 family ds39979a-page 86 preliminary ? 2010 microchip technology inc. 7.5.3 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 7.5.4 unexpected termination of write operation if a write is terminated by an unplanned event, such as loss of power or an unexpected reset, the memory location just programmed should be verified and repro- grammed if needed. if the write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation, the user can check the wrerr bit and rewrite the location(s) as needed. 7.6 flash program operation during code protection see section 26.6 program verification and code protection for details on code protection of flash program memory. table 7-2: registers associated with program flash memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page: tblptru bit 21 program memory table pointer upper byte (tblptr<20:16>) 49 tbpltrh program memory table pointer high byte (tblptr<15:8>) 49 tblptrl program memory table pointer low byte (tblptr<7:0>) 49 tablat program memory table latch 49 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 eecon2 eeprom control register 2 (not a physical register) 51 eecon1 wprog free wrerr wren wr 5 1 legend: = unimplemented, read as 0 . shaded cells are not used during flash program memory access. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 87 pic18f87j72 family 8.0 8 x 8 hardware multiplier 8.1 introduction all pic18 devices include an 8 x 8 hardware multiplier as part of the alu. the multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, prodh:prodl. the multipliers operation does not affect any flags in the status register. making multiplication a hardware operation allows it to be completed in a single instruction cycle. this has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the pic18 devices to be used in many applica- tions previously reserved for digital signal processors. a comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in table 8-1. 8.2 operation example 8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. only one instruction is required when one of the arguments is already loaded in the wreg register. example 8-2 shows the sequence to do an 8 x 8 signed multiplication. to account for the sign bits of the argu- ments, each arguments most significant bit (msb) is tested and the appropriate subtractions are done. example 8-1: 8 x 8 unsigned multiply routine example 8-2: 8 x 8 signed multiply routine table 8-1: performance comparison for v arious multiply operations movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movf arg2, w btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 routine multiply method program memory (words) cycles (max) time @ 48 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 5.7 ? s2 7 . 6 ? s6 9 ? s hardware multiply 1 1 83.3 ns 400 ns 1 ? s 8 x 8 signed without hardware multiply 33 91 7.5 ? s3 6 . 4 ? s9 1 ? s hardware multiply 6 6 500 ns 2.4 ? s6 ? s 16 x 16 unsigned without hardware multiply 21 242 20.1 ? s9 6 . 8 ? s2 4 2 ? s hardware multiply 28 28 2.3 ? s 11.2 ? s2 8 ? s 16 x 16 signed without hardware multiply 52 254 21.6 ? s 102.6 ? s2 5 4 ? s hardware multiply 35 40 3.3 ? s1 6 . 0 ? s4 0 ? s downloaded from: http:///
pic18f87j72 family ds39979a-page 88 preliminary ? 2010 microchip technology inc. example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. equation 8-1 shows the algorithm that is used. the 32-bit result is stored in four registers (res3:res0). equation 8-1: 16 x 16 unsigned multiplication algorithm example 8-3: 16 x 16 unsigned multiply routine example 8-4 shows the sequence to do a 16 x 16 signed multiply. equation 8-2 shows the algorithm used. the 32-bit result is stored in four registers (res3:res0). to account for the sign bits of the arguments, the msb for each argument pair is tested and the appropriate subtractions are done. equation 8-2: 16 x 16 signed multiplication algorithm example 8-4: 16 x 16 signed multiply routine res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) movf arg1l, w mulwf arg2l ; arg1l * arg2l-> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h-> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; res3:res0= arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 ) + (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) movf arg1l, w mulwfarg2l ; arg1l * arg2l -> ; prodh:prodl movffprodh, res1 ; movffprodl, res0 ; ; movf arg1h, w mulwfarg2h ; arg1h * arg2h -> ; prodh:prodl movffprodh, res3 ; movffprodl, res2 ; ; movf arg1l, w mulwfarg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwfres1, f ; add cross movf prodh, w ; products addwfcres2, f ; clrf wreg ; addwfcres3, f ; ; movf arg1h, w ; mulwfarg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwfres1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfcres3, f ; ; btfssarg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwfres2 ; movf arg1h, w ; subwfbres3 ; sign_arg1 btfssarg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwfres2 ; movf arg2h, w ; subwfbres3 ; cont_code : downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 89 pic18f87j72 family 9.0 interrupts members of the pic18f87j72 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. the high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. high-priority interrupt events will interrupt any low-priority interrupts that may be in progress. there are thirteen registers which are used to control interrupt operation. these registers are: rcon intcon intcon2 intcon3 pir1, pir2, pir3 pie1, pie2, pie3 ipr1, ipr2, ipr3 it is recommended that the microchip header files supplied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. in general, interrupt sources have three bits to control their operation. they are: flag bit to indicate that an interrupt event occurred enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon<7>). when interrupt priority is enabled, there are two bits which enable interrupts globally. setting the gieh bit (intcon<7>) enables all interrupts that have the priority bit set (high priority). setting the giel bit (intcon<6>) enables all interrupts that have the priority bit cleared (low priority). when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. individual interrupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with pic ? mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. intcon<6> is the peie bit which enables/disables all peripheral interrupt sources. intcon<7> is the gie bit which enables/disables all interrupt sources. all interrupts branch to address 0008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh or giel bit. high-priority interrupt sources can interrupt a low-priority interrupt. low-priority interrupts are not processed while high-priority interrupts are in progress. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (0008h or 0018h). once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the return from interrupt instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used) which re-enables interrupts. for external interrupt events, such as the intx pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two-cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the gie bit. note: do not use the movff instruction to modify any of the interrupt control registers while any interrupt is enabled. doing so may cause erratic microcontroller behavior. downloaded from: http:///
pic18f87j72 family ds39979a-page 90 preliminary ? 2010 microchip technology inc. figure 9-1: pic18f87j72 family interrupt logic tmr0ie gie/gieh peie/giel wake-up if in interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip rbif rbie rbip ipen tmr0if tmr0ip int1if int1ie int1ip int2if int2ie int2ip rbif rbie rbip int0if int0ie peie/giel interrupt to cpu vector to location ipen ipen 0018h pir1<6:3,1:0> pie1<6:3,1:0> ipr1<6:3,1:0> high-priority interrupt generation low-priority interrupt generation idle or sleep modes gie/gieh int3if int3ie int3ip int3if int3ie int3ip pir2<7:6,3:1> pie2<7:6 3:1> ipr2<7:6,3:1> pir3<6:0> pie3<6:0> ipr3<6:0> pir1<6:3,1:0> pie1<6:3,1:0> ipr1<6:3,1:0> pir2<7:6,3:1> pie2<7:6,3:1> ipr2<7:6, 3 : 1 > pir3<6:0> pie3<6:0> ipr3<6:0> ipen downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 91 pic18f87j72 family 9.1 intcon registers the intcon registers are readable and writable registers which contain various enable, priority and flag bits. note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. register 9-1: intcon: interrupt control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 gie/gieh: global interrupt enable bit when ipen = 0 : 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen = 1 : 1 = enables all high-priority interrupts 0 = disables all interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen = 0 : 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1 : 1 = enables all low-priority peripheral interrupts 0 = disables all low-priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit (1) 1 = at least one of the rb<7:4> pins changed state (must be cleared in software) 0 = none of the rb<7:4> pins have changed state note 1: a mismatch condition will continue to set this bit. reading portb, then waiting one instruction cycle, wi ll end the mismatch condition and allow the bit to be cleared. downloaded from: http:///
pic18f87j72 family ds39979a-page 92 preliminary ? 2010 microchip technology inc. register 9-2: intcon2: in terrupt control register 2 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0: external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1: external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2: external interrupt 2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 intedg3: external interrupt 3 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 2 tmr0ip: tmr0 overflow interrupt priority bit 1 =high priority 0 = low priority bit 1 int3ip: int3 external interrupt priority bit 1 =high priority 0 = low priority bit 0 rbip: rb port change interrupt priority bit 1 =high priority 0 = low priority note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bit s are clear prior to enabling an interrupt. this feature allows for software polling. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 93 pic18f87j72 family register 9-3: intcon3: in terrupt control register 3 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 int2ip: int2 external interrupt priority bit 1 =high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 =high priority 0 = low priority bit 5 int3ie: int3 external interrupt enable bit 1 = enables the int3 external interrupt 0 = disables the int3 external interrupt bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 int3if: int3 external interrupt flag bit 1 = the int3 external interrupt occurred (must be cleared in software) 0 = the int3 external interrupt did not occur bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. downloaded from: http:///
pic18f87j72 family ds39979a-page 94 preliminary ? 2010 microchip technology inc. 9.2 pir registers the pir registers contain the individual flag bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt request (flag) registers (pir1, pir2, pir3). note 1: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie (intcon<7>). 2: user software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. register 9-4: pir1: peripheral interrupt request (flag) register 1 u-0 r/w-0 r-0 r-0 r/w-0 u-0 r/w-0 r/w-0 adif rc1if tx1if sspif t m r 2 i ft m r 1 i f bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6 adif: a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rc1if: eusart receive interrupt flag bit 1 = the eusart receive buffer, rcreg1, is full (cleared when rcreg1 is read) 0 = the eusart receive buffer is empty bit 4 tx1if: eusart transmit interrupt flag bit 1 = the eusart transmit buffer, txreg1, is empty (cleared when txreg1 is written) 0 = the eusart transmit buffer is full bit 3 sspif: master synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 unimplemented: read as 0 bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 95 pic18f87j72 family register 9-5: pir2: peripheral interrupt request (flag) register 2 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 oscfif cmif b c l i fl v d i ft m r 3 i f bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 oscfif: oscillator fail interrupt flag bit 1 = device oscillator failed, clock input has changed to intosc (must be cleared in software) 0 = device clock operating bit 6 cmif: comparator interrupt flag bit 1 = comparator input has changed (must be cleared in software) 0 = comparator input has not changed bit 5-4 unimplemented: read as 0 bit 3 bclif: bus collision interrupt flag bit 1 = a bus collision occurred (must be cleared in software) 0 = no bus collision occurred bit 2 lvdif: low-voltage detect interrupt flag bit 1 = a low-voltage condition occurred (must be cleared in software) 0 = the device voltage is above the regulators low-voltage trip point bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 unimplemented: read as 0 downloaded from: http:///
pic18f87j72 family ds39979a-page 96 preliminary ? 2010 microchip technology inc. register 9-6: pir3: peripheral interrupt request (flag) register 3 u-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6 lcdif: lcd interrupt flag bit (valid when type-b waveform with non-static mode is selected) 1 = lcd data of all coms is output (must be cleared in software) 0 = lcd data of all coms is not yet output bit 5 rc2if: ausart receive interrupt flag bit 1 = the ausart receive buffer, rcreg2, is full (cleared when rcreg2 is read) 0 = the ausart receive buffer is empty bit 4 tx2if: ausart transmit interrupt flag bit 1 = the ausart transmit buffer, txreg2, is empty (cleared when txreg2 is written) 0 = the ausart transmit buffer is full bit 3 ctmuif: ctmu interrupt flag bit 1 = ctmu interrupt occured (must be cleared in software) 0 = no ctmu interrupt occured bit 2 ccp2if: ccp2 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. bit 1 ccp1if: ccp1 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. bit 0 rtccif: rtcc interrupt flag bit 1 = rtcc interrupt occured (must be cleared in software) 0 = no rtcc interrupt occured downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 97 pic18f87j72 family 9.3 pie registers the pie registers contain the individual enable bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt enable registers (pie1, pie2, pie3). when ipen = 0 , the peie bit must be set to enable any of these peripheral interrupts. register 9-7: pie1: peripheral interrupt enable register 1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 adie rc1ie tx1ie sspie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6 adie: a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rc1ie: eusart receive interrupt enable bit 1 = enables the eusart receive interrupt 0 = disables the eusart receive interrupt bit 4 tx1ie: eusart transmit interrupt enable bit 1 = enables the eusart transmit interrupt 0 = disables the eusart transmit interrupt bit 3 sspie: master synchronous serial port interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 unimplemented: read as 0 bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt downloaded from: http:///
pic18f87j72 family ds39979a-page 98 preliminary ? 2010 microchip technology inc. register 9-8: pie2: peripheral interrupt enable register 2 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 oscfie cmie bclie lvdie tmr3ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 oscfie: oscillator fail interrupt enable bit 1 = enabled 0 = disabled bit 6 cmie: comparator interrupt enable bit 1 = enabled 0 = disabled bit 5-4 unimplemented: read as 0 bit 3 bclie: bus collision interrupt enable bit 1 = enabled 0 = disabled bit 2 lvdie: low-voltage detect interrupt enable bit 1 = enabled 0 = disabled bit 1 tmr3ie: tmr3 overflow interrupt enable bit 1 = enabled 0 = disabled bit 0 unimplemented: read as 0 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 99 pic18f87j72 family register 9-9: pie3: peripheral interrupt enable register 3 u-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6 lcdie: lcd interrupt enable bit (valid when type-b waveform with non-static mode is selected) 1 = enabled 0 = disabled bit 5 rc2ie: ausart receive interrupt enable bit 1 = enabled 0 = disabled bit 4 tx2ie: ausart transmit interrupt enable bit 1 = enabled 0 = disabled bit 3 ctmuie: ctmu interrupt enable bit 1 = enabled 0 = disabled bit 2 ccp2ie: ccp2 interrupt enable bit 1 = enabled 0 = disabled bit 1 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 0 rtccie: rtcc interrupt enable bit 1 = enabled 0 = disabled downloaded from: http:///
pic18f87j72 family ds39979a-page 100 preliminary ? 2010 microchip technology inc. 9.4 ipr registers the ipr registers contain the individual priority bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (ipr1, ipr2, ipr3). using the priority bits requires that the interrupt priority enable (ipen) bit be set. register 9-10: ipr1: peripheral interrupt priority register 1 u-0 r/w-1 r/w-1 r/w-1 r/w-1 u-0 r/w-1 r/w-1 adip rc1ip tx1ip sspip tmr2ip tmr1ip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6 adip: a/d converter interrupt priority bit 1 =high priority 0 = low priority bit 5 rc1ip: eusart receive interrupt priority bit 1 =high priority 0 = low priority bit 4 tx1ip: eusart transmit interrupt priority bit 1 =high priority 0 = low priority bit 3 sspip: master synchronous serial port interrupt priority bit 1 =high priority 0 = low priority bit 2 unimplemented: read as 0 bit 1 tmr2ip: tmr2 to pr2 match interrupt priority bit 1 =high priority 0 = low priority bit 0 tmr1ip: tmr1 overflow interrupt priority bit 1 =high priority 0 = low priority downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 101 pic18f87j72 family register 9-11: ipr2: peripheral interrupt priority register 2 r/w-1 r/w-1 u-0 u-0 r/w-1 r/w-1 r/w-1 u-0 oscfip cmip bclip lvdip tmr3ip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 oscfip: oscillator fail interrupt priority bit 1 =high priority 0 = low priority bit 6 cmip: comparator interrupt priority bit 1 =high priority 0 = low priority bit 5-4 unimplemented: read as 0 bit 3 bclip: bus collision interrupt priority bit 1 =high priority 0 = low priority bit 2 lvdip: low-voltage detect interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr3ip: tmr3 overflow interrupt priority bit 1 =high priority 0 = low priority bit 0 unimplemented: read as 0 downloaded from: http:///
pic18f87j72 family ds39979a-page 102 preliminary ? 2010 microchip technology inc. register 9-12: ipr3: peripheral interrupt priority register 3 u-0 r/w-1 r-1 r-1 r/w-1 r/w-1 r/w-1 r/w-1 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6 lcdip: lcd interrupt priority bit (valid when type-b waveform with non-static mode is selected) 1 =high priority 0 = low priority bit 5 rc2ip: ausart receive priority flag bit 1 =high priority 0 = low priority bit 4 tx2ip: ausart transmit interrupt priority bit 1 =high priority 0 = low priority bit 3 ctmuip: ctmu interrupt priority bit 1 =high priority 0 = low priority bit ccp2ip: ccp2 interrupt priority bit 1 =high priority 0 = low priority bit ccp1ip: ccp1 interrupt priority bit 1 =high priority 0 = low priority bit 0 rtccip: rtcc interrupt priority bit 1 =high priority 0 = low priority downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 103 pic18f87j72 family 9.5 rcon register the rcon register contains bits used to determine the cause of the last reset or wake-up from idle or sleep modes. rcon also contains the bit that enables interrupt priorities (ipen). register 9-13: rcon: re set control register r/w-0 u-0 r/w-1 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen c m ri to pd por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6 unimplemented: read as 0 bit 5 cm : configuration mismatch flag bit 1 = a configuration mismatch reset has not occurred 0 = a configuration mismatch reset has occurred (must be subsequently set in software.) bit 4 ri : reset instruction flag bit for details of bit operation, see register 5-1. bit 3 to : watchdog timer time-out flag bit for details of bit operation, see register 5-1. bit 2 pd : power-down detection flag bit for details of bit operation, see register 5-1. bit 1 por : power-on reset status bit for details of bit operation, see register 5-1. bit 0 bor : brown-out reset status bit for details of bit operation, see register 5-1. downloaded from: http:///
pic18f87j72 family ds39979a-page 104 preliminary ? 2010 microchip technology inc. 9.6 intx pin interrupts external interrupts on the rb0/int0, rb1/int1, rb2/int2 and rb3/int3 pins are edge-triggered. if the corresponding intedgx bit in the intcon2 register is set (= 1 ), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. when a valid edge appears on the rbx/intx pin, the corresponding flag bit, intxif, is set. this interrupt can be disabled by clearing the corresponding enable bit, intxie. flag bit, intxif, must be cleared in software in the interrupt service routine (isr) before re-enabling the interrupt. all external interrupts (int0, int1, int2 and int3) can wake-up the processor from the power-managed modes if bit intxie was set prior to going into the power-managed modes. if the global interrupt enable bit, gie, is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1, int2 and int3 is determined by the value contained in the interrupt priority bits, int1ip (intcon3<6>), int2ip (intcon3<7>) and int3ip (intcon2<1>). there is no priority bit associated with int0. it is always a high-priority interrupt source. 9.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow in the tmr0 register (ffh ? 00h) will set flag bit, tmr0if. in 16-bit mode, an overflow in the tmr0h:tmr0l register pair (ffffh ? 0000h) will set tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit, tmr0ie (intcon<5>). interrupt priority for timer0 is determined by the value contained in the interrupt priority bit, tmr0ip (intcon2<2>). see section 11.0 timer0 module for further details on the timer0 module. 9.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit, rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<3>). interrupt priority for portb interrupt-on-change is determined by the value contained in the interrupt priority bit, rbip (intcon2<0>). 9.9 context saving during interrupts during interrupts, the return pc address is saved on the stack. additionally, the wreg, status and bsr registers are saved on the fast return stack. if a fast return from interrupt is not used (see section 6.3 data memory organization ), the user may need to save the wreg, status and bsr registers on entry to the interrupt service routine. depending on the users application, other registers may also need to be saved. example 9-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 9-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr_tmep located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 105 pic18f87j72 family 10.0 i/o ports depending on the features enabled, there are up to seven ports available. some pins of the i/o ports are multiplexed with an alternate function from the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three memory mapped registers for its operation: tris register (data direction register) port register (reads the levels on the pins of the device) lat register (output latch register) reading the port register reads the current status of the pins, whereas writing to the port register, writes to the output latch (lat) register. setting a tris bit (= 1 ) makes the corresponding port pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a tris bit (= 0 ) makes the corresponding port pin an output (i.e., put the contents of the corresponding lat bit on the selected pin). the output latch (lat register) is useful for read-modify-write operations on the value that the i/o pins are driving. read-modify-write operations on the lat register read and write the latched output value for the port register. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 10-1. figure 10-1: generic i/o port operation 10.1 i/o port pin capabilities when developing an application, the capabilities of the port pins must be considered. outputs on some pins have higher output drive strength than others. similarly, some pins can tolerate higher than v dd input levels. 10.1.1 input pins and voltage considerations the voltage tolerance of pins used as device inputs is dependent on the pins input function. most of the pins that are used as digital only inputs are able to handle dc voltages up to 5.5v, a level typical for digital logic circuits. in contrast, pins that also have analog input functions of any kind can only tolerate voltages up to v dd . table 10-1 summarizes the input voltage capabilities of the i/o pins. refer to section 29.0 electrical characteristics for more details. voltage excursions beyond v dd on these pins should be avoided. table 10-1: input voltage tolerance 10.1.2 pin output drive when used as digital i/o, the output pin drive strengths vary for groups of pins intended to meet the needs for a variety of applications. in general, there are three classes of output pins in terms of drive capability. portb and portc, as well as porta<7:6>, are designed to drive higher current loads, such as leds. portd, porte and portj can also drive leds but only those with smaller current requirements. portf, portg and porth, along with porta<5:0>, have the lowest drive level but are capable of driving normal digital circuit loads with a high input impedance. regardless of which port it is located on, all output pins in lcd segment or common-mode have sufficient output to directly drive a display. table 10-2 summarizes the output capabilities of the ports. refer to the absolute maximum ratings in section 29.0 electrical characteristics for more details. data bus wr lat wr tris rd port data latch tris latch rd tris input buffer i/o pin q d ckx q d ckx en qd en rd lat or port port or pin tolerated input description porta<7:0> v dd only v dd input levels tolerated. portc<1:0> portf<1,0> portf<7:1> portg<3:2, 0> portb<7:0> 5.5v tolerates input levels above v dd , useful for most standard logic. portc<7:2> portd<7:0> porte<7:2> portg<4,1> downloaded from: http:///
pic18f87j72 family ds39979a-page 106 preliminary ? 2010 microchip technology inc. table 10-2: output drive levels for various ports 10.1.3 pull-up configuration four of the i/o ports (portb, portd, porte and portj) implement configurable weak pull-ups on all pins. these are internal pull-ups that allow floating digital input signals to be pulled to a consistent level without the use of external resistors. the pull-ups are enabled with a single bit for each of the ports: rbpu (intcon2<7>) for portb, and rdpu, repu and pjpu (portg<7:5>) for the other ports. 10.1.4 open-drain outputs the output pins for several peripherals are also equipped with a configurable, open-drain output option. this allows the peripherals to communicate with external digital logic, operating at a higher voltage level, without the use of level translators. the open-drain option is implemented on port pins specifically associated with the data and clock outputs of the usarts, the mssp module (in spi mode) and the ccp modules. this option is selectively enabled by setting the open-drain control bit for the corresponding module in trisg and latg. their configuration is dis- cussed in more detail in section 10.4 portc, trisc and latc registers , section 10.6 porte, trise and late registers and section 10.8 portg, trisg and latg registers . when the open-drain option is required, the output pin must also be tied through an external pull-up resistor provided by the user to a higher voltage level, up to 5v (figure 10-2). when a digital logic high signal is output, it is pulled up to the higher voltage level. figure 10-2: using the open-drain output (usart shown as example) 10.2 porta, trisa and lata registers porta is an 8-bit wide, bidirectional port. the corre- sponding data direction and output latch registers are trisa and lata. ra4/t0cki is a schmitt trigger input. all other porta pins have ttl input levels and full cmos output drivers. the ra4 pin is multiplexed with the timer0 clock input and one of the lcd segment drives. ra5 and ra<3:0> are multiplexed with analog inputs for the a/d converter. the operation of the analog inputs as a/d converter inputs is selected by clearing or setting the pcfg<3:0> control bits in the adcon1 register. the corresponding trisa bits control the direction of these pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. osc2/clko/ra6 and osc1/clki/ra7 normally serve as the external circuit connections for the exter- nal (primary) oscillator circuit (hs oscillator modes) or the external clock input and output (ec oscillator modes). in these cases, ra6 and ra7 are not available as digital i/o and their corresponding tris and lat bits are read as 0 . when the device is configured to use intosc or intrc as the default oscillator mode (fosc2 configuration bit is 0 ), ra6 and ra7 are automatically configured as digital i/o. the oscillator and clock in/clock out functions are disabled. ra1, ra4 and ra5 are multiplexed with lcd segment drives, controlled by bits in the lcdse1 and lcdse2 registers. i/o port functionality is only available when the lcd segments are disabled. example 10-1: initializing porta low medium high porta<5:0> portd porta<7:6> portf porte portb portg portc tx x +5v 3.3v (at logic 1 ) 3.3v v dd 5v pic18f87j72 note: ra5 and ra<3:0> are configured as analog inputs on any reset and are read as 0 . ra4 is configured as a digital input. clrf porta ; initialize porta by ; clearing output latches clrf lata ; alternate method to ; clear output data latches movlw 07h ; configure a/d movwf adcon1 ; for digital inputs movlw 0bfh ; value used to initialize ; data direction movwf trisa ; set ra<7, 5:0> as inputs, ; ra<6> as output downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 107 pic18f87j72 family table 10-3: porta functions table 10-4: summary of regist ers associated with porta pin name function tris setting i/o i/o type description ra0/an0 ra0 0 o dig lata<0> data output; not affected by analog input. 1 i ttl porta<0> data input; disabled when analog input is enabled. an0 1 i ana a/d input channel 0. default input configuration on por; does not affect digital output. ra1/an1/seg18 ra1 0 o dig lata<1> data output; not affected by analog input. 1 i ttl porta<1> data input; disabled when analog input is enabled. an1 1 i ana a/d input channel 1. default input configuration on por; does not affect digital output. seg18 x o ana lcd segment 18 output; disables all other pin functions. ra2/an2/v ref -r a 2 0 o dig lata<2> data output; not affected by analog input. 1 i ttl porta<2> data input; disabled when analog functions are enabled. an2 1 i ana a/d input channel 2. default input configuration on por. v ref - 1 i ana a/d and comparator low reference voltage input. ra3/an3/v ref +r a 3 0 o dig lata<3> data output; not affected by analog input. 1 i ttl porta<3> data input; disabled when analog input is enabled. an3 1 i ana a/d input channel 3. default input configuration on por. v ref + 1 i ana a/d and comparator high reference voltage input. ra4/t0cki/ seg14 ra4 0 o dig lata<4> data output. 1 i st porta<4> data input. default configuration on por. t0cki x i st timer0 clock input. seg14 x o ana lcd segment 14 output; disables all other pin functions. ra5/an4/seg15 ra5 0 o dig lata<5> data output; not affected by analog input. 1 i ttl porta<5> data input; disabled when analog input is enabled. an4 1 i ana a/d input channel 4. default configuration on por. seg15 x o ana lcd segment 15 output; disables all other pin functions. osc2/clko/ra6 osc2 x o ana main oscillator feedback output connection (hs and hspll modes). clko x o dig system cycle clock output (f osc /4) (ec and ecpll modes). ra6 0 o dig lata<6> data output; disabled when fosc2 configuration bit is set. 1 i ttl porta<6> data input; disabled when fosc2 configuration bit is set. osc1/clki/ra7 osc1 x i ana main oscillator input connection (hs and hspll modes). clki x i ana main external clock sour ce input (ec and ecpll modes). ra7 0 o dig lata<7> data output; disabled when fosc2 configuration bit is set. 1 i ttl porta<7> data input; disabled when fosc2 configuration bit is set. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt trigger buffer input, ttl = ttl buffer input, x = dont care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porta ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 52 lata lata7 (1) lata6 (1) lata5 lata4 lata3 lata2 lata1 lata0 52 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 52 adcon1 trigsel vcfg1 v c f g 0p c f g 3p c f g 2p c f g 1p c f g 0 5 1 lcdse1 se15 se14 se13 se12 se11 se10 se09 se08 51 lcdse2 se23 se22 se21 se20 se19 se18 se17 se16 51 legend: = unimplemented, read as 0 . shaded cells are not used by porta. note 1: these bits are enabled depending on the oscillator mode se lected. when not enabled as porta pins, they are disabled and read as x . downloaded from: http:///
pic18f87j72 family ds39979a-page 108 preliminary ? 2010 microchip technology inc. 10.3 portb, trisb and latb registers portb is an 8-bit wide, bidirectional port. the corresponding data direction and output latch registers are trisb and latb. all pins on portb are digital only and tolerate voltages up to 5.5v. example 10-2: initializing portb each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is performed by clearing bit, rbpu (intcon2<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of the portb pins (rb<7:4>) have an interrupt-on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb<7:4> pin configured as an output is excluded from the interrupt-on-change comparison). the input pins (of rb<7:4>) are compared with the old value latched on the last read of portb. the mismatch outputs of rb<7:4> are ored together to generate the rb port change interrupt with flag bit, rbif (intcon<0>). this interrupt can wake the device from power-managed modes. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff (any) , portb instruction). this will end the mismatch condition. b) wait one instruction cycle. c) clear flag bit, rbif. a mismatch condition will continue to set flag bit, rbif. reading portb will end the mismatch condition and allow flag bit, rbif, to be cleared after a delay of one t cy . the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. rb<3:2> are multiplexed as ctmu edge inputs. rb<5:0> are also multiplexed with lcd segment drives, controlled by bits in the lcdse1 and lcdse3 registers. i/o port functionality is only available when the lcd segments are disabled. clrf portb ; initialize portb by ; clearing output; data latches clrf latb ; alternate method ; to clear output; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 109 pic18f87j72 family table 10-5: portb functions pin name function tris setting i/o i/o type description rb0/int0/seg30 rb0 0 o dig latb<0> data output. 1 i ttl portb<0> data input; weak pull-up when rbpu bit is cleared. int0 1 i st external interrupt 0 input. seg30 x o ana lcd segment 30 output; disables all other pin functions. rb1/int1/seg8 rb1 0 o dig latb<1> data output. 1 i ttl portb<1> data input; weak pull-up when rbpu bit is cleared. int1 1 i st external interrupt 1 input. seg8 x o ana lcd segment 8 output; disables all other pin functions. rb2/int2/seg9/ cted1 rb2 0 o dig latb<2> data output. 1 i ttl portb<2> data input; weak pull-up when rbpu bit is cleared. int2 1 i st external interrupt 2 input. seg9 x o ana lcd segment 9 output; disables all other pin functions. cted1 x i st ctmu edge 1 input. rb3/int3/seg10/ cted2 rb3 0 o dig latb<3> data output. 1 i ttl portb<3> data input; weak pull-up when rbpu bit is cleared. int3 1 i st external interrupt 3 input. seg10 x o ana lcd segment 10 output; disables all other pin functions. cted2 x i st ctmu edge 2 input. rb4/kbi0/seg11 rb4 0 o dig latb<4> data output. 1 i ttl portb<4> data input; weak pull-up when rbpu bit is cleared. kbi0 1 i ttl interrupt-on-pin change. seg11 x o ana lcd segment 11 output; disables all other pin functions. rb5/kbi1/seg29 rb5 0 o dig latb<5> data output. 1 i ttl portb<5> data input; weak pull-up when rbpu bit is cleared. kbi1 1 i ttl interrupt-on-pin change. seg29 x o ana lcd segment 29 output; disables all other pin functions. rb6/kbi2/pgc rb6 0 o dig latb<6> data output. 1 i ttl portb<6> data input; weak pull-up when rbpu bit is cleared. kbi2 1 i ttl interrupt-on-pin change. pgc x i st serial execution (icsp?) clock input for icsp and icd operation. rb7/kbi3/pgd rb7 0 o dig latb<7> data output. 1 i ttl portb<7> data input; weak pull-up when rbpu bit is cleared. kbi3 1 i ttl interrupt-on-pin change. pgd x o dig serial execution data output for icsp? and icd operation. x i st serial execution data input for icsp and icd operation. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt trigger buffer input, ttl = ttl buffer input, x = dont care (tris bit does not affect port direction or is overridden for this option). downloaded from: http:///
pic18f87j72 family ds39979a-page 110 preliminary ? 2010 microchip technology inc. table 10-6: summary of regist ers associated with portb n a m eb i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 reset values on page portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 52 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 52 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 52 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 49 intcon3 int2ip int1ip int3ie int2i e int1ie int3if int2if int1if 49 lcdse1 se15 se14 se13 se12 se11 se10 se09 se08 51 lcdse3 se31 se30 se29 se28 se27 se26 se25 se24 51 legend: shaded cells are not used by portb. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 111 pic18f87j72 family 10.4 portc, trisc and latc registers portc is an 8-bit wide, bidirectional port. the corresponding data direction and output latch registers are trisc and latc. only portc pins, rc2 through rc7, are digital only pins and can tolerate input voltages up to 5.5v. portc is multiplexed with ccp, mssp and eusart peripheral functions (table 10-7). the pins have schmitt trigger input buffers. the pins for ccp, spi and eusart are also configurable for open-drain out- put whenever these functions are active. open-drain configuration is selected by setting the spiod, ccpxod, and u1od control bits (trisg<7:5> and latg<6>, respectively). rc1 is normally configured as the default peripheral pin for the ccp2 module. assignment of ccp2 is controlled by configuration bit, ccp2mx (default state, ccp2mx = 1 ). when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the contents of the trisc register are affected by peripheral overrides. reading trisc always returns the current contents, even though a peripheral device may be overriding one or more of the pins. rc<7:1> pins are multiplexed with lcd segment drives, controlled by bits in the lcdse1, lcdse2, lcdse3 and lcdse4 registers. i/o port functionality is only available when the lcd segments are disabled. example 10-3: initializing portc note: these pins are configured as digital inputs on any device reset. clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs downloaded from: http:///
pic18f87j72 family ds39979a-page 112 preliminary ? 2010 microchip technology inc. table 10-7: portc functions pin name function tris setting i/o i/o type description rc0/t1oso/ t13cki rc0 0 o dig latc<0> data output. 1 i st portc<0> data input. t1oso x o ana timer1 oscillator output; enabled when timer1 oscillator is enabled. disables digital i/o and lcd segment driver. t13cki 1 i st timer1/timer3 counter input. rc1/t1osi/ ccp2/seg32 rc1 0 o dig latc<1> data output. 1 i st portc<1> data input. t1osi x i ana timer1 oscillator input. ccp2 (1) 0 o dig ccp2 compare/pwm output. 1 i st ccp2 capture input. seg32 x o ana lcd segment 32 output; disables all other pin functions. rc2/ccp1/ seg13 rc2 0 o dig latc<2> data output. 1 i st portc<2> data input. ccp1 0 o dig ccp1 compare/pwm output; takes priority over port data. 1 i st ccp1 capture input. seg13 x o ana lcd segment 13 output; disables all other pin functions. rc3/sck/scl/ seg17 rc3 0 o dig latc<3> data output. 1 i st portc<3> data input. sck 0 o dig spi clock output (mssp module); takes priority over port data. 1 i st spi clock input (mssp module). scl 0 odigi 2 c? clock output (mssp module); takes priority over port data. 1 ii 2 ci 2 c clock input (mssp module); input type depends on module setting. seg17 x o ana lcd segment 17 output; disables all other pin functions. rc4/sdi/sda/ seg16 rc4 0 o dig latc<4> data output. 1 i st portc<4> data input. sdi i st spi data input (mssp module). sda 1 odigi 2 c data output (mssp module); takes priority over port data. 1 ii 2 ci 2 c data input (mssp module); input type depends on module setting. seg16 x o ana lcd segment 16 output; disables all other pin functions. rc5/sdo/ seg12 rc5 0 o dig latc<5> data output. 1 i st portc<5> data input. sdo 0 o dig spi data output (mssp module). seg12 x o ana lcd segment 12 output; disables all other pin functions. rc6/tx1/ck1/ seg27 rc6 0 o dig latc<6> data output. 1 i st portc<6> data input. tx1 1 o dig synchronous serial data output (eusart module); takes priority over port data. ck1 1 o dig synchronous serial data input (eusart m odule); user must configure as an input. 1 i st synchronous serial clock input (eusart module). seg27 x o ana lcd segment 27 output; disables all other pin functions. rc7/rx1/dt1/ seg28 rc7 0 o dig latc<7> data output. 1 i st portc<7> data input. rx1 1 i st asynchronous serial receive data input (eusart module). dt1 1 o dig synchronous serial data output (eusart module); takes priority over port data. 1 i st synchronous serial data input (eusart m odule); user must configure as an input. seg28 x o ana lcd segment 28 output; disables all other pin functions. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt trigger buffer input, ttl = ttl buffe r input, i2c = i 2 c/smbus buffer input, x = dont care (tris bit does not affect port direction or is overridden for this option). note 1: default assignment for ccp2 when ccp2mx configuration bit is set. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 113 pic18f87j72 family table 10-8: summary of register s associated with portc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 52 latc latc7 latbc6 latc5 latcb4 latc3 latc2 latc1 latc0 52 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 52 latg u2od u1od latg4 latg3 latg2 latg1 latg0 52 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 52 lcdse1 se15 se14 se13 se12 se11 se10 se09 se08 51 lcdse2 se23 se22 se21 se20 se19 se18 se17 se16 51 lcdse3 se31 se30 se29 se28 se27 se26 se25 se24 51 lcdse4 se32 51 legend: shaded cells are not used by portc. downloaded from: http:///
pic18f87j72 family ds39979a-page 114 preliminary ? 2010 microchip technology inc. 10.5 portd, trisd and latd registers portd is an 8-bit wide, bidirectional port. the corresponding data direction and output latch registers are trisd and latd. all pins on portd are digital only and tolerate voltages up to 5.5v. all pins on portd are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. each of the portd pins has a weak internal pull-up. a single control bit can turn off all the pull-ups. this is performed by clearing bit, rdpu (portg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on all device resets. all of the portd pins are multiplexed with lcd segment drives, controlled by bits in the lcdse0 register. rd0 is multiplexed with the ctmu pulse generator output. i/o port functionality is only available when the lcd segments are disabled. example 10-4: initializing portd note: these pins are configured as digital inputs on any device reset. clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisd ; set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 115 pic18f87j72 family table 10-9: portd functions table 10-10: summary of register s associated with portd pin name function tris setting i/o i/o type description rd0/seg0/ ctpls rd0 0 o dig latd<0> data output. 1 i st portd<0> data input. seg0 x o ana lcd segment 0 output; disables all other pin functions. ctpls x o dig ctmu pulse generator output rd1/seg1 rd1 0 o dig latd<1> data output. 1 i st portd<1> data input. seg1 x o ana lcd segment 1 output; disables all other pin functions. rd2/seg2 rd2 0 o dig latd<2> data output. 1 i st portd<2> data input. seg2 x o ana lcd segment 2 output; disables all other pin functions. rd3/seg3 rd3 0 o dig latd<3> data output. 1 i st portd<3> data input. seg3 x o ana lcd segment 3 output; disables all other pin functions. rd4/seg4 rd4 0 o dig latd<4> data output. 1 i st portd<4> data input. seg4 x o ana lcd segment 4 output; disables all other pin functions. rd5/seg5 rd5 0 o dig latd<5> data output. 1 i st portd<5> data input. seg5 x o ana lcd segment 5 output; disables all other pin functions. rd6/seg6 rd6 0 o dig latd<6> data output. 1 i st portd<6> data input. seg6 x o ana lcd segment 6 output; disables all other pin functions. rd7/seg7 rd7 0 o dig latd<7> data output. 1 i st portd<7> data input. seg7 x i ana lcd segment 7 output; disables all other pin functions. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt trigger buffer input, x = dont care (tris bit does not affect port direction or is overridden for this opt ion). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 52 latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 52 trisd trisd7 trisd6 trisd5 trisd 4trisd3trisd2trisd1trisd0 52 portg rdpu repu rjpu rg4 rg3 rg2 rg1 rg0 52 lcdse0 se07 se06 se05 se04 se03 se02 se01 se00 51 legend: shaded cells are not used by portd. downloaded from: http:///
pic18f87j72 family ds39979a-page 116 preliminary ? 2010 microchip technology inc. 10.6 porte, trise and late registers porte is a 7-bit wide, bidirectional port. the corresponding data direction and output latch registers are trise and late. all pins on porte are digital only and tolerate voltages up to 5.5v. all pins on porte are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. the re7 pin is also configurable for open-drain output when ccp2 is active on this pin. open-drain configuration is selected by setting the ccp2od control bit (trisg<6>) each of the porte pins has a weak internal pull-up. a single control bit can turn off all the pull-ups. this is performed by clearing bit, repu (portg<6>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on any device reset. pins, re<6:3>, are multiplexed with the lcd common drives. i/o port functions are only available on those porte pins depending on which commons are active. the configuration is determined by the lmux<1:0> control bits (lcdcon<1:0>). the availability is summarized in table 10-11. table 10-11: porte pins available in different lcd drive configurations pins, re1 and re0, are multiplexed with the functions of lcdbias2 and lcdbias1. when lcd bias genera- tion is required (i.e., any application where the device is connected to an external lcd), these pins cannot be used as digital i/o. re7 is multiplexed with the lcd segment drive (seg31) controlled by the lcdse3<7> bit. i/o port function is only available when the segment is disabled. re7 can also be configured as the alternate peripheral pin for the ccp2 module. this is done by clearing the ccp2mx configuration bit. example 10-5: initializing porte note: these pins are configured as digital inputs on any device reset. lcdcon <1:0> active lcd commons porte available for i/o 00 com0 re6, re5, re4 01 com0, com1 re6, re5 10 com0, com1 and com2 re6 11 all (com0 through com3) none note: the pin corresponding to re2 of other pic18f parts has the function of lcdbias3 in this device. it cannot be used as digital i/o. clrf porte ; initialize porte by ; clearing output; data latches clrf late ; alternate method ; to clear output; data latches movlw 03h ; value used to ; initialize data ; direction movwf trise ; set re<1:0> as inputs ; re<7:2> as outputs downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 117 pic18f87j72 family table 10-12: po rte functions table 10-13: summary of registers associated with porte pin name function tris setting i/o i/o type description re0/lcdbias1 re0 0 o dig late<0> data output. 1 i st porte<0> data input. lcdbias1 i ana lcd module bias voltage input. re1/lcdbias2 re1 0 o dig late<1> data output. 1 i st porte<1> data input. lcdbias2 i ana lcd module bias voltage input. re3/com0 re3 0 o dig late<3> data output. 1 i st porte<3> data input. com0 x o ana lcd common 0 output; disables all other outputs. re4/com1 re4 0 o dig late<4> data output. 1 i st porte<4> data input. com1 x o ana lcd common 1 output; disables all other outputs. re5/com2 re5 0 o dig late<5> data output. 1 i st porte<5> data input. com2 x o ana lcd common 2 output; disables all other outputs. re6/com3 re6 0 o dig late<6> data output. 1 i st porte<6> data input. com3 x o ana lcd common 3 output; disables all other outputs. re7/ccp2/ seg31 re7 0 o dig late<7> data output. 1 i st porte<7> data input. ccp2 (1) 0 o dig ccp2 compare/pwm output; takes priority over port data. 1 i st ccp2 capture input. seg31 x o ana segment 31 analog output for lcd; disables digital output. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt trigger buffer input, x = dont care (tris bit does not affect port direction or is overridden for this opt ion). note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porte re7 re6 re5 re4 re3 r e 1r e 05 2 late late7 late6 late5 late4 late3 l a t e 1l a t e 05 2 trise trise7 trise6 trise5 trise4 trise3 trise1 trise0 52 portg rdpu repu rjpu rg4 rg3 rg2 rg1 rg0 52 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 52 lcdcon lcden slpen werr cs1 cs0 lmux1 lmux0 51 lcdse3 se31 se30 se29 se28 se27 se26 se25 se24 51 legend: shaded cells are not used by porte. downloaded from: http:///
pic18f87j72 family ds39979a-page 118 preliminary ? 2010 microchip technology inc. 10.7 portf, latf and trisf registers portf is a 7-bit wide, bidirectional port. the corresponding data direction and output latch registers are trisf and latf. all pins on portf are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. portf is multiplexed with analog peripheral functions, as well as lcd segments. pins, rf1 through rf6, may be used as comparator inputs or outputs by setting the appropriate bits in the cmcon register. to use rf<6:3> as digital inputs, it is also necessary to turn off the comparators. portf is also multiplexed with lcd segment drives controlled by bits in the lcdse2 and lcdse3 registers. i/o port functions are only available when the segments are disabled. example 10-6: initializing portf note 1: on device resets, pins, rf<6:1>, are configured as analog inputs and are read as 0 . 2: to configure portf as digital i/o, turn off comparators and set adcon1 value. clrf portf ; initialize portf by ; clearing output; data latches clrf latf ; alternate method ; to clear output; data latches movlw 07h ; movwf cmcon ; turn off comparators movlw 0fh ; movwf adcon1 ; set portf as digital i/o movlw 0ceh ; value used to ; initialize data ; direction movwf trisf ; set rf3:rf1 as inputs ; rf5:rf4 as outputs ; rf7:rf6 as inputs downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 119 pic18f87j72 family table 10-14: portf functions pin name function tris setting i/o i/o type description rf1/an6/c2out/ seg19 rf1 0 o dig latf<1> data output; not affected by analog input. 1 i st portf<1> data input; disabled when analog input is enabled. an6 1 i ana a/d input channel 6. default configuration on por. c2out 0 o dig comparator 2 output; takes priority over port data. seg19 x o ana lcd segment 19 output; disables all other pin functions. rf2/an7/c1out/ seg20 rf2 0 o dig latf<2> data output; not affected by analog input. 1 i st portf<2> data input; disabled when analog input is enabled. an7 1 i ana a/d input channel 7. default configuration on por. c1out 0 o dig comparator 1 output; takes priority over port data. seg20 x o ana lcd segment 20 output; disables all other pin functions. rf3/an8/seg21/ c2inb rf3 0 o dig latf<3> data output; not affected by analog input. 1 i st portf<3> data input; disabled when analog input is enabled. an8 1 i ana a/d input channel 8 and comparator c2+ input. default input configuration on por; not affected by analog output. seg21 x o ana lcd segment 21 output; disables all other pin functions. c2inb 1 i ana comparator 2 input b. rf4/an9/seg22/ c2ina rf4 0 o dig latf<4> data output; not affected by analog input. 1 i st portf<4> data input; disabled when analog input is enabled. an9 1 i ana a/d input channel 9 and comparator c2- input. default input configuration on por; does not affect digital output. seg22 x o ana lcd segment 22 output; disables all other pin functions. c2ina 1 i ana comparator 2 input a. rf5/an10/cv ref / seg23/c1inb rf5 0 o dig latf<5> data output; not affected by analog input. disabled when cv ref output is enabled. 1 i st portf<5> data input; disabled when analog input is enabled. disabled when cv ref output is enabled. an10 1 i ana a/d input channel 10 and comparator c1+ input. default input configuration on por. cv ref x o ana comparator voltage reference output. enabling this feature disables digital i/o. seg23 x o ana lcd segment 23 output; disables all other pin functions. c1inb 1 i ana comparator 1 input b. rf6/an11/seg24/ c1ina rf6 0 o dig latf<6> data output; not affected by analog input. 1 i st portf<6> data input; disabled when analog input is enabled. an11 1 i ana a/d input channel 11 and comparator c1- input. default input configuration on por; does not affect digital output. seg24 x o ana lcd segment 24 output; disables all other pin functions. c1ina 1 i ana comparator 1 input a. rf7/an5/ss / seg25 rf7 0 o dig latf<7> data output; not affected by analog input. 1 i st portf<7> data input; disabled when analog input is enabled. an5 1 i ana a/d input channel 5. default configuration on por. ss 1 i ttl slave select input for mssp module. seg25 x o ana lcd segment 25 output; disables all other pin functions. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt trigger buffer input, ttl = ttl buffer input, x = dont care (tris bit does not affect port direction or is overridden for this option). downloaded from: http:///
pic18f87j72 family ds39979a-page 120 preliminary ? 2010 microchip technology inc. table 10-15: summary of registers associated with portf name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 5 2 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 5 2 trisf trisf7trisf6trisf5trisf4trisf3trisf2trisf1 5 2 adcon1 trigsel vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 51 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 51 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 51 lcdse2 se23 se22 se21 se20 se19 se18 se17 se16 51 lcdse3 se31 se30 se29 se28 se27 se26 se25 se24 51 legend: = unimplemented, read as 0 . shaded cells are not used by portf. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 121 pic18f87j72 family 10.8 portg, trisg and latg registers portg is a 5-bit wide, bidirectional port. the corresponding data direction and output latch registers are trisg and latg. all pins on portg are digital only and tolerate voltages up to 5.5v. portg is multiplexed with both ausart and lcd functions (table 10-16). when operating as i/o, all portg pins have schmitt trigger input buffers. the rg1 pin is also configurable for open-drain output when the ausart is active. open-drain configuration is selected by setting the u2od control bit (latg<7>). rg4 is multiplexed with lcd segment drives controlled by bits in the lcdse2 register and as the rtcc pin. the i/o port function is only available when the segments are disabled. rg3 and rg2 are multiplexed with v lcap pins for the lcd charge pump and rg0 is multiplexed with the lcdbias0 bias voltage input. when these pins are used for lcd bias generation, the i/o and other functions are unavailable. when enabling peripheral functions, care should be taken in defining tris bits for each portg pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris register. this allows read-modify-write of the tris register without concern due to peripheral overrides. although the port itself is only five bits wide, the portg<7:5> bits are still implemented to control the weak pull-ups on the i/o ports associated with portd, porte and portj. clearing these bits enables the respective port pull-ups. by default, all pull-ups are disabled on device resets. most of the corresponding trisg and latg bits are implemented as open-drain control bits for ccp1, ccp2 and spi (trisg<7:5>), and the usarts (latg<7:6>). setting these bits configures the output pin for the corresponding peripheral for open-drain operation. latg<5> is not implemented. example 10-7: initializing portg clrf portg ; initialize portg by ; clearing output ; data latches clrf latg ; alternate method ; to clear output ; data latches movlw 04h ; value used to ; initialize data ; direction movwf trisg ; set rg1:rg0 as outputs ; rg2 as input; rg4:rg3 as inputs downloaded from: http:///
pic18f87j72 family ds39979a-page 122 preliminary ? 2010 microchip technology inc. table 10-16: po rtg functions table 10-17: summary of registers associated with portg pin name function tris setting i/o i/o type description rg0/lcdbias0 rg0 0 o dig latg<0> data output. 1 i st portg<0> data input. lcdbias0 x i ana lcd module bias voltage input. rg1/tx2/ck2 rg1 0 o dig latg<1> data output. 1 i st portg<1> data input. tx2 1 o dig synchronous serial data output (ausart module); takes priority over port data. ck2 1 o dig synchronous serial data input (aus art module); user must configure as an input. 1 i st synchronous serial clock input (ausart module). rg2/rx2/dt2/ v lcap 1 rg2 0 o dig latg<2> data output. 1 i st portg<2> data input. rx2 1 i st asynchronous serial receive data input (ausart module). dt2 1 o dig synchronous serial data output (ausart module); takes priority over port data. 1 i st synchronous serial data input (aus art module); user must configure as an input. v lcap 1 x i ana lcd charge pump capacitor input. rg3/v lcap 2r g 3 0 o dig latg<3> data output. 1 i st portg<3> data input. v lcap 2 x i ana lcd charge pump capacitor input. rg4/seg26/ rtcc rg4 0 o dig latg<4> data output. 1 i st portg<4> data input. seg26 x o ana lcd segment 26 output; disables all other pin functions. rtcc x o dig rtcc output. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt trigger buffer input, x = dont care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portg rdpu repu rjpu rg4 rg3 rg2 rg1 rg0 52 latg u2od u1od latg4 latg3 latg2 latg1 latg0 52 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 52 lcdse3 se31 se30 se29 se28 se27 se26 se25 se24 51 legend: = unimplemented, read as 0 . shaded cells are not used by portg. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 123 pic18f87j72 family 11.0 timer0 module the timer0 module incorporates the following features: software selectable operation as a timer or counter in both 8-bit or 16-bit modes readable and writable registers dedicated 8-bit, software programmable prescaler selectable clock source (internal or external) edge select for external clock interrupt-on-overflow the t0con register (register 11-1) controls all aspects of the modules operation, including the prescale selection; it is both readable and writable. a simplified block diagram of the timer0 module in 8-bit mode is shown in figure 11-1. figure 11-2 shows a simplified block diagram of the timer0 module in 16-bit mode. register 11-1: t0con: timer0 control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin input edge 0 = internal clock (2/4) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps<2:0> : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value downloaded from: http:///
pic18f87j72 family ds39979a-page 124 preliminary ? 2010 microchip technology inc. 11.1 timer0 operation timer0 can operate as either a timer or a counter. the mode is selected with the t0cs bit (t0con<5>). in timer mode (t0cs = 0 ), the module increments on every clock by default unless a different prescaler value is selected (see section 11.3 prescaler ). if the tmr0 register is written to, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. the counter mode is selected by setting the t0cs bit (= 1 ). in this mode, timer0 increments either on every rising or falling edge of pin, ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit, t0se (t0con<4>); clearing this bit selects the rising edge. restrictions on the external clock input are discussed below. an external clock source can be used to drive timer0, however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (t osc ). there is a delay between synchronization and the onset of incrementing the timer/counter. 11.2 timer0 reads and writes in 16-bit mode tmr0h is not the actual high byte of timer0 in 16-bit mode. it is actually a buffered version of the real high byte of timer0, which is not directly readable nor writ- able (refer to figure 11-2). tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this provides the ability to read all 16 bits of timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. similarly, a write to the high byte of timer0 must also take place through the tmr0h buffer register. the high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. figure 11-1: timer0 block diagram (8-bit mode) figure 11-2: timer0 block diagram (16-bit mode) note: upon reset, timer0 is enabled in 8-bit mode with the clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 sync with internal clocks tmr0l (2 t cy delay) internal data bus psa t0ps<2:0> set tmr0if on overflow 3 8 8 programmable prescaler note: upon reset, timer0 is enabled in 8-bit mode with the clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 sync with internal clocks tmr0l (2 t cy delay) internal data bus 8 psa t0ps<2:0> set tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l 8 programmable prescaler downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 125 pic18f87j72 family 11.3 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not directly readable or writable. its value is set by the psa and t0ps<2:0> bits (t0con<3:0>) which determine the prescaler assignment and prescale ratio. clearing the psa bit assigns the prescaler to the timer0 module. when it is assigned, prescale values from 1:2 through 1:256, in power-of-2 increments, are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0 , movwf tmr0 , bsf tmr0 , etc.) clear the prescaler count. 11.3.1 switching prescaler assignment the prescaler assignment is fully under software control and can be changed on-the-fly during program execution. 11.4 timer0 interrupt the tmr0 interrupt is generated when the tmr0 register overflows from ffh to 00h in 8-bit mode or from ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if flag bit. the interrupt can be masked by clearing the tmr0ie bit (intcon<5>). before re-enabling the interrupt, the tmr0if bit must be cleared in software by the interrupt service routine. since timer0 is shut down in sleep mode, the tmr0 interrupt cannot awaken the processor from sleep. table 11-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page tmr0l timer0 register low byte 50 tmr0h timer0 register high byte 50 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 50 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 52 legend: = unimplemented, read as 0 . shaded cells are not used by timer0. note 1: ra<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as 0 . downloaded from: http:///
pic18f87j72 family ds39979a-page 126 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 127 pic18f87j72 family 12.0 timer1 module the timer1 timer/counter module incorporates these features: software selectable operation as a 16-bit timer or counter readable and writable 8-bit registers (tmr1h and tmr1l) selectable clock source (internal or external) with device clock or timer1 oscillator internal options interrupt-on-overflow reset on ccp special event trigger device clock status flag (t1run) a simplified block diagram of the timer1 module is shown in figure 12-1. a block diagram of the modules operation in read/write mode is shown in figure 12-2. the module incorporates its own low-power oscillator to provide an additional clocking option. the timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. timer1 can also be used to provide real-time clock (rtc) functionality to applications with only a minimal addition of external components and code overhead. timer1 is controlled through the t1con control register (register 12-1). it also contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled or disabled by setting or clearing control bit, tmr1on (t1con<0>). register 12-1: t1con: ti mer1 control register r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 t1run: timer1 system clock status bit 1 = device clock is derived from timer1 oscillator 0 = device clock is derived from another source bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin, rc0/t1oso/t13cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 =stops timer1 downloaded from: http:///
pic18f87j72 family ds39979a-page 128 preliminary ? 2010 microchip technology inc. 12.1 timer1 operation timer1 can operate in one of these modes: timer synchronous counter asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). when tmr1cs is cleared (= 0 ), timer1 increments on every internal instruction cycle (f osc /4). when the bit is set, timer1 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when timer1 is enabled, the rc1/t1osi/seg32 and rc0/t1oso/t13cki pins become inputs. this means the values of trisc<1:0> are ignored and the pins are read as 0 . figure 12-1: timer1 block diagram (8-bit mode) figure 12-2: timer1 block diagram (16-bit read/write mode) t1sync tmr1cs t1ckps<1:0> sleep input t1oscen (1) f osc /4 internal clock on/off 10 2 t1oso/t13cki t1osi 10 tmr1on tmr1l set tmr1if on overflow tmr1 high byte clear tmr1 (ccp special event trigger) timer1 oscillator note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. on/off timer1 timer1 clock input prescaler 1, 2, 4, 8 synchronize detect t1sync tmr1cs t1ckps<1:0> sleep input t1oscen (1) f osc /4 internal clock 10 2 t1oso/t13cki t1osi note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 10 tmr1l internal data bus 8 set tmr1if on overflow tmr1 tmr1h high byte 8 8 8 read tmr1l write tmr1l 8 tmr1on clear tmr1 (ccp special event trigger) timer1 oscillator on/off timer1 timer1 clock input prescaler 1, 2, 4, 8 synchronize detect downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 129 pic18f87j72 family 12.2 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 12-2). when the rd16 control bit (t1con<7>) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer register. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. the timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writable in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. 12.3 timer1 oscillator an on-chip crystal oscillator circuit is incorporated between pins, t1osi (input) and t1oso (amplifier output). it is enabled by setting the timer1 oscillator enable bit, t1oscen (t1con<3>). the oscillator is a low-power circuit rated for 32 khz crystals. it will continue to run during all power-managed modes. the circuit for a typical lp oscillator is shown in figure 12-3. table 12-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. figure 12-3: external components for the timer1 lp oscillator table 12-1: capacitor selection for the timer1 oscillator (2,3,4) 12.3.1 using timer1 as a clock source the timer1 oscillator is also available as a clock source in power-managed modes. by setting the system clock select bits, scs<1:0> (osccon<1:0>), to 01 , the device switches to sec_run mode. both the cpu and peripherals are clocked from the timer1 oscillator. if the idlen bit (osccon<7>) is cleared and a sleep instruction is executed, the device enters sec_idle mode. additional details are available in section 4.0 power-managed modes . whenever the timer1 oscillator is providing the clock source, the timer1 system clock status flag, t1run (t1con<6>), is set. this can be used to determine the controllers current clocking mode. it can also indicate the clock source being currently used by the fail-safe clock monitor. if the clock monitor is enabled and the timer1 oscillator fails while providing the clock, polling the t1run bit will indicate whether the clock is being provided by the timer1 oscillator or another source. note: see the notes with table 12-1 for additional information about capacitor selection. c1 c2 xtal t1osi t1oso 32.768 khz 27 pf 27 pf pic18f87j72 oscillator type freq. c1 c2 lp 32.768 khz 27 pf (1) 27 pf (1) note 1: microchip suggests these values as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only. downloaded from: http:///
pic18f87j72 family ds39979a-page 130 preliminary ? 2010 microchip technology inc. 12.3.2 timer1 oscillator layout considerations the timer1 oscillator circuit draws very little power during operation. due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. the oscillator circuit, shown in figure 12-3, should be located as close as possible to the microcontroller. there should be no circuits passing within the oscillator circuit boundaries other than v ss or v dd . if a high-speed circuit must be located near the oscilla- tor (such as the ccp1 pin in output compare or pwm mode, or the primary oscillator using the osc2 pin), a grounded guard ring around the oscillator circuit, as shown in figure 12-4, may be helpful when used on a single-sided pcb or in addition to a ground plane. figure 12-4: oscillator circuit with grounded guard ring 12.4 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled or disabled by setting or clearing the timer1 interrupt enable bit, tmr1ie (pie1<0>). 12.5 resetting timer1 using the ccp special event trigger if ccp1 or ccp2 is configured to use timer1 and to generate a special event trigger in compare mode (ccpxm<3:0> = 1011 ), this signal will reset timer3. the trigger from ccp2 will also start an a/d conversion if the a/d module is enabled (see section 16.3.4 special event trigger for more information). the module must be configured as either a timer or a synchronous counter to take advantage of this feature. when used this way, the ccprxh:ccprxl register pair effectively becomes a period register for timer1. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger, the write operation will take precedence. 12.6 using timer1 as a real-time clock adding an external lp oscillator to timer1 (such as the one described in section 12.3 timer1 oscillator above) gives users the option to include rtc function- ality to their applications. this is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. when operating in sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate rtc device and battery backup. the application code routine, rtcisr , shown in example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an interrupt service routine. incrementing the tmr1 register pair to overflow triggers the interrupt and calls the routine which increments the seconds counter by one. additional counters for minutes and hours are incremented as the previous counter overflows. since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 khz clock would take 2 seconds. to force the overflow at the required one-second intervals, it is necessary to pre- load it. the simplest method is to set the msb of tmr1h with a bsf instruction. note that the tmr1l register is never preloaded or altered; doing so may introduce cumulative error over many cycles. for this method to be accurate, timer1 must operate in asynchronous mode and the timer1 overflow interrupt must be enabled (pie1<0> = 1 ) as shown in the routine, rtcinit . the timer1 oscillator must also be enabled and running at all times. v dd osc1 v ss osc2 rc0 rc1 rc2 note: not drawn to scale. note: the special event triggers from the ccpx module will not set the tmr1if interrupt flag bit (pir1<0>). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 131 pic18f87j72 family example 12-1: implementing a real-time clock using a timer1 interrupt service table 12-2: registers associated with timer1 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 adif rc1if tx1if sspif tmr2if tmr1if 52 pie1 adie rc1ie tx1ie sspie tmr2ie tmr1ie 52 ipr1 adip rc1ip tx1ip sspip tmr2ip tmr1ip 52 tmr1l timer1 register low byte 50 tmr1h timer1 register high byte 50 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 50 legend: shaded cells are not used by the timer1 module. rtcinit movlw 80h ; preload tmr1 register pair movwf tmr1h ; for 1 second overflow clrf tmr1l movlw b00001111 ; configure for external clock, movwf t1con ; asynchronous operation, external oscillator clrf secs ; initialize timekeeping registers clrf mins ; movlw .12 movwf hours bsf pie1, tmr1ie ; enable timer1 interrupt return rtcisr bsf tmr1h, 7 ; preload for 1 sec overflow bcf pir1, tmr1if ; clear interrupt flag incf secs, f ; increment seconds movlw .59 ; 60 seconds elapsed? cpfsgt secs return ; no, done clrf secs ; clear seconds incf mins, f ; increment minutes movlw .59 ; 60 minutes elapsed? cpfsgt mins return ; no, done clrf mins ; clear minutes incf hours, f ; increment hours movlw .23 ; 24 hours elapsed? cpfsgt hours return ; no, done clrf hours ; reset hours return ; done downloaded from: http:///
pic18f87j72 family ds39979a-page 132 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 133 pic18f87j72 family 13.0 timer2 module the timer2 module incorporates the following features: 8-bit timer and period registers (tmr2 and pr2, respectively) readable and writable (both registers) software programmable prescaler (1:1, 1:4 and 1:16) software programmable postscaler (1:1 through 1:16) interrupt on tmr2 to pr2 match optional use as the shift clock for the mssp module the module is controlled through the t2con register (register 13-1), which enables or disables the timer and configures the prescaler and postscaler. timer2 can be shut off by clearing control bit, tmr2on (t2con<2>), to minimize power consumption. a simplified block diagram of the module is shown in figure 13-1. 13.1 timer2 operation in normal operation, tmr2 is incremented from 00h on each clock (f osc /4). a 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by-16 prescale options. these are selected by the prescaler control bits, t2ckps<1:0> (t2con<1:0>). the value of tmr2 is compared to that of the period register, pr2, on each clock cycle. when the two values match, the comparator generates a match signal as the timer output. this signal also resets the value of tmr2 to 00h on the next cycle and drives the output counter/postscaler (see section 13.2 timer2 interrupt ). the tmr2 and pr2 registers are both directly readable and writable. the tmr2 register is cleared on any device reset, while the pr2 register initializes at ffh. both the prescaler and postscaler counters are cleared on the following events: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr2 is not cleared when t2con is written. register 13-1: t2con: ti mer2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6-3 t2outps<3:0>: timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 downloaded from: http:///
pic18f87j72 family ds39979a-page 134 preliminary ? 2010 microchip technology inc. 13.2 timer2 interrupt timer2 can also generate an optional device interrupt. the timer2 output signal (tmr2 to pr2 match) pro- vides the input for the 4-bit output counter/postscaler. this counter generates the tmr2 match interrupt flag which is latched in tmr2if (pir1<1>). the interrupt is enabled by setting the tmr2 match interrupt enable bit, tmr2ie (pie1<1>). a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, t2outps<3:0> (t2con<6:3>). 13.3 timer2 output the unscaled output of tmr2 is available primarily to the ccp modules, where it is used as a time base for operations in pwm mode. timer2 can be optionally used as the shift clock source for the mssp module operating in spi mode. additional information is provided in section 18.0 master synchronous serial port (mssp) module . figure 13-1: timer2 block diagram table 13-1: registers associated with timer2 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 adif rc1if tx1if sspif t m r 2 i f tmr1if 52 pie1 adie rc1ie tx1ie sspie t m r 2 i e tmr1ie 52 ipr1 adip rc1ip tx1ip sspip t m r 2 i p tmr1ip 52 tmr2 timer2 register 50 t2con t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 50 pr2 timer2 period register 50 legend: = unimplemented, read as 0 . shaded cells are not used by the timer2 module. comparator tmr2 output tmr2 postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 4 t2outps<3:0> t2ckps<1:0> set tmr2if internal data bus 8 reset tmr2/pr2 8 8 (to pwm or mssp) match downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 135 pic18f87j72 family 14.0 timer3 module the timer3 timer/counter module incorporates these features: software selectable operation as a 16-bit timer or counter readable and writable 8-bit registers (tmr3h and tmr3l) selectable clock source (internal or external) with device clock or timer1 oscillator internal options interrupt-on-overflow module reset on ccp special event trigger a simplified block diagram of the timer3 module is shown in figure 14-1. a block diagram of the modules operation in read/write mode is shown in figure 14-2. the timer3 module is controlled through the t3con register (register 14-1). it also selects the clock source options for the ccp modules. see section 16.2.2 timer1/timer3 mode selection for more information. register 14-1: t3con: ti mer3 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6,3 t3ccp<2:1>: timer3 and timer1 to ccpx enable bits 1x = timer3 is the capture/compare clock source for the ccp modules 01 = timer3 is the capture/compare clock source for ccp2; timer1 is the capture/compare clock source for ccp1 00 = timer1 is the capture/compare clock source for the ccp modules bit 5-4 t3ckps<1:0> : timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the device clock comes from timer1/timer3.) when tmr3cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0 : this bit is ignored. timer3 uses the internal clock when tmr3cs = 0 . bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t13cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 downloaded from: http:///
pic18f87j72 family ds39979a-page 136 preliminary ? 2010 microchip technology inc. 14.1 timer3 operation timer3 can operate in one of three modes: timer synchronous counter asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con<1>). when tmr3cs is cleared (= 0 ), timer3 increments on every internal instruction cycle (f osc /4). when the bit is set, timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. as with timer1, the rc1/t1osi/seg32 and rc0/t1oso/t13cki pins become inputs when the timer1 oscillator is enabled. this means the values of trisc<1:0> are ignored and the pins are read as 0 . figure 14-1: timer3 block diagram (8-bit mode) figure 14-2: timer3 block diagram (16-bit read/write mode) t3sync tmr3cs t3ckps<1:0> sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 10 2 t1oso/t13cki t1osi 10 tmr3on tmr3l set tmr3if on overflow tmr3 high byte timer1 oscillator note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. on/off timer3 ccpx special event trigger ccpx select from t3con<6,3> clear tmr3 timer1 clock input t3sync tmr3cs t3ckps<1:0> sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 10 2 t13cki/t1oso t1osi note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to elimin ate power drain. 10 tmr3l internal data bus 8 set tmr3if on overflow tmr3 tmr3h high byte 8 8 8 read tmr3l write tmr3l 8 tmr3on ccpx special event trigger timer1 oscillator on/off timer3 timer1 clock input ccpx select from t3con<6,3> clear tmr3 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 137 pic18f87j72 family 14.2 timer3 16-bit read/write mode timer3 can be configured for 16-bit reads and writes (see figure 14-2). when the rd16 control bit (t3con<7>) is set, the address for tmr3h is mapped to a buffer register for the high byte of timer3. a read from tmr3l will load the contents of the high byte of timer3 into the timer3 high byte buffer register. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. a write to the high byte of timer3 must also take place through the tmr3h buffer register. the timer3 high byte is updated with the contents of tmr3h when a write occurs to tmr3l. this allows a user to write all 16 bits to both the high and low bytes of timer3 at once. the high byte of timer3 is not directly readable or writable in this mode. all reads and writes must take place through the timer3 high byte buffer register. writes to tmr3h do not clear the timer3 prescaler. the prescaler is only cleared on writes to tmr3l. 14.3 using the timer1 oscillator as the timer3 clock source the timer1 internal oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen (t1con<3>) bit. to use it as the timer3 clock source, the tmr3cs bit must also be set. as previously noted, this also configures timer3 to increment on every rising edge of the oscillator source. the timer1 oscillator is described in section 12.0 timer1 module . 14.4 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and overflows to 0000h. the timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, tmr3if (pir2<1>). this interrupt can be enabled or disabled by setting or clearing the timer3 interrupt enable bit, tmr3ie (pie2<1>). 14.5 resetting timer3 using the ccp special event trigger if ccp1 or ccp2 is configured to use timer3 and to generate a special event trigger in compare mode (ccpxm<3:0> = 1011 ), this signal will reset timer3. the trigger from ccp2 will also start an a/d conversion if the a/d module is enabled (see section 16.3.4 special event trigger for more information). the module must be configured as either a timer or synchronous counter to take advantage of this feature. when used this way, the ccprxh:ccprxl register pair effectively becomes a period register for timer3. if timer3 is running in asynchronous counter mode, the reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from a ccp module, the write will take precedence. table 14-1: registers associated with timer3 as a timer/counter note: the special event triggers from the ccpx module will not set the tmr3if interrupt flag bit (pir2<1>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir2 oscfif cmif bclif lvdif tmr3if 5 2 pie2 oscfie cmie bclie lvdie tmr3ie 5 2 ipr2 oscfip cmip bclip lvdip tmr3ip 5 2 tmr3l timer3 register low byte 51 tmr3h timer3 register high byte 51 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 50 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 51 legend: = unimplemented, read as 0 . shaded cells are not used by the timer3 module. downloaded from: http:///
pic18f87j72 family ds39979a-page 138 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 139 pic18f87j72 family 15.0 real-time clock and calendar (rtcc) the key features of the real-time clock and calendar (rtcc) module are: time: hours, minutes and seconds 24-hour format (military time) calendar: weekday, date, month and year alarm configurable year range: 2000 to 2099 leap year correction bcd format for compact firmware optimized for low-power operation user calibration with auto-adjust calibration range: ? 2.64 seconds error per month requirements: external 32.768 khz clock crystal alarm pulse or seconds clock output on rtcc pin the rtcc module is intended for applications, where accurate time must be maintained for an extended period with minimum to no intervention from the cpu. the module is optimized for low-power usage in order to provide extended battery life while keeping track of time. the module is a 100-year clock and calendar with auto- matic leap year detection. the range of the clock is from 00:00:00 (midnight) on january 1, 2000 to 23:59:59 on december 31, 2099. hours are measured in 24-hour (military time) format. the clock provides a granularity of one second with half-second visibility to the user. figure 15-1: rtcc block diagram rtcc prescalers rtcc timer comparator compare registers repeat counter year mthdy wkdyhr minsec almthdy alwdhr alminsec with masks rtcc interrupt logic rtccfg alrmrpt alarm event 0.5s rtcc clock domain alarm pulse rtcc interrupt cpu clock domain rtcvalx alrmvalx rtcc pin rtcoe 32.768 khz input from timer1 oscillator internal rc downloaded from: http:///
pic18f87j72 family ds39979a-page 140 preliminary ? 2010 microchip technology inc. 15.1 rtcc module registers the rtcc module registers are divided into following categories: rtcc control registers rtccfg rtccal padcfg1 alrmcfg alrmrpt rtcc value registers rtcvalh and rtcvall C can access the fol- lowing registers - year -month -day - weekday -hour - minute - second alarm value registers alrmvalh and alrmvall C can access the following registers: - alrmmnth -alrmday -alrmwd -alrmhr - alrmmin - alrmsec note: the rtcvalh and rtcvall registers can be accessed through rtcrpt<1:0>. alrmvalh and alrmvall can be accessed through alrmptr<1:0>. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 141 pic18f87j72 family 15.1.1 rtcc control registers register 15-1: rtccfg: rtcc configuration register (1) r/w-0 u-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 rtcen (2) rtcwren rtcsync halfsec (3) rtcoe rtcptr1 rtcptr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 rtcen: rtcc enable bit (2) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 6 unimplemented: read as 0 bit 5 rtcwren: rtcc value registers write enable bit 1 = rtcvalh and rtcvall registers can be written to by the user 0 = rtcvalh and rtcvall registers are locked out from being written to by the user bit 4 rtcsync: rtcc value registers read synchronization bit 1 = rtcvalh, rtcvall and alrmrpt registers can change while reading due to a rollover ripple resulting in an invalid data read. if the register is read twice and results in the same data, the data can be assumed to be valid. 0 = rtcvalh, rtcvall and alcfgrpt registers can be read without concern over a rollover ripple bit 3 halfsec: half-second status bit (3) 1 = second half period of a second 0 = first half period of a second bit 2 rtcoe: rtcc output enable bit 1 = rtcc clock output is enabled 0 = rtcc clock output is disabled bit 1-0 rtcptr<1:0>: rtcc value register window pointer bits points to the corresponding rtcc value registers when reading rtcvalh and rtcvall registers. the rtcptr<1:0> value decrements on every read or write of rtcvalh<7:0> until it reaches 00 . rtcvalh: 00 = minutes 01 = weekday 10 = month 11 = reserved rtcvall: 00 = seconds 01 = hours 10 = day 11 = year note 1: the rtccfg register is only affected by a por. for resets other than por, rtcc will continue to run even if the device is in reset. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only; it is cleared to 0 on a write to the lower half of the minsec register. downloaded from: http:///
pic18f87j72 family ds39979a-page 142 preliminary ? 2010 microchip technology inc. register 15-2: rtccal: rtcc calibration register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 cal<7:0>: rtc drift calibration bits 01111111 = maximum positive adjustment; adds 508 rtc clock pulses every minute .. . 00000001 = minimum positive adjustment; adds four rtc clock pulses every minute 00000000 = no adjustment 11111111 = minimum negative adjustment; subtracts four rtc clock pulses every minute .. . 10000000 = maximum negative adjustment; subtracts 512 rtc clock pulses every minute register 15-3: padcfg1: pad configuration register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 rtsecsel1 (1) rtsecsel0 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-3 unimplemented: read as 0 bit 2-1 rtsecsel<1:0>: rtcc seconds clock output select bits (1) 11 = reserved; do not use 10 = rtcc source clock is selected for the rtcc pin (pin can be intosc or timer1 oscillator, depending on the rtcosc (config3l<1>) bit setting) (2) 01 = rtcc seconds clock is selected for the rtcc pin 00 = rtcc alarm pulse is selected for the rtcc pin bit 0 unimplemented: read as 0 note 1: to enable the actual rtcc output, the rtcoe (rtccfg<2>) bit must be set. 2: if the timer1 oscillator is the clock source for rtcc, t1oscen bit should be set (t1con<3> = 1 ). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 143 pic18f87j72 family register 15-4: alrmcfg: al arm configuration register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 alrmen: alarm enable bit 1 = alarm is enabled (cleared automatically after an alarm event whenever arpt<7:0> = 00 and chime = 0 ) 0 = alarm is disabled bit 6 chime: chime enable bit 1 = chime is enabled; alrmptr<1:0> bits are allowed to roll over from 00h to ffh 0 = chime is disabled; alrmptr<1:0> bits stop once they reach 00h bit 5-2 amask<3:0>: alarm mask configuration bits 0000 = every half second 0001 = every second 0010 = every 10 seconds 0011 = every minute 0100 = every 10 minutes 0101 = every hour 0110 = once a day 0111 = once a week 1000 = once a month 1001 = once a year (except when configured for february 29 th , once every four years) 101x = reserved C do not use 11xx = reserved C do not use bit 1-0 alrmptr<1:0>: alarm value register window pointer bits points to the corresponding alarm value registers when reading the alrmvalh and alrmvall registers. the alrmptr<1:0> value decrements on every read or write of alrmvalh until it reaches 00 . alrmvalh: 00 = alrmmin 01 =alrmwd 10 =alrmmnth 11 = unimplemented alrmvall: 00 = alrmsec 01 =alrmhr 10 =alrmday 11 = unimplemented downloaded from: http:///
pic18f87j72 family ds39979a-page 144 preliminary ? 2010 microchip technology inc. 15.1.2 rtcvalh and rtcvall register mappings register 15-5: alrmrpt: alarm calibration register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 arpt<7:0>: alarm repeat counter value bits 11111111 = alarm will repeat 255 more times .. . 00000000 = alarm will not repeat the counter decrements on any alarm event. the counter is prevented from rolling over from 00h to ffh unless chime = 1 . register 15-6: reserved register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 unimplemented: read as 0 register 15-7: year: year value register (1) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x yrten3 yrten2 yrten1 yrten0 yrone3 yrone2 yrone1 yrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-4 yrten<3:0>: binary coded decimal value of years tens digit bits contains a value from 0 to 9. bit 3-0 yrone<3:0>: binary coded decimal value of years ones digit bits contains a value from 0 to 9. note 1: a write to the year register is only allowed when rtcwren = 1 . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 145 pic18f87j72 family register 15-8: month: month value register (1) u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x mthten0 mthone3 mthone2 mthone1 mthone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as 0 bit 4 mthten0: binary coded decimal value of months tens digit bits contains a value of 0 or 1. bit 3-0 mthone<3:0>: binary coded decimal value of months ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 15-9: day: day value register (1) u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x dayten1 dayten0 dayone3 dayone2 dayone1 dayone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5-4 dayten<1:0>: binary coded decimal value of days tens digit bits contains a value from 0 to 3. bit 3-0 dayone<3:0>: binary coded decimal value of days ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 15-10: weekday: weekday value register (1) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x wday2 wday1 wday0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-3 unimplemented: read as 0 bit 2-0 wday<2:0>: binary coded decimal value of weekday digit bits contains a value from 0 to 6. note 1: a write to this register is only allowed when rtcwren = 1 . downloaded from: http:///
pic18f87j72 family ds39979a-page 146 preliminary ? 2010 microchip technology inc. register 15-11: hour: hour value register (1) u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5-4 hrten<1:0>: binary coded decimal value of hours tens digit bits contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary coded decimal value of hours ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 15-12: minute: minute value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6-4 minten<2:0>: binary coded decimal value of minutes tens digit bits contains a value from 0 to 5. bit 3-0 minone<3:0>: binary coded decimal value of minutes ones digit bits contains a value from 0 to 9. register 15-13: second: second value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6-4 secten<2:0>: binary coded decimal value of seconds tens digit bits contains a value from 0 to 5. bit 3-0 secone<3:0>: binary coded decimal value of seconds ones digit bits contains a value from 0 to 9. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 147 pic18f87j72 family 15.1.3 alrmvalh and alrmvall register mappings register 15-14: alrmmnth: alarm month value register (1) u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x mthten0 mthone3 mthone2 mthone1 mthone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as 0 bit 4 mthten0: binary coded decimal value of months tens digit bits contains a value of 0 or 1. bit 3-0 mthone<3:0>: binary coded decimal value of months ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 15-15: alrmday: alarm day value register (1) u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x dayten1 dayten0 dayone3 dayone2 dayone1 dayone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5-4 dayten<1:0>: binary coded decimal value of days tens digit bits contains a value from 0 to 3. bit 3-0 dayone<3:0>: binary coded decimal value of days ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 15-16: alrmwd: alarm weekday value register (1) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x wday2 wday1 wday0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-3 unimplemented: read as 0 bit 2-0 wday<2:0>: binary coded decimal value of weekday digit bits contains a value from 0 to 6. note 1: a write to this register is only allowed when rtcwren = 1 . downloaded from: http:///
pic18f87j72 family ds39979a-page 148 preliminary ? 2010 microchip technology inc. register 15-17: alrmhr: alarm hours value register (1) u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5-4 hrten<1:0>: binary coded decimal value of hours tens digit bits contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary coded decimal value of hours ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 15-18: alrmmin: alarm minutes value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6-4 minten<2:0>: binary coded decimal value of minutes tens digit bits contains a value from 0 to 5. bit 3-0 minone<3:0>: binary coded decimal value of minutes ones digit bits contains a value from 0 to 9. register 15-19: alrmsec: alarm seconds value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6-4 secten<2:0>: binary coded decimal value of seconds tens digit bits contains a value from 0 to 5. bit 3-0 secone<3:0>: binary coded decimal value of seconds ones digit bits contains a value from 0 to 9. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 149 pic18f87j72 family 15.1.4 rtcen bit write an attempt to write to the rtcen bit while rtcwren = 0 will be ignored. rtcwren must be set before a write to rtcen can take place. like the rtcen bit, the rtcvalh and rtcvall registers can only be written to when rtcwren = 1 . a write to these registers, while rtcwren = 0 , will be ignored. 15.2 operation 15.2.1 register interface the register interface for the rtcc and alarm values is implemented using the binary coded decimal (bcd) format. this simplifies the firmware when using the module, as each of the digits is contained within its own 4-bit value (see figure 15-2 and figure 15-3). figure 15-2: timer digit format figure 15-3: alarm digit format 0-6 0-9 0-9 0-3 0-9 0-9 0-9 0-9 0-2 0-5 0-5 0/1 day of week year day hours (24-hour format) minutes seconds 1/2 second bit 0-1 0-9 month (binary format) 0-6 0-3 0-9 0-9 0-9 0-9 0-2 0-5 0-5 day of week day hours (24-hour format) minutes seconds 0-1 0-9 month downloaded from: http:///
pic18f87j72 family ds39979a-page 150 preliminary ? 2010 microchip technology inc. 15.2.2 clock source as mentioned earlier, the rtcc module is intended to be clocked by an external real-time clock crystal oscillating at 32.768 khz, but can also be an internal oscillator. the rtcc clock selection is decided by the rtcosc bit (config3l<1>). calibration of the crystal can be done through this mod- ule to yield an error of 3 seconds or less per month. (for further details, see section 15.2.9 calibration .) figure 15-4: clock source multiplexing 15.2.2.1 real-time clock enable the rtcc module can be clocked by an external, 32.768 khz crystal (timer1 oscillator) or the internal rc oscillator, which can be selected in config3l<1>. if the external clock is used, the timer1 oscillator should be enabled by setting the t1oscen bit (t1con<3> = 1 ). if intrc is providing the clock, the intrc clock can be brought out to the rtcc pin by the rtsecsel<1:0> bits in the padcfg register. 15.2.3 digit carry rules this section explains which timer values are affected when there is a rollover. time of day: from 23:59:59 to 00:00:00 with a carry to the day field month: from 12/31 to 01/01 with a carry to the year field day of week: from 6 to 0 with no carry (see table 15-1) year carry: from 99 to 00; this also surpasses the use of the rtcc for the day to month rollover schedule, see table 15-2. considering that the following values are in bcd for- mat, the carry to the upper bcd digit will occur at a count of 10 and not at 16 (seconds, minutes, hours, weekday, days and months). table 15-1: day of week schedule table 15-2: day to month rollover schedule note 1: writing to the lower half of the minsec register resets all counters, allowing fraction of a second synchronization; clock prescaler is held in reset when rtcen = 0 . 32.768 khz xtal 1:16384 half second (1) half-second clock one-second clock year month day day of week second hour:minute clock prescaler (1) from sosc internal rc config 3l<1> day of week sunday 0 monday 1 tuesday 2 wednesday 3 thursday 4 friday 5 saturday 6 month maximum day field 01 (january) 31 02 (february) 28 or 29 (1) 03 (march) 31 04 (april) 30 05 (may) 31 06 (june) 30 07 (july) 31 08 (august) 31 09 (september) 30 10 (october) 31 11 (november) 30 12 (december) 31 note 1: see section 15.2.4 leap year . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 151 pic18f87j72 family 15.2.4 leap year since the year range on the rtcc module is 2000 to 2099, the leap year calculation is determined by any year divisible by 4 in the above range. only february is effected in a leap year. february will have 29 days in a leap year and 28 days in any other year. 15.2.5 general functionality all timer registers containing a time value of seconds or greater are writable. the us er configures the time by writing the required year, month, day, hour, minutes and seconds to the timer register s via register pointers (see section 15.2.8 register mapping ). the timer uses the newly written values and proceeds with the count from the required starting point. the rtcc is enabled by setting the rtcen bit (rtccfg<7>). if enabled while adjusting these regis- ters, the timer still continues to increment. however, any time the minsec register is written to, both of the timer prescalers are reset to 0 . this allows fraction of a second synchronization. the timer registers are updated in the same cycle as the write instructions execution by the cpu. the user must ensure that when rtcen = 1 , the updated regis- ters will not be incremented at the same time. this can be accomplished in several ways: by checking the rtcsync bit (rtccfg<4>) by checking the preceding digits from which a carry can occur by updating the registers immediately following the seconds pulse (or alarm interrupt) the user has visibility to the half-second field of the counter. this value is read-only and can be reset only by writing to the lower half of the seconds register. 15.2.6 safety window for register reads and writes the rtcsync bit indicates a time window during which the rtcc clock domain registers can be safely read and written without concern about a rollover. when rtcsync = 0 , the registers can be safely accessed by the cpu. whether rtcsync = 1 or 0 , the user should employ a firmware solution to ensure that the data read did not fall on a rollover boundary, resulting in an invalid or partial read. this firmware solution would consist of reading each register twice and then comparing the two values. if the two values matched, then a rollover did not occur. 15.2.7 write lock in order to perform a write to any of the rtcc timer registers, the rtcwren bit (rtccfg<5>) must be set. to avoid accidental writes to the rtcc timer register, it is recommended that the rtcwren bit (rtccfg<5>) be kept clear at any time other than while writing to it. for the rtcwren bit to be set, there is only one instruction cycle time window allowed between the 55h/aa sequence and the setting of rtcwren. for that reason, it is recommended that users follow the code example in example 15-1. example 15-1: setting the rtcwren bit 15.2.8 register mapping to limit the register interface, the rtcc timer and alarm timer registers are accessed through corresponding register pointers. the rtcc value register window (rtcvalh and rtcvall) uses the rtcptr bits (rtccfg<1:0>) to select the required timer register pair. by reading or writing to the rtcvalh register, the rtcc pointer value (rtcptr<1:0>) decrements by 1 until it reaches 00 . once it reaches 00 , the minutes and seconds value will be accessible through rtcvalh and rtcvall until the pointer value is manually changed. table 15-3: rtcvalh and rtcvall register mapping the alarm value register window (alrmvalh and alrmvall) uses the alrmptr bits (alrmcfg<1:0>) to select the desired alarm register pair. by reading or writing to the alrmvalh register, the alarm pointer value, alrmptr<1:0>, decrements by 1 until it reaches 00 . once it reaches 00 , the alrmmin and alrmsec value will be accessible through alrmvalh and alrmvall until the pointer value is manually changed. movlw 0x55 movwf eecon2 movlw 0xaa movwf eecon2 bsf rtccfg,rtcwren rtcptr<1:0> rtcc value register window rtcvalh rtcvall 00 minutes seconds 01 weekday hours 10 month day 11 year downloaded from: http:///
pic18f87j72 family ds39979a-page 152 preliminary ? 2010 microchip technology inc. table 15-4: alrmval register mapping 15.2.9 calibration the real-time crystal input can be calibrated using the periodic auto-adjust feature. when properly calibrated, the rtcc can provide an error of less than three seconds per month. to perform this calibration, find the number of error clock pulses and store the value into the lower half of the rtccal register. the 8-bit, signed value, loaded into rtccal, is multiplied by 4 and will either be added or subtracted from the rtcc timer, once every minute. to calibrate the rtcc module: 1. use another timer resource on the device to find the error of the 32.768 khz crystal. 2. convert the number of error clock pulses per minute (see equation 15-1). if the oscillator is faster than ideal (negative result from step 2), the rcfgcall register value needs to be negative. this causes the specified number of clock pulses to be subtracted from the timer counter once every minute. if the oscillator is slower than ideal (positive result from step 2), the rcfgcall register value needs to be positive. this causes the specified number of clock pulses to be added to the timer counter once every minute. 3. load the rtccal register with the correct value. writes to the rtccal register should occur only when the timer is turned off, or immediately after the rising edge of the seconds pulse. 15.3 alarm the alarm features and characteristics are: configurable from half a second to one year enabled using the alrmen bit (alrmcfg<7>, register 15-4) offers one-time and repeat alarm options 15.3.1 configuring the alarm the alarm feature is enabled using the alrmen bit. this bit is cleared when an alarm is issued. the bit will not be cleared if the chime bit = 1 or if alrmrpt ? 0 . the interval selection of the alarm is configured through the alrmcfg bits (amask<3:0>). (see figure 15-5.) these bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. the alarm can also be configured to repeat based on a preconfigured interval. the number of times this occurs, after the alarm is enabled, is stored in the alrmrpt register. alrmptr<1:0> alarm value register window alrmvalh alrmvall 00 alrmmin alrmsec 01 alrmwd alrmhr 10 alrmmnth alrmday 11 equation 15-1: converting error clock pulses (ideal frequency (32,758) C measured frequency) * 60 = error clocks per minute note: in determining the crystals error value, it is the users responsibility to include the crystals initial error from drift due to temperature or crystal aging. note: while the alarm is enabled (alrmen = 1 ), changing any of the registers, other than the rtccal, alrmcfg and alrmrpt registers, and the chime bit, can result in a false alarm event leading to a false alarm interrupt. to avoid this, only change the timer and alarm values while the alarm is disabled (alrmen = 0 ). it is recom- mended that the alrmcfg and alrmrpt registers and chime bit be changed when rtcsync = 0 . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 153 pic18f87j72 family figure 15-5: alarm mask settings when alrmcfg = 00 and the chime bit = 0 (alrmcfg<6>), the repeat function is disabled and only a single alarm will occur. the alarm can be repeated up to 255 times by loading the alrmrpt register with ffh. after each alarm is issued, the alrmrpt register is decremented by one. once the register has reached 00 , the alarm will be issued one last time. after the alarm is issued a last time, the alrmen bit is cleared automatically and the alarm turned off. indefinite repetition of the alarm can occur if the chime bit = 1 . when chime = 1 , the alarm is not disabled when the alrmrpt register reaches 00 , but it rolls over to ff and continues counting indefinitely. note 1: annually, except when configured for february 29. s ss mss mm s s hh mm ss dh h m m s s dd hh mm ss mm d d h h mm s s day of the week month day hours minutes seconds alarm mask setting amask<3:0> 0000 C every half second 0001 C every second 0010 C every 10 seconds 0011 C every minute 0100 C every 10 minutes 0101 C every hour 0110 C every day 0111 C every week 1000 C every month 1001 C every year (1) downloaded from: http:///
pic18f87j72 family ds39979a-page 154 preliminary ? 2010 microchip technology inc. 15.3.2 alarm interrupt at every alarm event, an interrupt is generated. addi- tionally, an alarm pulse output is provided that operates at half the frequency of the alarm. the alarm pulse output is completely synchronous with the rtcc clock and can be used as a trigger clock to other peripherals. this output is available on the rtcc pin. the output pulse is a clock with a 50% duty cycle and a frequency half that of the alarm event (see figure 15-6). the rtcc pin can also output the seconds clock. the user can select between the alarm pulse, generated by the rtcc module, or the seconds clock output. the rtsecsel<1:0> (padcfg1<2:1>) bits select between these two outputs: alarm pulse C rtsecsel<1:0> = 00 seconds clock C rtsecsel<1:0> = 01 figure 15-6: timer pulse generation 15.4 sleep mode the timer and alarm continue to operate while in sleep mode. the operation of the alarm is not affected by sleep as an alarm event can always wake-up the cpu. the idle mode does not affect the operation of the timer or alarm. 15.5 reset 15.5.1 device reset when a device reset occurs, the alcfgrpt register is forced to its reset state, causing the alarm to be disabled (if enabled prior to the reset). if the rtcc was enabled, it will continue to operate when a basic device reset occurs. 15.5.2 power-on reset (por) the rtccfg and alrmrpt registers are reset only on a por. once the device exits the por state, the clock registers should be reloaded with the desired values. the timer prescaler values can be reset only by writing to the seconds register. no device reset can affect the prescalers. rtcen bit alrmen bit rtcc alarm event rtcc pin downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 155 pic18f87j72 family 15.6 register maps table 15-5, table 15-6 and table 15-7 summarize the registers associated with the rtcc module. table 15-5: rtcc control registers file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets on page rtccfg rtcen rtcwren rtcsync halfsec rtcoe rtcptr1 rtcptr0 54 rtccal cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 54 padcfg1 rtsecsel1 rtsecsel0 5 4 alrmcfg alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 54 alrmrpt arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 54 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal for 80-pin devices. table 15-6: rtcc value registers file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets on page rtcvalh rtcc value high register window based on rtcptr<1:0> 54 rtcvall rtcc value low register window based on rtcptr<1:0> 54 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal for 80-pin devices. table 15-7: alarm value registers file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets on page alrmvalh alarm value high register window based on alrmptr<1:0> 54 alrmvall alarm value low register window based on alrmptr<1:0> 54 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal for 80-pin devices. downloaded from: http:///
pic18f87j72 family ds39979a-page 156 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 157 pic18f87j72 family 16.0 capture/compare/pwm (ccp) modules pic18f87j72 family devices have two ccp (capture/compare/pwm) modules, designated ccp1 and ccp2. both modules implement standard capture, compare and pulse-width modulation (pwm) modes. each ccp module contains two 8-bit registers that can operate as two 8-bit capture registers, two 8-bit compare registers or two pwm master/slave duty cycle registers. for the sake of clarity, all ccp module operation in the following sections is described with respect to ccp2, but is equally applicable to ccp1. register 16-1: ccpxcon: ccpx control register (ccp1, ccp2 modules) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5-4 dcxb<1:0>: pwm duty cycle bit 1 and bit 0 for ccpx module capture mode: unused. compare mode : unused. pwm mode: these bits are the two least significant bits (bit 1 and bit 0) of the 10-bit pwm duty cycle. the eight most significant bits (dcx<9:2>) of the duty cycle are found in ccprxl. bit 3-0 ccpxm<3:0> : ccpx module mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0001 = reserved 0010 = compare mode, toggle output on match (ccpxif bit is set) 0011 = reserved 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode: initialize ccpx pin low; on compare match, force ccpx pin high (ccpxif bit is set) 1001 = compare mode: initialize ccpx pin high; on compare match, force ccpx pin lo w (ccpxif bit is set) 1010 = compare mode: generate software interrupt on compare match (ccpxif bit is set, ccpx pin reflects i/o state) 1011 = compare mode: special event trigger; reset timer; start a/d conversion on ccpx match (ccpxif bit is set) (1) 11xx =pwm mode note 1: ccpxm<3:0> = 1011 will only reset the timer and not start an a/d conversion on a ccp1 match. downloaded from: http:///
pic18f87j72 family ds39979a-page 158 preliminary ? 2010 microchip technology inc. 16.1 ccp module configuration each capture/compare/pwm module is associated with a control register (generically, ccpxcon) and a data register (ccprx). the data register, in turn, is comprised of two 8-bit registers: ccprxl (low byte) and ccprxh (high byte). all registers are both readable and writable. 16.1.1 ccp modules and timer resources the ccp modules utilize timers, 1, 2 or 3, depending on the mode selected. timer1 and timer3 are available to modules in capture or compare modes, while timer2 is available for modules in pwm mode. table 16-1: ccp mode C timer resource the assignment of a particular timer to a module is determined by the timer to ccp enable bits in the t3con register (register 14-1). both modules may be active at any given time and may share the same timer resource if they are configured to operate in the same mode (capture/compare or pwm) at the same time. the interactions between the two modules are summarized in table 16-2. depending on the configuration selected, up to four timers may be active at once, with modules in the same configuration (capture/compare or pwm) sharing timer resources. the possible configurations are shown in figure 16-1. 16.1.2 open-drain output option when operating in output mode (i.e., in compare or pwm modes), the drivers for the ccpx pins can be optionally configured as open-drain outputs. this feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. the open-drain output option is controlled by the ccp2od and ccp1od bits (trisg<6:5>). setting the appropriate bit configures the pin for the corresponding module for open-drain operation. 16.1.3 ccp2 pin assignment the pin assignment for ccp2 (capture input, compare and pwm output) can change, based on device config- uration. the ccp2mx configuration bit determines which pin ccp2 is multiplexed to. by default, it is assigned to rc1 (ccp2mx = 1 ). if the configuration bit is cleared, ccp2 is multiplexed with re7. changing the pin assignment of ccp2 does not automatically change any requirements for configuring the port pin. users must always verify that the appropri- ate tris register is configured correctly for ccp2 operation, regardless of where it is located. figure 16-1: ccp and timer interconnect configurations ccp mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 tmr1 tmr2 tmr3 ccp2 ccp1 tmr1 tmr2 tmr3 ccp2 ccp1 tmr1 tmr3 tmr2 ccp2 ccp1 t3ccp<2:1> = 00 t3ccp<2:1> = 01 t3ccp<2:1> = 1x timer1 is used for all capture and compare operations for all ccp modules. timer2 is used for pwm operations for all ccp modules. modules may share either timer resource as a common time base. timer1 is used for capture and compare operations for ccp1 and timer 3 is used for ccp2. both the modules use timer2 as a common time base if they are in pwm modes. timer3 is used for all capture and compare operations for all ccp modules. timer2 is used for pwm operations for all ccp modules. modules may share either timer resource as a common time base. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 159 pic18f87j72 family table 16-2: interactions between ccp1 and ccp2 for timer resources ccp1 mode ccp2 mode interaction capture capture each module can use tmr1 or tmr3 as the time base. the time base can be different for each ccp. capture compare ccp2 can be configured for the special event trigger to reset tmr1 or tmr3 (depending upon which time base is used). automatic a/d conversions on trigger event can also be done. operation of ccp1 could be affected if it is using the same timer as a time base. compare capture ccp1 can be configured for the special event trigger to reset tmr1 or tmr3 (depending upon which time base is used). operation of ccp2 could be affected if it is using the same timer as a time base. compare compare either module can be configured for the special event trigger to reset the time base. automatic a/d conversions on ccp2 trigger event can be done. conflicts may occur if both modules are using the same time base. capture pwm none compare pwm none pwm capture none pwm compare none pwm pwm both pwms will have the same frequency and update rate (tmr2 interrupt). downloaded from: http:///
pic18f87j72 family ds39979a-page 160 preliminary ? 2010 microchip technology inc. 16.2 capture mode in capture mode, the ccpr2h:ccpr2l register pair captures the 16-bit value of the tmr1 or tmr3 register when an event occurs on the ccp2 pin (rc1 or re7, depending on device configuration). an event is defined as one of the following: every falling edge every rising edge every 4th rising edge every 16th rising edge the event is selected by the mode select bits, ccp2m<3:0> (ccp2con<3:0>). when a capture is made, the interrupt request flag bit, ccp2if (pir3<2>), is set; it must be cleared in software. if another capture occurs before the value in register, ccpr2, is read, the old captured value is overwritten by the new captured value. 16.2.1 ccp pin configuration in capture mode, the appropriate ccpx pin should be configured as an input by setting the corresponding tris direction bit. 16.2.2 timer1/timer3 mode selection the timers that are to be used with the capture feature (timer1 and/or timer3) must be running in timer mode or synchronized counter mode. in asynchronous counter mode, the capture operation may not work. the timer to be used with each ccp module is selected in the t3con register (see section 16.1.1 ccp modules and timer resources ). 16.2.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccp2ie bit (pie3<2>) clear to avoid false interrupts and should clear the flag bit, ccp2if, following any such change in operating mode. 16.2.4 ccp prescaler there are four prescaler settings in capture mode. they are specified as part of the operating mode selected by the mode select bits (ccp2m<3:0>). whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. example 16-1 shows the recommended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the false interrupt. example 16-1: changing between capture prescalers figure 16-2: capture mode operation block diagram note: if rc1/ccp2 or re7/ccp2 is configured as an output, a write to the port can cause a capture condition. clrf ccp2con ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp2con ; load ccp2con with ; this value ccpr1h ccpr1l tmr1h tmr1l set ccp1if tmr3 enable q1:q4 ccp1con<3:0> ccp1 pin prescaler ? 1, 4, 16 and edge detect tmr1 enable t3ccp2 t3ccp2 ccpr2h ccpr2l tmr1h tmr1l set ccp2if tmr3 enable ccp2con<3:0> ccp2 pin prescaler ? 1, 4, 16 tmr3h tmr3l tmr1 enable t3ccp2 t3ccp1 t3ccp2 t3ccp1 tmr3h tmr3l and edge detect 4 4 4 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 161 pic18f87j72 family 16.3 compare mode in compare mode, the 16-bit ccpr2 register value is constantly compared against either the tmr1 or tmr3 register pair value. when a match occurs, the ccp2 pin can be: driven high driven low toggled (high-to-low or low-to-high) remain unchanged (that is, reflects the state of the i/o latch) the action on the pin is based on the value of the mode select bits (ccp2m<3:0>). at the same time, the interrupt flag bit, ccp2if, is set. 16.3.1 ccp pin configuration the user must configure the ccpx pin as an output by clearing the appropriate tris bit. 16.3.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode, or synchronized counter mode, if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 16.3.3 software interrupt mode when the generate software interrupt mode is chosen (ccp2m<3:0> = 1010 ), the ccp2 pin is not affected. only a ccp interrupt is generated, if enabled, and the ccp2ie bit is set. 16.3.4 special event trigger both ccp modules are equipped with a special event trigger. this is an internal hardware signal generated in compare mode to trigger actions by other modules. the special event trigger is enabled by selecting the compare special event trigger mode (ccp2m<3:0> = 1011 ). for either ccp module, the special event trigger resets the timer register pair for whichever timer resource is currently assigned as the modules time base. this allows the ccprx registers to serve as a programmable period register for either timer. the special event trigger for ccp2 can also start an a/d conversion. in order to do this, the a/d converter must already be enabled. figure 16-3: compare mode operation block diagram note: clearing the ccp2con register will force the rc1 or re7 compare output latch (depending on device configuration) to the default low level. this is not the portc or porte i/o data latch. note: the special event trigger of ccp1 only resets timer1/timer3 and cannot start an a/d conversion even when the a/d converter is enabled. ccpr1h ccpr1l tmr1h tmr1l comparator q s r output logic special event trigger set ccp1if ccp1 pin tris ccp1con<3:0> output enable tmr3h tmr3l ccpr2h ccpr2l comparator 1 0 t3ccp2 t3ccp1 set ccp2if 1 0 compare 4 (timer1 reset) q s r output logic special event trigger ccp2 pin tris ccp2con<3:0> output enable 4 (timer1/timer3 reset, a/d trigger) match compare match downloaded from: http:///
pic18f87j72 family ds39979a-page 162 preliminary ? 2010 microchip technology inc. table 16-3: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 rcon ipen cm ri to pd por bor 50 pir3 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif 52 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie 52 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip 52 pir2 oscfif cmif bclif lvdif tmr3if 5 2 pie2 oscfie cmie bclie lvdie tmr3ie 5 2 ipr2 oscfip cmip bclip lvdip tmr3ip 5 2 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 52 trise trise7 trise6 trise5 trise4 trise3 trise1 trise0 52 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 52 tmr1l timer1 register low byte 50 tmr1h timer1 register high byte 50 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 50 tmr3h timer3 register high byte 51 tmr3l timer3 register low byte 51 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 51 ccpr1l capture/compare/pwm register 1 low byte 53 ccpr1h capture/compare/pwm register 1 high byte 53 ccp1con dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 53 ccpr2l capture/compare/pwm register 2 low byte 53 ccpr2h capture/compare/pwm register 2 high byte 53 ccp2con dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 53 legend: = unimplemented, read as 0 . shaded cells are not used by capture/compare, timer1 or timer3. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 163 pic18f87j72 family 16.4 pwm mode in pulse-width modulation (pwm) mode, the ccp2 pin produces up to a 10-bit resolution pwm output. since the ccp2 pin is multiplexed with a portc or porte data latch, the appropriate tris bit must be cleared to make the ccp2 pin an output. figure 16-4 shows a simplified block diagram of the ccp1 module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 16.4.3 setup for pwm operation . figure 16-4: simplified pwm block diagram a pwm output (figure 16-5) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 16-5: pwm output 16.4.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following formula: equation 16-1: pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp2 pin is set (exception: if pwm duty cycle = 0%, the ccp2 pin will not be set) the pwm duty cycle is latched from ccpr2l into ccpr2h note: clearing the ccp2con register will force the rc1 or re7 output latch (depending on device configuration) to the default low level. this is not the portc or porte i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: the 8-bit tmr2 value is concatenated with the 2-bit internal q clock, or 2 bits of the prescaler, to create the 10-bit time base. note: the timer2 postscalers (see section 13.0 timer2 module ) are not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 pwm period = (pr2) + 1] 4 t osc (tmr2 prescale value) downloaded from: http:///
pic18f87j72 family ds39979a-page 164 preliminary ? 2010 microchip technology inc. 16.4.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr2l register and to the ccp2con<5:4> bits. up to 10-bit resolution is available. the ccpr2l contains the eight msbs and the ccp2con<5:4> bits contain the two lsbs. this 10-bit value is represented by ccpr2l:ccp2con<5:4>. the following equation is used to calculate the pwm duty cycle in time: equation 16-2: ccpr2l and ccp2con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr2h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr2h is a read-only register. the ccpr2h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm operation. when the ccpr2h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp2 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: equation 16-3: table 16-4: example pwm frequencies and resolutions at 40 mhz pwm duty cycle = (ccpr2l:ccp2con<5:4>) t osc (tmr2 prescale value) note: if the pwm duty cycle value is longer than the pwm period, the ccp2 pin will not be cleared. f osc f pwm --------------- ?? ?? log 2 ?? log ----------------------------- b i t s = pwm resolution (max) pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz t i m e r p r e s c a l e r ( 1 , 4 , 1 6 )1 641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 14 12 10 8 7 6.58 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 165 pic18f87j72 family 16.4.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr2l register and ccp2con<5:4> bits. 3. make the ccp2 pin an output by clearing the appropriate tris bit. 4. set the tmr2 prescale value, then enable timer2 by writing to t2con. 5. configure the ccp2 module for pwm operation. table 16-5: registers associated with pwm and timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 rcon ipen cm ri to pd por bor 50 pir1 adif rc1if tx1if sspif t m r 2 i f tmr1if 52 pie1 adie rc1ie tx1ie sspie t m r 2 i e tmr1ie 52 ipr1 adip rc1ip tx1ip sspip t m r 2 i p tmr1ip 52 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 52 trise trise7 trise6 trise5 trise4 trise3 trise1 trise0 52 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 52 tmr2 timer2 register 50 pr2 timer2 period register 50 t2con t2outps3 t2outps2 t2outps1 t2o utps0 tmr2on t2ckps1 t2ckps0 50 ccpr1l capture/compare/pwm register 1 low byte 53 ccpr1h capture/compare/pwm register 1 high byte 53 ccp1con dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 53 ccpr2l capture/compare/pwm register 2 low byte 53 ccpr2h capture/compare/pwm register 2 high byte 53 ccp2con dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 53 legend: = unimplemented, read as 0 . shaded cells are not used by pwm or timer2. downloaded from: http:///
pic18f87j72 family ds39979a-page 166 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 167 pic18f87j72 family 17.0 liquid crystal display (lcd) driver module the liquid crystal display (lcd) driver module generates the timing control to drive a static or multiplexed lcd panel. it also provides control of the lcd pixel data. the module can drive panels of up to 132 pixels (33 segments by 4 commons). the lcd driver module supports these features: direct driving of lcd panel on-chip bias generator with dedicated charge pump to support a range of fixed and variable bias options up to four commons, with four multiplexing modes up to 33 segments three lcd clock sources with selectable prescaler, with a fourth source available for use with the lcd charge pump a simplified block diagram of the module is shown in figure 17-1. figure 17-1: lcd driver module block diagram com<3:0> timing control data bus intrc oscillator f osc /4 t13cki 132 to 33 mux seg<32:0> to i/o pins 20 x 8 (= 4 x 40) lcd data lcdcon lcdps lcdsex lcddata0 lcddata1 lcddata21 lcddata22 .. . lcd bias generation lcd clock source select lcd charge pump 33 4 bias voltage 8 intosc oscillator downloaded from: http:///
pic18f87j72 family ds39979a-page 168 preliminary ? 2010 microchip technology inc. 17.1 lcd registers the lcd driver module has 33 registers: lcd control register (lcdcon) lcd phase register (lcdps) lcdreg register (lcd regulator control) five lcd segment enable registers (lcdse4:lcdse0) 20 lcd data registers (lcddatax, for x from 0 to 22, with 5, 11 and 17 not implemented) 17.1.1 lcd control registers the lcdcon register, shown in register 17-1, controls the overall operation of the module. once the module is configured, the lcden (lcdcon<7>) bit is used to enable or disable the lcd module. the lcd panel can also operate during sleep by clearing the slpen (lcdcon<6>) bit. the lcdps register, shown in register 17-2, configures the lcd clock source prescaler and the type of waveform: type-a or type-b. details on these features are provided in section 17.2 lcd clock source , section 17.3 lcd bias generation and section 17.8 lcd waveform generation . the lcdreg register is described in section 17.3 lcd bias generation . the lcd segment enable registers (lcdsex) configure the functions of the port pins. setting the segment enable bit for a particular segment configures that pin as an lcd driver. the prototype lcdse register is shown in register 17-3. there are five lcdse registers (lcdse4:lcdse0), listed in table 17-1. register 17-1: lcdcon: lcd control register r/w-0 r/w-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 lcden slpen werr cs1 cs0 lmux1 lmux0 bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 lcden: lcd driver enable bit 1 = lcd driver module is enabled 0 = lcd driver module is disabled bit 6 slpen: lcd driver enable in sleep mode bit 1 = lcd driver module is disabled in sleep mode 0 = lcd driver module is enabled in sleep mode bit 5 werr: lcd write failed error bit 1 = lcddatax register written while lcdps<4> = 0 (must be cleared in software) 0 = no lcd write error bit 4 unimplemented: read as 0 bit 3-2 cs<1:0>: clock source select bits 1x = intrc (31 khz) 01 = t13cki (timer1) 00 = system clock (f osc /4) bit 1-0 lmux<1:0>: commons select bits lmux<1:0> multiplex type maximum number of pixels bias type 00 static (com0) 33 static 01 1/2 (com1:com0) 66 1/2 or 1/3 10 1/3 (com2:com0) 99 1/2 or 1/3 11 1/4 (com3:com0) 132 1/3 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 169 pic18f87j72 family register 17-2: lcdps: lcd phase register r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 wft biasmd lcda wa lp3 lp2 lp1 lp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 wft: waveform type select bit 1 = type-b waveform (phase changes on each frame boundary) 0 = type-a waveform (phase changes within each common type) bit 6 biasmd: bias mode select bit when lmux<1:0> = 00 : 0 = static bias mode (do not set this bit to 1 ) when lmux<1:0> = 01 or 10 : 1 = 1/2 bias mode 0 = 1/3 bias mode when lmux<1:0> = 11 : 0 = 1/3 bias mode (do not set this bit to 1 ) bit 5 lcda: lcd active status bit 1 = lcd driver module is active 0 = lcd driver module is inactive bit 4 wa: lcd write allow status bit 1 = write into the lcddatax registers is allowed 0 = write into the lcddatax registers is not allowed bit 3-0 lp<3:0>: lcd prescaler select bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1 downloaded from: http:///
pic18f87j72 family ds39979a-page 170 preliminary ? 2010 microchip technology inc. table 17-1: lcdse registers and associated segments register 17-3: lcdsex: lcd segment enable registers r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 se(n + 7) se(n + 6) se(n + 5) se(n + 4) se(n + 3) se(n + 2) se(n + 1) se(n) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 seg(n + 7):seg(n): segment enable bits for lcdse0: n = 0 for lcdse1: n = 8 for lcdse2: n = 16 for lcdse3: n = 24 for lcdse4: n = 32 1 = segment function of the pin is enabled; digital i/o disabled 0 = i/o function of the pin is enabled register segments lcdse0 7:0 lcdse1 15:8 lcdse2 23:16 lcdse3 31:24 lcdse4 (1) 32 note 1: only lcdse4<0> (seg32) is implemented. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 171 pic18f87j72 family 17.1.2 lcd data registers once the module is initialized for the lcd panel, the individual bits of the lcddata registers are cleared or set to represent a clear or dark pixel, respectively. specific sets of lcddata registers are used with specific segments and common signals. each bit represents a unique combination of a specific segment connected to a specific common. individual lcddata bits are named by the convention sxxcy, with xx as the segment number and y as the common number. the relationship is summarized in table 17-2. the prototype lcddata register is shown in register 17-4. table 17-2: lcddata registers and bits for segment and com combinations note: lcddata5, lcddata11 and lcddata17 are not implemented. register 17-4: lcddatax: lcd data registers (1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 s(n + 7)cy s(n + 6)cy s(n + 5)cy s(n + 4)cy s(n + 3)cy s(n + 2)cy s(n + 1)cy s(n)cy bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 s(n + 7)cy:s(n)cy: pixel on bits for lcddata0 through lcddata5: n = (8x), y = 0 (1) for lcddata6 through lcddata10: n = (8(x C 6)), y = 1 for lcddata12 through lcddata16: n = (8(x C 12)), y = 2 (1) for lcddata18 through lcddata22: n = (8(x C 18)), y = 3 (1) 1 = pixel on (dark) 0 = pixel off (clear) note 1: lcddata5, lcddata11 and lcddata17 are not implemented. segments com lines 0123 0 through 7 lcddata0 lcddata6 lcddata12 lcddata18 s00c0:s07c0 s00c1:s07c1 s00c2:s07c2 s00c3:s07c3 8 through 15 lcddata1 lcddata7 lcddata13 lcddata19 s08c0:s15c0 s08c1:s15c1 s08c2:s15c2 s08c0:s15c3 16 through 23 lcddata2 lcddata8 lcddata14 lcddata20 s16c0:s23c0 s16c1:s23c1 s16c2:s23c2 s16c3:s23c3 24 through 31 lcddata3 lcddata9 lcddata15 lcddata21 s24c0:s31c0 s24c1:s31c1 s24c2:s31c2 s24c3:s31c3 32 lcddata4 (1) lcddata10 (1) lcddata16 (1) lcddata22 (1) s32c0 s32c1 s32c2 s32c3 note 1: only bit<0> of these registers is implemented. downloaded from: http:///
pic18f87j72 family ds39979a-page 172 preliminary ? 2010 microchip technology inc. 17.2 lcd clock source the lcd driver module generates its internal clock from 3 possible sources: system clock (f osc /4) timer1 oscillator intrc source the lcd clock generator uses a configurable divide-by-32/divide-by-8192 postscaler to produce a baseline frequency of about 1 khz nominal, regardless of the source selected. the clock source selection and the postscaler configuration are determined by the clock source select bits, cs<1:0> (lcdcon<3:2>). an additional programmable prescaler is used to derive the lcd frame frequency from the 1 khz baseline. the prescaler is configured using the lp<3:0> bits (lcdps<3:0>) for any one of 16 options, ranging from 1:1 to 1:16. proper timing for waveform generation is set by the lmux<1:0> bits (lcdcon<1:0>). these bits determine which commons multiplexing mode is to be used, and divide down the lcd clock source as required. they also determine the configuration of the ring counter that is used to switch the lcd commons on or off. 17.2.1 lcd voltage regulator clock source in addition to the clock source for lcd timing, a separate 31 khz nominal clock is required for the lcd charge pump. this is provided from a distinct branch of the lcd clock source. the charge pump clock can use either the timer1 oscillator or the intrc source, as well as the 8 mhz intosc source (after being divided by 256 by a prescaler). the charge pump clock source is configured using the cksel<1:0> bits (lcdreg<1:0>). 17.2.2 clock source considerations when using the system clock as the lcd clock source, it is assumed that the system clock frequency is a nom- inal 32 mhz (for a f osc /4 frequency of 8 mhz). because the prescaler option for the f osc /4 clock selection is fixed at divide-by-8192, system clock speeds that differ from 32 mhz will produce frame frequencies and refresh rates different than discussed in this chapter. the user will need to keep this in mind when designing the display application. the timer1 and intrc sources can be used as lcd clock sources when the device is in sleep mode. to use the timer1 oscillator, it is necessary to set the t1oscen bit (t1con<3>). selecting either timer1 or intrc as the lcd clock source will not automatically activate these sources. similarly, selecting the intosc as the charge pump clock source will not turn the oscillator on. to use intosc, it must be selected as the system clock source by using the fosc2 configuration bit. if timer1 is used as a clock source for the device, either as an lcd clock source or for any other purpose, lcd segment 32 becomes unavailable. figure 17-2: lcd clock generation lcdcon<3:2> timer1 oscillator internal 31 khz source 4 programmable 1, 2, 3, 4 ring counter com0 com1 com2 com3 2 32 lcdcon<1:0> lcdps<3:0> system clock (f osc /4) intosc 8 mhz source 1:1 to 1:16 prescaler 1x 01 00 11 10 01 00 31 khz clock 1110 01 lcdreg<1:0> to lcd charge pump 8192 or 4 2 2 2 256 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 173 pic18f87j72 family 17.3 lcd bias generation the lcd driver module is capable of generating the required bias voltages for lcd operation with a mini- mum of external components. this includes the ability to generate the different voltage levels required by the different bias types required by the lcd. the driver module can also provide bias voltages both above and below microcontroller v dd through the use of an on-chip lcd voltage regulator. 17.3.1 lcd bias types pic18f87j72 family devices support three bias types based on the waveforms generated to control segments and commons: static (two discrete levels) 1/2 bias (three discrete levels 1/3 bias (four discrete levels) the use of different waveforms in driving the lcd is dis- cussed in more detail in section 17.8 lcd waveform generation . 17.3.2 lcd voltage regulator the purpose of the lcd regulator is to provide proper bias voltage and good contrast for the lcd, regardless of v dd levels. this module contains a charge pump and internal voltage reference. the regulator can be config- ured by using external components to boost bias voltage above v dd . it can also operate a display at a constant voltage below v dd . the regulator can also be selectively disabled to allow bias voltages to be generated by an external resistor network. the lcd regulator is controlled through the lcdreg register (register 17-5). it is enabled or disabled using the cksel<1:0> bits, while the charge pump can be selectively enabled using the cpen bit. when the reg- ulator is enabled, the mode13 bit is used to select the bias type. the peak lcd bias voltage, measured as a difference between the potentials of lcdbias3 and lcdbias0, is configured with the bias bits. register 17-5: lcdreg: voltag e regulator control register u - 0 r w - 0r w - 1r w - 1r w - 1r w - 1r w - 0r w - 0 cpen bias2 bias1 bias0 mode13 cksel1 cksel0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 unimplemented: read as 0 bit 6 cpen: lcd charge pump enable bit 1 = charge pump enabled; highest lcd bias voltage is 3.6v 0 = charge pump disabled; highest lcd bias voltage is av dd bit 5-3 bias<2:0>: regulator voltage output control bits 111 = 3.60v peak (offset on lcdbias0 of 0v) 110 = 3.47v peak (offset on lcdbias0 of 0.13v) 101 = 3.34v peak (offset on lcdbias0 of 0.26v) 100 = 3.21v peak (offset on lcdbias0 of 0.39v) 011 = 3.08v peak (offset on lcdbias0 of 0.52v) 010 = 2.95v peak (offset on lcdbias0 of 0.65v) 001 = 2.82v peak (offset on lcdbias0 of 0.78v) 000 = 2.69v peak (offset on lcdbias0 of 0.91v) bit 2 mode13: 1/3 lcd bias enable bit 1 = regulator output supports 1/3 lcd bias mode 0 = regulator output supports static lcd bias mode bit 1-0 cksel<1:0>: regulator clock source select bits 11 = intrc 10 = intosc 8 mhz source 01 = timer1 oscillator 00 = lcd regulator disabled downloaded from: http:///
pic18f87j72 family ds39979a-page 174 preliminary ? 2010 microchip technology inc. 17.3.3 bias configurations pic18f87j72 family devices have four distinct circuit configurations for lcd bias generation: m0: regulator with boost m1: regulator without boost m2: resistor ladder with software contrast m3: resistor ladder with hardware contrast 17.3.3.1 m0 (regulator with boost) in m0 operation, the lcd charge pump feature is enabled. this allows the regulator to generate voltages up to +3.6v to the lcd (as measured at lcdbias3). m0 uses a flyback capacitor connected between v lcap 1 and v lcap 2, as well as filter capacitors on lcdbias0 through lcdbias3, to obtain the required voltage boost (figure 17-3). the output voltage (v bias ) is the difference of potential between lcdbias3 and lcdbias0. it is set by the bias<2:0> bits which adjust the offset between lcdbias0 and v ss . the flyback capacitor (c fly ) acts as a charge storage element for large lcd loads. this mode is useful in those cases where the voltage requirements of the lcd are higher than the microcontrollers v dd . it also permits software control of the displays contrast by adjustment of bias voltage by changing the value of the bias bits. m0 supports static and 1/3 bias types. generation of the voltage levels for 1/3 bias is handled automatically, but must be configured in software. m0 is enabled by selecting a valid regulator clock source (cksel<1:0> set to any value except 00 ) and setting the cpen bit. if static bias type is required, the mode13 bit must be cleared. 17.3.3.2 m1 (regulator without boost) m1 operation is similar to m0, but does not use the lcd charge pump. it can provide v bias up to the voltage level supplied directly to lcdbias3. it can be used in cases where v dd for the application is expected to never drop below a level that can provide adequate contrast for the lcd. the connection of external com- ponents is very similar to m0, except that lcdbias3 must be tied directly to v dd (figure 17-3). the bias<2:0> bits can still be used to adjust contrast in software by changing v bias . as with m0, changing these bits changes the offset between lcdbias0 and v ss . in m1, this is reflected in the change between the lcdbias0 and the voltage tied to lcdbias3. thus, if v dd should change, v bias will also change; where in m0, the level of v bias is constant. like m0, m1 supports static and 1/3 bias types. generation of the voltage levels for 1/3 bias is handled automatically but must be configured in software. m1 is enabled by selecting a valid regulator clock source (cksel<1:0> set to any value except 00 ) and clearing the cpen bit. if 1/3 bias type is required, the mode13 bit should also be set. figure 17-3: lcd regulator connectio ns for m0 and m1 configurations note: when the device enters sleep mode while operating in bias modes, m0 or m1, be sure that the bias capacitors are fully dis- charged in order to get the lowest sleep current. lcdbias3 lcdbias2 lcdbias1 lcdbias0 av dd v dd v lcap 1 v lcap 2 c fly c0 c1 c2 c3 c0 c1 c2 v dd v dd (v bias up to 3.6v) mode 0 (v bias ? v dd ) mode 1 c fly note 1: these values are provided for design guidance only. they should be optimized f or the application by the designer based on the actual lcd specifications. 0.47 f (1) 0.47 f (1) 0.47 f (1) 0.47 f (1) 0.47 f (1) 0.47 f (1) 0.47 f (1) 0.47 f (1) 0.47 f (1) pic18f87j72 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 175 pic18f87j72 family 17.3.3.3 m2 (resistor ladder with software contrast) m2 operation also uses the lcd regulator but disables the charge pump. the regulators internal voltage refer- ence remains active as a way to regulate contrast. it is used in cases where the current requirements of the lcd exceed the capacity of the regulators charge pump. in this configuration, the lcd bias voltage levels are created by an external resistor voltage divider connected across lcdbias0 through lcdbias3, with the top of the divider tied to v dd (figure 17-4). the potential at the bottom of the ladder is determined by the lcd regulators voltage reference, tied internally to lcdbias0. the bias type is determined by the volt- ages on the lcdbias pins, which are controlled by the configuration of the resistor ladder. most applications using m2 will use a 1/3 or 1/2 bias type. while static bias can also be used, it offers extremely limited contrast range and additional current consumption over other bias generation modes. like m1, the lcdbias bits can be used to control con- trast, limited by the level of v dd supplied to the device. also, since there is no capacitor required across v lcap 1 and v lcap 2, these pins are available as digital i/o ports, rg2 and rg3. m2 is selected by clearing the cksel<1:0> bits and setting the cpen bit. figure 17-4: resistor ladder conne ctions for m2 configuration lcdbias3 note 1: these values are provided for design guidance only; they should be optimized for the application by the designer based on the actual lcd specifications. bias level at pin bias type 1/2 bias 1/3 bias lcdbias0 (internal low reference voltage) (internal low reference voltage) lcdbias1 1/2 v bias 1/3 v bias lcdbias2 1/2 v bias 2/3 v bias lcdbias3 v bias (up to av dd )v bias (up to av dd ) 10 k ? (1) 10 k ? (1) 1/2 bias 1/3 bias lcdbias2 lcdbias1 lcdbias0 av dd 10 k ? (1) 10 k ? (1) 10 k ? (1) v dd pic18f87j72 downloaded from: http:///
pic18f87j72 family ds39979a-page 176 preliminary ? 2010 microchip technology inc. 17.3.3.4 m3 (hardware contrast) in m3, the lcd regulator is completely disabled. like m2, lcd bias levels are tied to av dd , and are generated using an external divider. the difference is that the inter- nal voltage reference is also disabled and the bottom of the ladder is tied to ground (v ss ); see figure 17-5. the value of the resistors, and the difference between v ss and v dd , determine the contrast range; no software adjustment is possible. this configuration is also used where the lcds current requirements exceed the capacity of the charge pump and software contrast control is not needed. depending on the bias type required, resistors are connected between some or all of the pins. a potentio- meter can also be connected between lcdbias3 and v dd to allow for hardware controlled contrast adjustment. m3 is selected by clearing the cksel<1:0> and cpen bits. figure 17-5: resistor ladder co nnections for m3 configuration lcdbias3 note 1: these values are provided for design guidance only; th ey should be optimized for the application by the designer based on the actual lcd specifications. 2: potentiometer for manual contrast adjustment is optional; it may be omitted entirely. bias level at pin bias type static 1/2 bias 1/3 bias lcdbias0 av ss av ss av ss lcdbias1 av ss 1/2 av dd 1/3 av dd lcdbias2 av dd 1/2 av dd 2/3 av dd lcdbias3 av dd av dd av dd 10 k ? (1) 10 k ? (1) static bias 1/2 bias 1/3 bias lcdbias2 lcdbias1 lcdbias0 av dd 10 k ? (1) 10 k ? (1) 10 k ? (1) v dd (2) pic18f87j72 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 177 pic18f87j72 family 17.3.4 design cons iderations for the lcd charge pump when designing applications that use the lcd regula- tor with the charge pump enabled, users must always consider both the dynamic current and rms (static) current requirements of the display, and what the charge pump can deliver. both dynamic and static current can be determined by equation 17-1: equation 17-1: for dynamic current, c is the value of the capacitors attached to lcdbias3 and lcdbias2. the variable, dv , is the voltage drop allowed on c2 and c3 during a voltage switch on the lcd display, and dt is the dura- tion of the transient current after a clock pulse occurs. for practical design purposes, these will be assumed to be 0.047 ? f for c , 0.1v for dv and 1 ? s for dt . this yields a dynamic current of 4.7 ma for 1 ? s. rms current is determined by the value of c fly for c , the voltage across v lcap 1 and v lcap 2 for dv and the regulator clock period (t per ) for dt . assuming c fly of 0.047 ? f, a value of 1.02v across c fly and t per of 30 ? s, the maximum theoretical static current will be 1.8 ma. since the charge pump must charge five capacitors, the maximum current becomes 360 ? a. for a real-world assumption of 50% efficiency, this yields a practical current of 180 ? a. users should compare the calculated current capacity against the requirements of the lcd. while dv and dt are relatively fixed by device design, the values of c fly and the capacitors on the lcdbias pins can be changed to increase or decrease current. as always, any changes should be evaluated in the actual circuit for its impact on the application. 17.4 lcd multiplex types the lcd driver module can be configured into four multiplex types: static (only com0 used) 1/2 multiplex (com0 and com1 are used) 1/3 multiplex (com0, com1 and com2 are used) 1/4 multiplex (all com0, com1, com2 and com3 are used) the number of active commons used is configured by the lmux<1:0> bits (lcdcon<1:0>), which deter- mines the function of the porte<6:4> pins (see table 17-3 for details). if the pin is configured as a com drive, the port i/o function is disabled and the tris setting of that pin is overridden. table 17-3: porte<6:4> function 17.5 segment enables the lcdsex registers are used to select the pin function for each segment pin. setting a bit configures the corresponding pin to function as a segment driver. lcdsex registers do not override the tris bit settings, so the tris bits must be configured as input for that pin. 17.6 pixel control the lcddatax registers contain bits which define the state of each pixel. each bit defines one unique pixel. table 17-2 shows the correlation of each bit in the lcddatax registers to the respective common and segment signals. any lcd pixel location not being used for display can be used as general purpose ram. i = c x dvdt note: on a power-on reset, the lmux<1:0> bits are 00 . lmux<1:0> porte<6> porte<5> porte<4> 00 digital i/o digital i/o digital i/o 01 digital i/o digital i/o com1 driver 10 digital i/o com2 driver com1 driver 11 com3 driver com2 driver com1 driver note: on a power-on reset, these pins are configured as digital i/o. downloaded from: http:///
pic18f87j72 family ds39979a-page 178 preliminary ? 2010 microchip technology inc. 17.7 lcd frame frequency the rate at which the com and seg outputs change is called the lcd frame frequency. frame frequency is set by the lp<3:0> bits (lcdps<3:0>) and is also affected by the multiplex mode being used. the rela- tionship between the multiplex mode, lp bits setting and frame rate is shown in table 17-4 and table 17-5. table 17-4: frame frequency formulas table 17-5: approximate frame frequency (in hz) for lp prescaler settings 17.8 lcd waveform generation lcd waveform generation is based on the principle that the net ac voltage across the dark pixel should be maximized and the net ac voltage across the clear pixel should be minimized. the net dc voltage across any pixel should be zero. the com signal represents the time slice for each common, while the seg contains the pixel data. the pixel signal (com-seg) will have no dc component and it can take only one of the two rms values. the higher rms value will create a dark pixel and a lower rms value will create a clear pixel. as the number of commons increases, the delta between the two rms values decreases. the delta represents the maximum contrast that the display can have. the lcds can be driven by two types of waveform: type-a and type-b. in the type-a waveform, the phase changes within each common type, whereas in the type-b waveform, the phase changes on each frame boundary. thus, the type-a waveform maintains 0 v dc over a single frame, whereas the type-b waveform takes two frames. figure 17-6 through figure 17-16 provide waveforms for static, half multiplex, one-third multiplex and quarter multiplex drives for type-a and type-b waveforms. multiplex mode frame frequency (hz) static clock source/(4 x 1 x (lp<3:0> + 1)) 1/2 clock source/(2 x 2 x (lp<3:0> + 1)) 1/3 clock source/(1 x 3 x (lp<3:0> + 1)) 1/4 clock source/(1 x 4 x (lp<3:0> + 1)) lp<3:0> multiplex mode static 1/2 1/3 1/4 1 125 125 167 125 2 83 83 111 83 3 6 26 28 36 2 4 5 05 06 75 0 5 4 24 25 64 2 6 3 63 64 83 6 7 3 13 14 23 1 note 1: if the power-managed sleep mode is invoked while the lcd sleep bit is set (lcdcon<6> is 1 ), take care to execute sleep only when the v dc on all the pixels is 0 . 2: when the lcd clock source is the system clock, the lcd module will go to sleep if the microcontroller goes into sleep mode, regardless of the setting of the splen bit. thus, always take care to see that the v dc on all pixels is 0 whenever sleep mode is invoked. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 179 pic18f87j72 family figure 17-6: type-a/type-b waveforms in static drive v 1 v 0 com0 seg0 com0-seg0 com0-seg1 seg1 v 1 v 0 v 1 v 0 v 0 v 1 -v 1 v 0 1 frame com0 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 downloaded from: http:///
pic18f87j72 family ds39979a-page 180 preliminary ? 2010 microchip technology inc. figure 17-7: type-a waveforms in 1/2 mux, 1/2 bias drive v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 -v 2 -v 1 v 2 v 1 v 0 -v 2 -v 1 com0com1 seg0 seg1 com0-seg0 com0-seg1 1 frame com1 com0 seg0 seg1 seg2 seg3 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 181 pic18f87j72 family figure 17-8: type-b waveforms in 1/2 mux, 1/2 bias drive v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 -v 2 -v 1 v 2 v 1 v 0 -v 2 -v 1 com0com1 seg0 seg1 com0-seg0 com0-seg1 com1 com0 seg0 seg1 seg2 seg3 2 frames downloaded from: http:///
pic18f87j72 family ds39979a-page 182 preliminary ? 2010 microchip technology inc. figure 17-9: type-a waveforms in 1/2 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0com1 seg0 seg1 com0-seg0 com0-seg1 1 frame com1 com0 seg0 seg1 seg2 seg3 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 183 pic18f87j72 family figure 17-10: type-b waveforms in 1/2 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0 com1 seg0 seg1 com0-seg0 com0-seg1 com1 com0 seg0 seg1 seg2 seg3 2 frames downloaded from: http:///
pic18f87j72 family ds39979a-page 184 preliminary ? 2010 microchip technology inc. figure 17-11: type-a waveforms in 1/3 mux, 1/2 bias drive v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 -v 2 -v 1 v 2 v 1 v 0 -v 2 -v 1 com0com1 com2 seg0 seg1 com0-seg0 com0-seg1 1 frame com2com1 com0 seg0 seg1 seg2 seg2 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 185 pic18f87j72 family figure 17-12: type-b waveforms in 1/3 mux, 1/2 bias drive v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 -v 2 -v 1 v 2 v 1 v 0 -v 2 -v 1 com0com1 com2 seg0 seg1 com0-seg0 com0-seg1 2 frames com2com1 com0 seg0 seg1 seg2 downloaded from: http:///
pic18f87j72 family ds39979a-page 186 preliminary ? 2010 microchip technology inc. figure 17-13: type-a waveforms in 1/3 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0com1 com2 seg0 seg1 com0-seg0 com0-seg1 1 frame com2com1 com0 seg0 seg1 seg2 seg2 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 187 pic18f87j72 family figure 17-14: type-b waveforms in 1/3 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0 com1 com2 seg0 seg1 com0-seg0 com0-seg1 2 frames com2 com1 com0 seg0 seg1 seg2 downloaded from: http:///
pic18f87j72 family ds39979a-page 188 preliminary ? 2010 microchip technology inc. figure 17-15: type-a waveforms in 1/4 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0com1 com2 com3 seg0 seg1 com0-seg0 com0-seg1 com3com2 com1 com0 1 frame seg0 seg1 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 189 pic18f87j72 family figure 17-16: type-b waveforms in 1/4 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0com1 com2 com3 seg0 seg1 com0-seg0 com0-seg1 com3com2 com1 com0 2 frames seg0 seg1 downloaded from: http:///
pic18f87j72 family ds39979a-page 190 preliminary ? 2010 microchip technology inc. 17.9 lcd interrupts the lcd timing generation provides an interrupt that defines the lcd frame timing. this interrupt can be used to coordinate the writing of the pixel data with the start of a new frame. writing pixel data at the frame boundary allows a visually crisp transition of the image. this interrupt can also be used to synchronize external events to the lcd. for example, the interface to an external segment driver can be synchronized for segment data update to the lcd frame. a new frame is defined to begin at the leading edge of the com0 common signal. the interrupt will be set immediately after the lcd controller completes accessing all pixel data required for a frame. this will occur at a fixed interval before the frame boundary (t fint ), as shown in figure 17-17. the lcd controller will begin to access data for the next frame within the interval from the interrupt to when the controller begins to access data after the interrupt (t fwr ). new data must be written within t fwr , as this is when the lcd controller will begin to access the data for the next frame. when the lcd driver is running with type-b wave- forms, and the lmux<1:0> bits are not equal to 00 , there are some additional issues that must be addressed. since the dc voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames. if the pixel data were allowed to change, the waveform for the odd frames would not necessarily be the complement of the waveform generated in the even frames and a dc component would be introduced into the panel. there- fore, when using type-b waveforms, the user must synchronize the lcd pixel updates to occur within a subframe after the frame interrupt. to correctly sequence writing while in type-b, the interrupt will only occur on complete phase intervals. if the user attempts to write when the write is disabled, the werr (lcdcon<5>) bit is set. figure 17-17: example waveforms and interrupt timing in quarter duty cycle drive note: the interrupt is not generated when the type-a waveform is selected and when the type-b with no multiplex (static) is selected. frame boundary frame boundary lcd interrupt occurs controller accesses next frame data t fint t fwr t fwr =t frame /2 * (lmux<1:0> + 1) + t cy /2 t fint =(t fwr /2 C (2 t cy + 40 ns)) ?? minimum = 1.5(t frame /4) C (2 t cy + 40 ns) (t fwr /2 C (1 t cy + 40 ns)) ?? maximum = 1.5(t frame /4) C (1 t cy + 40 ns) frame boundary v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 com0 com1 com2 com3 2 frames downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 191 pic18f87j72 family 17.10 operation during sleep the lcd module can operate during sleep. the selec- tion is controlled by the slpen bit (lcdcon<6>). setting the slpen bit allows the lcd module to go to sleep. clearing the slpen bit allows the module to continue to operate during sleep. if a sleep instruction is executed and slpen = 1 , the lcd module will cease all functions and go into a very low-current consumption mode. the module will stop operation immediately and drive the minimum lcd voltage on both segment and common lines. figure 17-18 shows this operation. to ensure that no dc component is introduced on the panel, the sleep instruction should be executed imme- diately after a lcd frame boundary. the lcd interrupt can be used to determine the frame boundary. see section 17.9 lcd interrupts for the formulas to calculate the delay. if a sleep instruction is executed and slpen = 0 , the module will continue to display the current contents of the lcddata registers. to allow the module to continue operation while in sleep, the clock source must be either the timer1 oscillator or one of the internal oscillators (either intrc or intosc as the default system clock). while in sleep, the lcd data cannot be changed. the lcd module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shutdown of the core and other peripheral functions. if the system clock is selected and the module is not configured for sleep operation, the module will ignore the slpen bit and stop operation immediately. the minimum lcd voltage will then be driven onto the segments and commons 17.10.1 using the lcd regulator during sleep applications that use the lcd regulator for bias generation may not achieve the same degree of power reductions in sleep mode when compared to applica- tions using mode 3 (resistor ladder) biasing. this is particularly true with mode 0 operation, where the charge pump is active. if modes 0, 1 or 2 are used for bias generation, software contrast control will not be available. figure 17-18: sleep entry/exit when slpen = 1 or cs<1:0> = 00 sleep instruction execution wake-up 2 frames v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 com0 com1 com2 seg0 downloaded from: http:///
pic18f87j72 family ds39979a-page 192 preliminary ? 2010 microchip technology inc. 17.11 configuring the lcd module the following is the sequence of steps to configure the lcd module. 1. select the frame clock prescale using bits, lp<3:0> (lcdps<3:0>). 2. configure the appropriate pins to function as segment drivers using the lcdsex registers. 3. configure the appropriate pins as inputs using the trisx registers. 4. configure the lcd module for the following using the lcdcon register: multiplex and bias mode (lmux<1:0>) timing source (cs<1:0>) sleep mode (slpen) 5. write initial values to pixel data registers, lcddata0 through lcddata23. 6. configure the lcd regulator: a) if m2 or m3 bias configuration is to be used, turn off the regulator by setting cksel<1:0> (lcdreg<1:0>) to 00 . set or clear the cpen bit (lcdreg<6>) to select mode 2 or mode 3, as appropriate. b) if m0 or m1 bias generation is to be used: set the v bias level using the bias<2:0> bits (lcdreg<5:3>). set or clear the cpen bit to enable or disable the charge pump. set or clear the mode13 bit (lcdreg<2>) to select the bias mode. select a regulator clock source using the cksel<1:0> bits. 7. clear lcd interrupt flag, lcdif (pir3<6>), and if desired, enable the interrupt by setting the lcdie bit (pie3<6>). 8. enable the lcd module by setting the lcden bit (lcdcon<7>). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 193 pic18f87j72 family table 17-6: registers associ ated with lcd operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir3 l c d i f rc2if tx2if ctmuif ccp2if ccp1if rtccif 52 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie 52 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip 52 rcon ipen cm ri to pd por bor 50 lcddata22 s32c3 53 lcddata21 s31c3 s30c3 s29c3 s28c3 s27c3 s26c3 s25c3 s24c3 53 lcddata20 s23c3 s22c3 s21c3 s20c3 s19c3 s18c3 s17c3 s16c3 53 lcddata19 s15c3 s14c3 s13c3 s12c3 s11c3 s10c3 s09c3 s08c3 53 lcddata18 s07c3 s06c3 s05c3 s04c3 s03c3 s02c3 s01c3 s00c3 53 lcddata16 s32c2 53 lcddata15 s31c2 s30c2 s29c2 s28c2 s27c2 s26c2 s25c2 s24c2 53 lcddata14 s23c2 s22c2 s21c2 s20c2 s19c2 s18c2 s17c2 s16c2 53 lcddata13 s15c2 s14c2 s13c2 s12c2 s11c2 s10c2 s09c2 s08c2 53 lcddata12 s07c2 s06c2 s05c2 s04c2 s03c2 s02c2 s01c2 s00c2 53 lcddata10 s32c1 53 lcddata9 s31c1 s30c1 s29c1 s28c1 s27c1 s26c1 s25c1 s24c1 53 lcddata8 s23c1 s22c1 s21c1 s20c1 s19c1 s18c1 s17c1 s16c1 53 lcddata7 s15c1 s14c1 s13c1 s12c1 s11c1 s10c1 s09c1 s08c1 53 lcddata6 s07c1 s06c1 s05c1 s04c1 s03c1 s02c1 s01c1 s00c1 53 lcddata4 s32c0 51 lcddata3 s31c0 s30c0 s29c0 s28c0 s27c0 s26c0 s25c0 s24c0 51 lcddata2 s23c0 s22c0 s21c0 s20c0 s19c0 s18c0 s17c0 s16c0 51 lcddata1 s15c0 s14c0 s13c0 s12c0 s11c0 s10c0 s09c0 s08c0 51 lcddata0 s07c0 s06c0 s05c0 s04c0 s03c0 s02c0 s01c0 s00c0 51 lcdse4 se32 51 lcdse3 se31 se30 se29 se28 se27 se26 se25 se24 51 lcdse2 se23 se22 se21 se20 se19 se18 se17 se16 51 lcdse1 se15 se14 se13 se12 se11 se10 se09 se08 51 lcdse0 se07 se06 se05 se04 se03 se02 se01 se00 51 lcdcon lcden slpen werr cs1 cs0 lmux1 lmux0 51 lcdps wft biasmd lcda wa lp3 lp2 lp1 lp0 51 lcdreg cpen bias2 bias1 bias0 mode13 cksel1 cksel0 50 legend: = unimplemented, read as 0 . shaded cells are not used for lcd operation. note 1: these registers or individual bits are unimplemented on pic18f86j72 devices. note: when the device enters sleep mode while operating in bias modes, m0 or m1, be sure that the bias capacitors are fully discharged in order to get the lowest sleep current. downloaded from: http:///
pic18f87j72 family ds39979a-page 194 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 195 pic18f87j72 family 18.0 master synchronous serial port (mssp) module 18.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c?) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: master mode multi-master mode slave mode 18.2 control registers each mssp module has three associated control registers. these include a status register (sspstat) and two control registers (sspcon1 and sspcon2). the use of these registers and their individual bits differ significantly depending on whether the mssp module is operated in spi or i 2 c mode. additional details are provided under the individual sections. 18.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communication, typically three pins are used: serial data out (sdo) C rc5/sdo/seg12 serial data in (sdi) C rc4/sdi/sda/seg16 serial clock (sck) C rc3/sck/scl/seg17 additionally, a fourth pin may be used when in a slave mode of operation: slave select (ss ) C rf7/an5/ss /seg25 figure 18-1 shows the block diagram of the mssp module when operating in spi mode. figure 18-1: mssp block diagram (spi mode) ( ) read write internal data bus sspsr reg sspm<3:0> bit 0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to txx/rxx in sspsr tris bit 2 smp:cke sdo sspbuf reg sdi ss sck downloaded from: http:///
pic18f87j72 family ds39979a-page 196 preliminary ? 2010 microchip technology inc. 18.3.1 registers each mssp module has four registers for spi mode operation. these are: mssp control register 1 (sspcon1) mssp status register (sspstat) serial receive/transmit buffer register (sspbuf) mssp shift register (sspsr) C not directly accessible sspcon1 and sspstat are the control and status registers in spi mode operation. the sspcon1 register is readable and writable. the lower 6 bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. in receive operations, sspsr and sspbuf together, create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double-buffered. a write to sspbuf will write to both sspbuf and sspsr. register 18-1: sspstat: mssp status register (spi mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r0 r-0 smp cke (1) d/a psr / w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode. bit 6 cke: spi clock select bit (1) 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state bit 5 d/a : data/address bit used in i 2 c? mode only. bit 4 p: stop bit used in i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write information bit used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only. bit 0 bf: buffer full status bit (receive mode only) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty note 1: polarity of clock state is set by the ckp bit (sspcon1<4>). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 197 pic18f87j72 family register 18-2: sspcon1: mssp control register 1 (spi mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov (1) sspen (2) ckp sspm3 (3) sspm2 (3) sspm1 (3) sspm0 (3) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 wcol: write collision detect bit (transmit mode only) 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit (1) spi slave mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over- flow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = no overflow bit 5 sspen: master synchronous serial port enable bit (2) 1 = enables serial port and configures sck, sdo, sdi and ss as serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm<3:0>: master synchronous serial port mode select bits (3) 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as an i/o pin 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note 1: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 2: when enabled, these pins must be properly configured as input or output. 3: bit combinations not specifically listed here are either reserved or implemented in i 2 c? mode only. downloaded from: http:///
pic18f87j72 family ds39979a-page 198 preliminary ? 2010 microchip technology inc. 18.3.2 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon1<5:0> and sspstat<7:6>). these control bits allow the following to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) each mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then, the buffer full detect bit, bf (sspstat<0>), and the interrupt flag bit, sspif, are set. this double-buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol (sspcon1<7>), will be set. user software must clear the wcol bit so that it can be determined if the follow- ing write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. the buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (trans- mission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 18-1 shows the loading of the sspbuf (sspsr) for data transmission. the sspsr is not directly readable or writable and can only be accessed by addressing the sspbuf register. additionally, the sspstat register indicates the various status conditions. example 18-1: loading the sspbuf (sspsr) register note: to prevent lost data in master mode, read sspbuf after each transmission to clear the bf bit. loop btfss sspstat, bf ;has data been received (transmit complete)? bra loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 199 pic18f87j72 family 18.3.3 enabling spi i/o to enable the serial port, mssp enable bit, sspen (sspcon1<5>), must be set. to reset or reconfigure spi mode, clear the sspen bit, reinitialize the sspcon registers and then set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port func- tion, some must have their data direction bits (in the tris register) appropriately programmed as follows: sdi is automatically controlled by the spi module sdo must have trisc<5> bit cleared sck (master mode) must have trisc<3> bit cleared sck (slave mode) must have trisc<3> bit set ss must have trisf<7> bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. 18.3.4 open-drain output option the drivers for the sdo output and sck clock pins can be optionally configured as open-drain outputs. this feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor, and allows the output to communicate with external circuits without the need for additional level shifters. the open-drain output option is controlled by the spiod bit (trisg<7>). setting the bit configures both pins for open-drain operation. 18.3.5 typical connection figure 18-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock. both processors should be programmed to the same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data ? C ? slave sends dummy data master sends data ? C ? slave sends data master sends dummy data ? C ? slave sends data figure 18-2: spi master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm<3:0> = 00xx serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm<3:0> = 010x serial clock downloaded from: http:///
pic18f87j72 family ds39979a-page 200 preliminary ? 2010 microchip technology inc. 18.3.6 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 18-2) will broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a line activity monitor mode. the clock polarity is selected by appropriately programming the ckp bit (sspcon1<4>). this, then, would give waveforms for spi communication as shown in figure 18-3, figure 18-5 and figure 18-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user-programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 t cy ) f osc /64 (or 16 t cy ) timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 18-3 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 18-3: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) next q4 cycle after q2 ? bit 0 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 201 pic18f87j72 family 18.3.7 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sck pin. the idle state is determined by the ckp bit (sspcon1<4>). while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 18.3.8 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). when the ss pin is low, trans- mission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the application. when the spi module resets, the bit counter is forced to 0 . this can be done by either forcing the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus conflict. figure 18-4: slave synchronization waveform note 1: when the spi is in slave mode with ss pin control enabled (sspcon1<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 next q4 cycle after q2 ? downloaded from: http:///
pic18f87j72 family ds39979a-page 202 preliminary ? 2010 microchip technology inc. figure 18-5: spi mode waveform (slave mode with cke = 0 ) figure 18-6: spi mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2 ? bit 0 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2 ? downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 203 pic18f87j72 family 18.3.9 operation in power-managed modes in spi master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of sleep mode, all clocks are halted. in idle modes, a clock is provided to the peripherals. that clock should be from the primary clock source, the secondary clock (timer1 oscillator at 32.768 khz) or the intrc source. see section 3.3 clock sources and oscillator switching for additional information. in most cases, the speed that the master clocks spi data is not important; however, this should be evaluated for each system. if mssp interrupts are enabled, they can wake the con- troller from sleep mode, or one of the idle modes, when the master completes sending data. if an exit from sleep or idle mode is not desired, mssp interrupts should be disabled. if the sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. after the device returns to run mode, the module will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in any power-managed mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set, and if enabled, will wake the device. 18.3.10 effects of a reset a reset disables the mssp module and terminates the current transfer. 18.3.11 bus mode compatibility table 18-1 shows the compatibility between the standard spi modes and the states of the ckp and cke control bits. there is also an smp bit which controls when the data is sampled. table 18-1: spi bus modes table 18-2: registers associat ed with spi operation standard spi mode terminology control bits state ckp cke 0, 0 (1) 01 0, 1 0 0 1, 0 1 1 1, 1 (1) 10 note 1: use one of these modes when using the spi to communicate with the afe. see section 22.5 using the afe for more information. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 adif rc1if tx1if sspif tmr2if tmr1if 52 pie1 adie rc1ie tx1ie sspie tmr2ie tmr1ie 52 ipr1 adip rc1ip tx1ip sspip tmr2ip tmr1ip 52 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 52 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 5 2 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 52 sspbuf mssp receive buffer/transmit register 50 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 50 sspstat smp cke d/a p s r/w ua bf 50 legend: shaded cells are not used by the mssp module in spi mode. downloaded from: http:///
pic18f87j72 family ds39979a-page 204 preliminary ? 2010 microchip technology inc. 18.4 i 2 c mode the mssp module in i 2 c mode fully implements all master and slave functions (including general call support) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master function). the mssp module implements the standard mode specifications as well as 7-bit and 10-bit addressing. two pins are used for data transfer: serial clock (scl) C rc3/sck/scl/seg17 serial data (sda) C rc4/sdi/sda/seg16 the user must configure these pins as inputs by setting the trisc<4:3> bits. figure 18-7: mssp block diagram (i 2 c? mode) 18.4.1 registers the mssp module has six registers for i 2 c operation. these are: mssp control register 1 (sspcon1) mssp control register 2 (sspcon2) mssp status register (sspstat) serial receive/transmit buffer register (sspbuf) mssp shift register (sspsr) C not directly accessible mssp address register (sspadd) sspcon1, sspcon2 and sspstat are the control and status registers in i 2 c mode operation. the sspcon1 and sspcon2 registers are readable and writable. the lower 6 bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. many of the bits in sspcon2 assume different functions, depending on whether the module is operat- ing in master or slave mode; bits<5:2> also assume different names in slave mode. the different aspects of sspcon2 are shown in register 18-5 (for master mode) and register 18-6 (slave mode). sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. sspadd register holds the slave device address when the mssp is configured in i 2 c slave mode. when the mssp is configured in master mode, the lower seven bits of sspadd act as the baud rate generator reload value. in receive operations, sspsr and sspbuf together, create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) shift clock msb lsb scl sda address mask downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 205 pic18f87j72 family register 18-3: sspstat: mssp status register (i 2 c? mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a p (1) s (1) r/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 smp: slew rate control bit in master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high-speed mode (400 khz) bit 6 cke: smbus select bit in master or slave mode: 1 = enable smbus specific inputs 0 = disable smbus specific inputs bit 5 d/a : data/address bit in master mode: reserved. in slave mode: 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (1) 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last bit 3 s: start bit (1) 1 = indicates that a start bit has been detected last 0 = start bit was not detected last bit 2 r/w : read/write information bit (i 2 c? mode only) in slave mode: (2) 1 = read 0 = write in master mode: (3) 1 = transmit is in progress 0 = transmit is not in progress bit 1 ua: update address bit (10-bit slave mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit in transmit mode: 1 = sspbuf is full 0 = sspbuf is empty in receive mode: 1 = sspbuf is full (does not include the ack and stop bits) 0 = sspbuf is empty (does not include the ack and stop bits) note 1: this bit is cleared on reset and when sspen is cleared. 2: this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. 3: oring this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in active mode. downloaded from: http:///
pic18f87j72 family ds39979a-page 206 preliminary ? 2010 microchip technology inc. register 18-4: sspcon1: ms sp control register 1 (i 2 c? mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen (1) ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 wcol: write collision detect bit in master transmit mode: 1 = a write to the sspbuf register is attempted while the i 2 c? conditions are not valid for a transmission to be started (must be cleared in software) 0 = no collision in slave transmit mode: 1 = the sspbuf register is written while it was still transmitting the previous word (must be cleared in software) 0 = no collision in receive mode (master or slave modes): this is a dont care bit. bit 6 sspov: receive overflow indicator bit in receive mode: 1 = a byte is received while the sspbuf register is still holding the previous byte (must be cleared in software) 0 = no overflow in transmit mode: this is a dont care bit in transmit mode. bit 5 sspen: master synchronous serial port enable bit (1) 1 = enables the serial port and configures the sda and scl pins as the serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: sck release control bit in slave mode: 1 = releases clock 0 = holds clock low (clock stretch); used to ensure data setup time in master mode: unused in this mode. bit 3-0 sspm<3:0>: synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1011 = i 2 c firmware controlled master mode (slave idle) 1000 = i 2 c master mode, clock = f osc /(4 * (sspadd + 1)) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address bit combinations not specifically listed here are either reserved or implemented in spi mode only. note 1: when enabled, the sda and scl pins must be configured as inputs. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 207 pic18f87j72 family register 18-5: sspcon2: ms sp control register 2 (i 2 c? master mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt (1) acken (2) rcen (2) pen (2) rsen (2) sen (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 gcen: general call enable bit unused in master mode. bit 6 ackstat: acknowledge status bit (master transmit mode only) 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (master receive mode only) (1) 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (2) 1 = initiate acknowledge sequence on sda and scl pins and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (master receive mode only) (2) 1 = enables receive mode for i 2 c? 0 = receive idle bit 2 pen: stop condition enable bit (2) 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (2) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable bit (2) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle note 1: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 2: if the i 2 c module is active, these bits may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). downloaded from: http:///
pic18f87j72 family ds39979a-page 208 preliminary ? 2010 microchip technology inc. register 18-6: sspcon2: ms sp control register 2 (i 2 c? slave mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat admsk5 admsk4 admsk3 admsk2 admsk1 sen (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 gcen: general call enable bit 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit unused in slave mode. bit 5-2 admsk<5:2>: slave address mask select bits 1 = masking of corresponding bits of sspadd is enabled 0 = masking of corresponding bits of sspadd is disabled bit 1 admsk1: slave address least significant bit(s) mask select bit in 7-bit addressing mode: 1 = masking of sspadd<1> only is enabled 0 = masking of sspadd<1> only is disabled in 10-bit addressing mode: 1 = masking of sspadd<1:0> is enabled 0 = masking of sspadd<1:0> is disabled bit 0 sen: stretch enable bit (1) 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: if the i 2 c? module is active, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 209 pic18f87j72 family 18.4.2 operation the mssp module functions are enabled by setting the mssp enable bit, sspen (sspcon1<5>). the sspcon1 register allows control of the i 2 c operation. four mode selection bits (sspcon1<3:0>) allow one of the following i 2 c modes to be selected: i 2 c master mode, clock = (f osc /4) x (sspadd + 1) i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address) with start and stop bit interrupts enabled i 2 c slave mode (10-bit address) with start and stop bit interrupts enabled i 2 c firmware controlled master mode, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate trisc or trisd bits. to ensure proper operation of the module, pull-up resistors must be provided externally to the scl and sda pins. 18.4.3 slave mode in slave mode, the scl and sda pins must be configured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). the i 2 c slave mode hardware will always generate an interrupt on an exact address match. in addition, address masking will also allow the hardware to gener- ate an interrupt for more than one address (up to 31 in 7-bit addressing and up to 63 in 10-bit addressing). through the mode select bits, the user can also choose to interrupt on start and stop bits. when an address is matched, or the data transfer after an address match is received, the hardware auto- matically will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value currently in the sspsr register. any combination of the following conditions will cause the mssp module not to give this ack pulse: the buffer full bit, bf (sspstat<0>), was set before the transfer was received. the overflow bit, sspov (sspcon1<6>), was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit, sspif, is set. the bf bit is cleared by reading the sspbuf register, while bit, sspov, is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter 100 and parameter 101. 18.4.3.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8 bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register, sspsr<7:1>, is compared to the value of the sspadd register. the address is com- pared on the falling edge of the eighth clock (scl) pulse. if the addresses match and the bf and sspov bits are clear, the following events occur: 1. the sspsr register value is loaded into the sspbuf register. 2. the buffer full bit, bf, is set. 3. an ack pulse is generated. 4. the mssp interrupt flag bit, sspif, is set (and interrupt is generated, if enabled) on the falling edge of the ninth scl pulse. in 10-bit addressing mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit, r/w (sspstat<2>), must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal 11110 a9 a8 0 , where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit addressing is as follows, with steps 7 through 9 for the slave-transmitter: 1. receive first (high) byte of address (sspif, bf and ua bits (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears ua bit and releases the scl line). 3. read the sspbuf register (clears bf bit) and clear flag bit, sspif. 4. receive second (low) byte of address (sspif, bf and ua bits are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear ua bit. 6. read the sspbuf register (clears bf bit) and clear flag bit, sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (sspif and bf bits are set). 9. read the sspbuf register (clears bf bit) and clear flag bit, sspif. downloaded from: http:///
pic18f87j72 family ds39979a-page 210 preliminary ? 2010 microchip technology inc. 18.4.3.2 address masking masking an address bit causes that bit to become a dont care. when one address bit is masked, two addresses will be acknowledged and cause an interrupt. it is possible to mask more than one address bit at a time, which makes it possible to acknowledge up to 31 addresses in 7-bit mode and up to 63 addresses in 10-bit mode (see example 18-2). the i 2 c slave behaves the same way whether address masking is used or not. however, when address masking is used, the i 2 c slave can acknowledge multiple addresses and cause interrupts. when this occurs, it is necessary to determine which address caused the interrupt by checking sspbuf. in 7-bit addressing mode, address mask bits, admsk<5:1> (sspcon<5:1>), mask the correspond- ing address bits in the sspadd register. for any admsk bits that are set (admsk = 1 ), the corresponding address bit is ignored (sspadd = x ). for the module to issue an address acknowledge, it is sufficient to match only on addresses that do not have an active address mask. in 10-bit addressing mode, admsk<5:2> bits mask the corresponding address bits in the sspadd regis- ter. in addition, admsk1 simultaneously masks the two lsbs of the address (sspadd<1:0>). for any admsk bits that are active (admsk = 1 ), the correspond- ing address bit is ignored (sspadd = x ). also note, that although in 10-bit addressing mode, the upper address bits reuse part of the sspadd register bits; the address mask bits do not interact with those bits. they only affect the lower address bits. example 18-2: address masking examples note 1: admsk1 masks the two least significant bits of the address. 2: the two most significant bits of the address are not affected by address masking. 7-bit addressing: sspadd<7:1> = a0h ( 1010000 ) (sspadd<0> is assumed to be 0 ) admsk<5:1> = 00111 addresses acknowledged: a0h, a2h, a4h, a6h, a8h, aah, ach, aeh 10-bit addressing: sspadd<7:0> = a0h ( 10100000 ) (the two msbs of the address are ignored in this example, since they are not affected by masking) admsk<5:1> = 00111 addresses acknowledged: a0h, a1h, a2h, a3h, a4h, a5h, a6h, a7h, a8h, a9h, aah, abh, ach, adh, aeh, afh downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 211 pic18f87j72 family 18.4.3.3 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and the sda line is held low (ack ). when the address byte overflow condition exists, then the no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit, bf (sspstat<0>), is set or bit, sspov (sspcon1<6>), is set. an mssp interrupt is generated for each data transfer byte. the interrupt flag bit, sspif, must be cleared in software. the sspstat register is used to determine the status of the byte. if sen is enabled (sspcon2<0> = 1 ), sck/scl will be held low (clock stretch) following each data transfer. the clock must be released by setting bit, ckp (sspcon1<4>). see section 18.4.4 clock stretching for more details. 18.4.3.4 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin, rc3, is held low, regardless of sen (see section 18.4.4 clock stretching for more details). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register which also loads the sspsr register. then, the rc3 pin should be enabled by setting bit, ckp (sspcon1<4>). the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 18-10). the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is complete. in this case, when the ack is latched by the slave, the slave logic is reset and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, pin, rc3, must be enabled by setting bit, ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse. downloaded from: http:///
pic18f87j72 family ds39979a-page 212 preliminary ? 2010 microchip technology inc. figure 18-8: i 2 c? slave mode timing with sen = 0 (reception, 7-bit addressing) sda scl sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon1<6>) s 1 234567891234567891 2345 789 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 ckp (ckp does not reset to 0 when sen = 0 ) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 213 pic18f87j72 family figure 18-9: i 2 c? slave mode timing with sen = 0 and admsk<5:1> = 01011 (reception, 7-bit addressing) sdascl sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon1<6>) s 1 234567 89 12 34567 891 2345 7 89 p a7 a6 a5 x a3 x x d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 ckp (ckp does not reset to 0 when sen = 0 ) note 1: x = dont care (i.e., address bit can be eithe r a 1 or a 0 ) . 2: in this example, an address equal to a7.a6.a5.x.a3.x.x will be acknowledged and cause an in terrupt. downloaded from: http:///
pic18f87j72 family ds39979a-page 214 preliminary ? 2010 microchip technology inc. figure 18-10: i 2 c? slave mode timing (transmission, 7-bit addressing) sdascl bf (sspxstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software data in sampled s ack transmitting data r/w = 1 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr transmitting data d7 1 ckp (sspxcon1<4>) p ack ckp is set in software ckp is set in software scl held low while cpu responds to sspif sspif (pir1<3> or pir3<7>) from sspif isr clear by reading downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 215 pic18f87j72 family figure 18-11: i 2 c? slave mode timing with sen = 0 (reception, 10-bit addressing) sdascl sspif (pir1<3>) bf (sspstat<0>) s 123456789 12 3456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1a0 d7 d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) sspov is set because sspbuf is still full. ack is not sent. (ckp does not reset to 0 when sen = 0 ) clock is held low until update of sspadd has taken place downloaded from: http:///
pic18f87j72 family ds39979a-page 216 preliminary ? 2010 microchip technology inc. figure 18-12: i 2 c? slave mode timing with sen = 0 and admsk<5:1> = 01001 (reception, 10-bit addressing) sda scl sspif (pir1<3>) bf (sspstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9 a8 a7 a6 a5 x a3 a2 x x d7 d6 d5 d4 d3 d1 d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) sspov is set because sspbuf is still full. ack is not sent. (ckp does not reset to 0 when sen = 0 ) clock is held low until update of sspadd has taken place note 1: x = dont care (i.e., address bit can be either a 1 or a 0 ). 2: in this example, an address equal to a9.a8.a7.a6.a5 .x.a3.a2.x.x will be acknowl edged and cause an interrupt. 3: note that the most significant bits of the address are not affected by the bit masking. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 217 pic18f87j72 family figure 18-13: i 2 c? slave mode timing (transmission, 10-bit addressing) sdascl sspif (pir1<3>) bf (sspstat<0>) s 123456789 123456789 12345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1a0 11110 a8 r/w = 1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer a9 6 receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software completion of clears bf flag ckp (sspcon1<4>) ckp is set in software ckp is automatically cleared in hardware, holding scl low clock is held low until update of sspadd has taken place data transmission clock is held low until ckp is set to 1 third address sequence bf flag is clear at the end of the downloaded from: http:///
pic18f87j72 family ds39979a-page 218 preliminary ? 2010 microchip technology inc. 18.4.4 clock stretching both 7-bit and 10-bit slave modes implement automatic clock stretching during a transmit sequence. the sen bit (sspcon2<0>) allows clock stretching to be enabled during receives. setting sen will cause the scl pin to be held low at the end of each data receive sequence. 18.4.4.1 clock stretching for 7-bit slave receive mode (sen = 1 ) in 7-bit slave receive mode, on the falling edge of the ninth clock at the end of the ack sequence, if the bf bit is set, the ckp bit in the sspcon1 register is automatically cleared, forcing the scl output to be held low. the ckp being cleared to 0 will assert the scl line low. the ckp bit must be set in the users isr before reception is allowed to continue. by holding the scl line low, the user has time to service the isr and read the contents of the sspbuf before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring (see figure 18-15). 18.4.4.2 clock stretching for 10-bit slave receive mode (sen = 1 ) in 10-bit slave receive mode, during the address sequence, clock stretching automatically takes place but ckp is not cleared. during this time, if the ua bit is set after the ninth clock, clock stretching is initiated. the ua bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the r/w bit cleared to 0 . the release of the clock line occurs upon updating sspadd. clock stretching will occur on each data receive sequence as described in 7-bit mode. 18.4.4.3 clock stretching for 7-bit slave transmit mode the 7-bit slave transmit mode implements clock stretching by clearing the ckp bit after the falling edge of the ninth clock if the bf bit is clear. this occurs regardless of the state of the sen bit. the users isr must set the ckp bit before transmis- sion is allowed to continue. by holding the scl line low, the user has time to service the isr and load the contents of the sspbuf before the master device can initiate another transmit sequence (see figure 18-10). 18.4.4.4 clock stretching for 10-bit slave transmit mode in 10-bit slave transmit mode, clock stretching is con- trolled during the first two address sequences by the state of the ua bit, just as it is in 10-bit slave receive mode. the first two addresses are followed by a third address sequence which contains the high-order bits of the 10-bit address and the r/w bit set to 1 . after the third address sequence is performed, the ua bit is not set, the module is now configured in transmit mode and clock stretching is controlled by the bf flag as in 7-bit slave transmit mode (see figure 18-13). note 1: if the user reads the contents of the sspbuf before the falling edge of the ninth clock, thus clearing the bf bit, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. the user should be careful to clear the bf bit in the isr before the next receive sequence in order to prevent an overflow condition. note: if the user polls the ua bit and clears it by updating the sspadd register before the falling edge of the ninth clock occurs and if the user hasnt cleared the bf bit by read- ing the sspbuf register before that time, then the ckp bit will still not be asserted low. clock stretching on the basis of the state of the bf bit only occurs during a data sequence, not an address sequence. note 1: if the user loads the contents of sspbuf, setting the bf bit before the falling edge of the ninth clock, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 219 pic18f87j72 family 18.4.4.5 clock synchronization and the ckp bit when the ckp bit is cleared, the scl output is forced to 0 . however, clearing the ckp bit will not assert the scl output low until the scl output is already sampled low. therefore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have deasserted scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 18-14). figure 18-14: clock synchronization timing sda scl dx C 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon ckp master device deasserts clock master device asserts clock downloaded from: http:///
pic18f87j72 family ds39979a-page 220 preliminary ? 2010 microchip technology inc. figure 18-15: i 2 c? slave mode timing with sen = 1 (reception, 7-bit addressing) sdascl sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon1<6>) s 1 234 56 7 89 1 2345 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 ckp ckp written to 1 in if bf is cleared prior to the falling edge of the 9th clock, ckp will not be reset to 0 and no clock stretching will occur software clock is held low until ckp is set to 1 clock is not held low because buffer full bit is clear prior to falling edge of 9th clock clock is not held low because ack = 1 bf is set after falling edge of the 9th clock, ckp is reset to 0 and clock stretching occurs downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 221 pic18f87j72 family figure 18-16: i 2 c? slave mode timing with sen = 1 (reception, 10-bit addressing) sda scl sspif (pir1<3>) bf (sspstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address after falling edge ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address after falling edge sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) ckp written to 1 note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. in software clock is held low until update of sspadd has taken place of ninth clock of ninth clock sspov is set because sspbuf is still full. ack is not sent. dummy read of sspbuf to clear bf flag clock is held low until ckp is set to 1 clock is not held low because ack = 1 downloaded from: http:///
pic18f87j72 family ds39979a-page 222 preliminary ? 2010 microchip technology inc. 18.4.5 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually determines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all 0 s with r/w = 0 . the general call address is recognized when the general call enable bit, gcen, is enabled (sspcon2<7> set). following a start bit detect, 8 bits are shifted into the sspsr and the address is compared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag bit is set (eighth bit), and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device-specific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match and the ua bit is set (sspstat<1>). if the general call address is sampled when the gcen bit is set, while the slave is configured in 10-bit addressing mode, then the second half of the address is not necessary, the ua bit will not be set and the slave will begin receiving data after the acknowledge (figure 18-17). figure 18-17: slave mode general call address sequence (7 or 10-bit addressing mode) sda scl s sspif bf (sspstat<0>) sspov (sspcon1<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt 0 1 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 223 pic18f87j72 family 18.4.6 master mode master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. in master mode, the scl and sda lines are manipulated by the mssp hardware. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle, with both the s and p bits clear. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit conditions. once master mode is enabled, the user has six options. 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register initiating transmission of data/address. 4. configure the i 2 c port to receive data. 5. generate an acknowledge condition at the end of a received byte of data. 6. generate a stop condition on sda and scl. the following events will cause the mssp interrupt flag bit, sspif, to be set (and mssp interrupt, if enabled): start condition stop condition data transfer byte transmitted/received acknowledge transmit repeated start figure 18-18: mssp block diagram (i 2 c? master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start con- dition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, sspbuf internal data bus set/reset s, p, wcol (sspstat, sspcon1) shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset ackstat, pen (sspcon2) rate generator sspm<3:0> start bit detect downloaded from: http:///
pic18f87j72 family ds39979a-page 224 preliminary ? 2010 microchip technology inc. 18.4.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic 0 . serial data is transmitted, 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic 1 . thus, the first byte transmitted is a 7-bit slave address followed by a 1 to indicate the receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmit- ted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator, used for the spi mode operation, is used to set the scl clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. see section 18.4.7 baud rate for more detail. a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit, sen (sspcon2<0>). 2. sspif is set. the mssp module will wait the required start time before any other operation takes place. 3. the user loads the sspbuf with the slave address to transmit. 4. address is shifted out the sda pin until all 8 bits are transmitted. 5. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 6. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 7. the user loads the sspbuf with eight bits of data. 8. data is shifted out the sda pin until all 8 bits are transmitted. 9. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 10. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 11. the user generates a stop condition by setting the stop enable bit, pen (sspcon2<2>). 12. interrupt is generated once the stop condition is complete. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 225 pic18f87j72 family 18.4.7 baud rate in i 2 c master mode, the baud rate generator (brg) reload value is placed in the lower 7 bits of the sspadd register (figure 18-19). when a write occurs to sspbuf, the baud rate generator will automatically begin counting. the brg counts down to 0 and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack ), the internal clock will automatically stop counting and the scl pin will remain in its last state. table 18-3 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. 18.4.7.1 baud rate generation in power-managed modes when the device is operating in one of the power-managed modes, the clock source to the brg may change frequency or even stop, depending on the mode and clock source selected. switching to a run or idle mode from either the secondary clock or internal oscillator is likely to change the clock rate to the brg. in sleep mode, the brg will not be clocked at all. figure 18-19: baud rate generator block diagram table 18-3: i 2 c? clock rate w/brg note: a brg value of 00h is not supported. f cy f cy * 2 brg value f scl (2 rollovers of brg) 16 mhz 32 mhz 03h 1 mhz (1) 10 mhz 20 mhz 18h 400 khz (2) 10 mhz 20 mhz 1fh 312.5 khz 10 mhz 20 mhz 63h 100 khz 4 mhz 8 mhz 09h 400 khz (2) 4 mhz 8 mhz 0ch 308 khz 4 mhz 8 mhz 27h 100 khz 1 mhz 2 mhz 02h 333 khz (2) 1 mhz 2 mhz 09h 100 khz note 1: f osc must be at least 16 mhz for i 2 c bus operation at this speed. 2: the i 2 c? interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. sspm<3:0> brg down counter clko f osc /4 sspadd<6:0> sspm<3:0> scl reload control reload downloaded from: http:///
pic18f87j72 family ds39979a-page 226 preliminary ? 2010 microchip technology inc. 18.4.7.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, deasserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device (figure 18-20). figure 18-20: baud rate generator timing with clock arbitration sda scl scl deasserted but slave holds dx C 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 227 pic18f87j72 family 18.4.8 i 2 c master mode start condition timing to initiate a start condition, the user sets the start enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit (sspstat<3>) to be set. following this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will automatically be cleared by hardware. the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. 18.4.8.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 18-21: first start bit timing note: if, at the beginning of the start condition, the sda and scl pins are already sampled low, or if during the start condi- tion, the scl line is sampled low before the sda line is driven low, a bus collision occurs. the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit downloaded from: http:///
pic18f87j72 family ds39979a-page 228 preliminary ? 2010 microchip technology inc. 18.4.9 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded with the contents of sspadd<6:0> and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. following this, the rsen bit (sspcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 18.4.9.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 18-22: repeated start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: sda is sampled low when scl goes from low-to-high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data 1 . note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here on falling edge of ninth clock, end of xmit at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sda = 1 , sda = 1 , scl (no change) scl = 1 occurs here: t brg t brg and sets sspif rsen bit set by hardware t brg downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 229 pic18f87j72 family 18.4.10 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by simply writing a value to the sspbuf register. this action will set the buffer full bit, bf, and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification parameter 106). scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high (see data setup time specification parameter 107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received prop- erly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared; if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged (figure 18-23). after the write to the sspbuf, each bit of the address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will deassert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmission of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 18.4.10.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 18.4.10.2 wcol status flag if the user writes to the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buf- fer are unchanged (the write doesnt occur) after 2 t cy after the sspbuf write. if sspbuf is rewritten within 2 t cy , the wcol bit is set and sspbuf is updated. this may result in a corrupted transfer. the user should verify that the wcol is clear after each write to sspbuf to ensure the transfer is correct. in all cases, wcol must be cleared in software. 18.4.10.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowl- edge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 18.4.11 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to-low/low-to-high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the con- tents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 18.4.11.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 18.4.11.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 18.4.11.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesnt occur). note: the mssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded. downloaded from: http:///
pic18f87j72 family ds39979a-page 230 preliminary ? 2010 microchip technology inc. figure 18-23: i 2 c? master mode waveform (transmission, 7 or 10-bit addressing) sdascl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from mssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> (sen = 1 ), start condition begins from slave, clear ackstat bit (sspcon2<6>) ackstat in sspcon2 = 1 cleared in software sspbuf written pen r/w cleared in software downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 231 pic18f87j72 family figure 18-24: i 2 c? master mode waveform (reception, 7-bit addressing) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sdascl 1 23456 789 12345678 9 123 4 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ), write to sspbuf occurs here, ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu (sspstat<0>) ack cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif ack from master, set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknowledge sequence of receive set acken, start acknowledge sequence, sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence, sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically acken begin start condition cleared in software sda = ackdt = 0 last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software sspov is set because sspbuf is still full responds to sspif downloaded from: http:///
pic18f87j72 family ds39979a-page 232 preliminary ? 2010 microchip technology inc. 18.4.12 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 18-25). 18.4.12.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). 18.4.13 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2<2>). at the end of a receive/transmit, the scl line is held low after the fall- ing edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sampled high while scl is high, the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 18-26). 18.4.13.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write doesnt occur). figure 18-25: acknowledge sequence waveform figure 18-26: stop condition receive or transmit mode note: t brg = one baud rate generator period. sda scl sspif set at acknowledge sequence starts here, write to sspcon2, acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspif software sspif set at the end of acknowledge sequence cleared in software ack sclsda sda asserted low before rising edge of clock write to sspcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 233 pic18f87j72 family 18.4.14 sleep operation while in sleep mode, the i 2 c module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 18.4.15 effects of a reset a reset disables the mssp module and terminates the current transfer. 18.4.16 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the mssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed in hardware with the result placed in the bclif bit. the states where arbitration can be lost are: address transfer data transfer a start condition a repeated start condition an acknowledge condition 18.4.17 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a 1 on sda by letting sda float high, and another master asserts a 0 . when the scl pin floats high, data should be stable. if the expected data on sda is a 1 and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif, and reset the i 2 c port to its idle state (figure 18-27). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deasserted, and the respective control bits in the sspcon2 register, are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. figure 18-27: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data doesnt match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0 downloaded from: http:///
pic18f87j72 family ds39979a-page 234 preliminary ? 2010 microchip technology inc. 18.4.17.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 18-28). b) scl is sampled low before sda is asserted low (figure 18-29). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: the start condition is aborted; the bclif flag is set; and the mssp module is reset to its idle state (figure 18-28). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data 1 during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 18-30). if, however, a 1 is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0. if the scl pin is sampled as 0 during this time, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 18-28: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus colli- sion because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because mssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif sspif sda = 0 , scl = 1 . sspif and bclif are cleared in software sspif and bclif are cleared in software set bclif, start condition. set bclif. s downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 235 pic18f87j72 family figure 18-29: bus collision during start condition (scl = 0 ) figure 18-30: brg reset due to sda arbitration during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared in software bus collision occurs. set bclif. scl = 0 before brg time-out, 0 0 0 0 sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0 , scl = 1 , scl pulled low after brg time-out set sspif 0 sda pulled low by other master. reset brg and assert sda. set sen, enable start sequence if sda = 1 , scl = 1 downloaded from: http:///
pic18f87j72 family ds39979a-page 236 preliminary ? 2010 microchip technology inc. 18.4.17.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data 1 . when the user deasserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to 0 . the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data 0 , see figure 18-31). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data 1 during the repeated start condition (see figure 18-32). if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 18-31: bus collision during a repeated start condition (case 1) figure 18-32: bus collision during repeated start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared in software 0 0 sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl. t brg t brg 0 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 237 pic18f87j72 family 18.4.17.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data 0 (figure 18-33). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data 0 (figure 18-34). figure 18-33: bus collision during a stop condition (case 1) figure 18-34: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif 0 0 sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif 0 0 downloaded from: http:///
pic18f87j72 family ds39979a-page 238 preliminary ? 2010 microchip technology inc. table 18-4: registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 adif rc1if tx1if sspif tmr2if tmr1if 52 pie1 adie rc1ie tx1ie sspie tmr2ie tmr1ie 52 ipr1 adip rc1ip tx1ip sspip tmr2ip tmr1ip 52 pir2 oscfif cmif b c l i f lvdif tmr3if 5 2 pie2 oscfie cmie b c l i e lvdie tmr3ie 5 2 ipr2 oscfip cmip b c l i p lvdip tmr3ip 5 2 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 52 sspbuf mssp receive buffer/transmit register 50 sspadd mssp address register (i 2 c? slave mode), mssp baud rate reload register (i 2 c master mode) 50 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 50 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 50 gcen ackstat admsk5 (1) admsk4 (1) admsk3 (1) admsk2 (1) admsk1 (1) sen sspstat smp cke d/a psr / w ua bf 50 legend: = unimplemented, read as 0 . shaded cells are not used by the mssp module in i 2 c? mode. note 1: alternate bit definitions for use in i 2 c slave mode operations only. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 239 pic18f87j72 family 19.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) pic18f87j72 family devices have three serial i/o modules: the mssp module, discussed in the previous chapter and two universal synchronous asynchronous receiver transmitter (usart) modules. (generically, the usart is also known as a serial communications interface or sci.) the usart can be configured as a full-duplex asynchronous system that can communi- cate with peripheral devices, such as crt terminals and personal computers. it can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. there are two distinct implementations of the usart module in these devices: the enhanced usart (eusart) discussed here and the addressable usart discussed in the next chapter. for this device family, usart1 always refers to the eusart, while usart2 is always the ausart. the eusart and ausart modules implement the same core features for serial communications; their basic operation is essentially the same. the eusart module provides additional features, including auto- matic baud rate detection and calibration, automatic wake-up on sync break reception and 12-bit break character transmit. these features make it ideally suited for use in local interconnect network bus (lin/j2602 bus) systems. the eusart can be configured in the following modes: asynchronous (full-duplex) with: - auto-wake-up on character reception - auto-baud calibration - 12-bit break character transmission synchronous C master (half-duplex) with selectable clock polarity synchronous C slave (half-duplex) with selectable clock polarity the pins of the eusart are multiplexed with the functions of portc (rc6/tx1/ck1/seg27 and rc7/rx1/dt1/seg28). in order to configure these pins as an eusart: spen bit (rcsta1<7>) must be set (= 1 ) trisc<7> bit must be set (= 1 ) trisc<6> bit must be set (= 1 ) the driver for the tx1 output pin can also be optionally configured as an open-drain output. this feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor, and allows the out- put to communicate with external circuits without the need for additional level shifters. the open-drain output option is controlled by the u1od bit (latg<6>). setting this bit configures the pin for open-drain operation. 19.1 control registers the operation of the enhanced usart module is controlled through three registers: transmit status and control register 1 (txsta1) receive status and control register 1 (rcsta1) baud rate control register 1 (baudcon1) the registers are described in register 19-1, register 19-2 and register 19-3. note: the eusart control will automatically reconfigure the pin from input to output as needed. downloaded from: http:///
pic18f87j72 family ds39979a-page 240 preliminary ? 2010 microchip technology inc. register 19-1: txsta1: eusart transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 csrc: clock source select bit asynchronous mode: dont care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit is enabled 0 = transmit is disabled bit 4 sync: eusart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode: 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode: dont care. bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsr is empty 0 = tsr is full bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 241 pic18f87j72 family register 19-2: rcsta1: eusart rece ive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 spen: serial port enable bit 1 = serial port is enabled 0 = serial port is disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : dont care. synchronous mode C master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode C slave: dont care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit, cren, is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enables interrupt and loads the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 9-bit (rx9 = 0 ) : dont care. bit 2 ferr: framing error bit 1 = framing error (can be cleared by reading the rcreg1 register and receiving the ne xt valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit, cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be address/data bit or a parity bit and must be calculated by user firm ware. downloaded from: http:///
pic18f87j72 family ds39979a-page 242 preliminary ? 2010 microchip technology inc. register 19-3: baudcon1: baud ra te control register 1 r/w-0 r-1 r/w - 0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 abdovf rcmt rxdtp txckp brg16 wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 abdovf : auto-baud acquisition rollover status bit 1 = a brg rollover has occurred during auto-baud rate detect mode (must be cleared in software) 0 = no brg rollover has occurred bit 6 rcmt : receive operation idle status bit 1 = receive operation is idle 0 = receive operation is active bit 5 rxdtp : received data polarity select bit (asynchronous mode only) 1 = rxx data is inverted 0 = rxx data is not inverted bit 4 txckp : clock and data polarity select bit asynchronous mode: 1 = transmit idle state is low 0 = transmit idle state is high synchronous mode: 1 = ckx clock idle state is high 0 = ckx clock idle state is low bit 3 brg16: 16-bit baud rate register enable bit 1 = 16-bit baud rate generator C spbrgh1 and spbrg1 0 = 8-bit baud rate generator C spbrg1 only (compatible mode), spbrgh1 value is ignored bit 2 unimplemented: read as 0 bit 1 wue: wake-up enable bit asynchronous mode: 1 = eusart will continue to sample the rx1 pin C interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = rx1 pin is not monitored or a rising edge detected synchronous mode: unused in this mode. bit 0 abden : auto-baud detect enable bit asynchronous mode: 1 = enable baud rate measurement on the next character. requires reception of a sync field (55h); cleared in hardware upon completion. 0 = baud rate measurement is disabled or completed synchronous mode: unused in this mode. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 243 pic18f87j72 family 19.2 eusart baud rate generator (brg) the brg is a dedicated, 8-bit or 16-bit generator that supports both the asynchronous and synchronous modes of the eusart. by default, the brg operates in 8-bit mode; setting the brg16 bit (baudcon1<3>) selects 16-bit mode. the spbrgh1:spbrg1 register pair controls the period of a free-running timer. in asynchronous mode, brgh (txsta1<2>) and brg16 (baudcon1<3>) bits also control the baud rate. in synchronous mode, brgh is ignored. table 19-1 shows the formula for computa- tion of the baud rate for different eusart modes that only apply in master mode (internally generated clock). given the desired baud rate and f osc , the nearest integer value for the spbrgh1:spbrg1 registers can be calculated using the formulas in table 19-1. from this, the error in baud rate can be determined. an example calculation is shown in example 19-1. typical baud rates and error values for the various asynchronous modes are shown in table 19-2. it may be advantageous to use the high baud rate (brgh = 1 ) or the 16-bit brg to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. writing a new value to the spbrgh1:spbrg1 regis- ters causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. spbrgh1:spbrg1 values of 0000h and 0001h are not supported in synchronous mode. 19.2.1 operation in power-managed modes the device clock is used to generate the desired baud rate. when one of the power-managed modes is entered, the new clock source may be operating at a different frequency. this may require an adjustment to the value in the spbrg1 register pair. 19.2.2 sampling the data on the rx1 pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx1 pin. table 19-1: baud rate formulas example 19-1: calculating baud rate error table 19-2: registers associated with the baud rate generator configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n + 1)] 001 8-bit/asynchronous f osc /[16 (n + 1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n + 1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = dont care, n = value of spbrgh1:spbrg1 register pair name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 51 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 51 baudcon1 abdovf rcmt rxdtp txckp brg16 wue abden 53 spbrgh1 eusart baud rate generator register high byte 53 spbrg1 eusart baud rate generator register low byte 51 legend: = unimplemented, read as 0 . shaded cells are not used by the brg. for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: desired baud rate = f osc /(64 ([spbrgh1:spbrg1] + 1)) solving for spbrgh1:spbrg1: x = ((f osc /desired baud rate)/64) C 1 = ((16000000/9600)/64) C 1 = [25.042] = 25 calculated baud rate=16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate C de sired baud rate)/desired baud rate = (9615 C 9600)/9600 = 0.16% downloaded from: http:///
pic18f87j72 family ds39979a-page 244 preliminary ? 2010 microchip technology inc. table 19-3: baud rates for asynchronous modes baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0 . 3 1.2 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 9.6 8.929 -6.99 6 19.2 20.833 8.51 2 57.6 62.500 8.51 0 115.2 62.500 -45.75 0 baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0 . 3 1 . 2 2.4 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 19.2 19.231 0.16 12 57.6 62.500 8.51 3 115.2 125.000 8.51 1 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 245 pic18f87j72 family baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 19.2 19.231 0.16 12 57.6 62.500 8.51 3 115.2 125.000 8.51 1 baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 115.2 111.111 -3.55 8 table 19-3: baud rates for asynchronous modes (continued) downloaded from: http:///
pic18f87j72 family ds39979a-page 246 preliminary ? 2010 microchip technology inc. 19.2.3 auto-baud rate detect the enhanced usart module supports the automatic detection and calibration of baud rate. this feature is active only in asynchronous mode and while the wue bit is clear. the automatic baud rate measurement sequence (figure 19-1) begins whenever a start bit is received and the abden bit is set. the calculation is self-averaging. in the auto-baud rate detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rx1 signal, the rx1 signal is timing the brg. in abd mode, the internal baud rate generator is used as a counter to time the bit period of the incoming serial byte stream. once the abden bit is set, the state machine will clear the brg and look for a start bit. the auto-baud rate detect must receive a byte with the value, 55h (ascii u, which is also the lin/j2602 bus sync character), in order to calculate the proper bit rate. the measure- ment is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. after a start bit, the spbrg1 begins counting up, using the preselected clock source on the first rising edge of rx1. after eight bits on the rx1 pin or the fifth rising edge, an accumulated value totalling the proper brg period is left in the spbrgh1:spbrg1 register pair. once the 5th edge is seen (this should correspond to the stop bit), the abden bit is automatically cleared. if a rollover of the brg occurs (an overflow from ffffh to 0000h), the event is trapped by the abdovf status bit (baudcon1<7>). it is set in hardware by brg rollovers and can be set or cleared by the user in software. abd mode remains active after rollover events and the abden bit remains set (figure 19-2). while calibrating the baud rate period, the brg registers are clocked at 1/8th the preconfigured clock rate. note that the brg clock is configured by the brg16 and brgh bits. the brg16 bit (baudcon1<3>) must be set to use the spbrg1 and spbrgh1 registers as a 16-bit counter. this allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the spbrgh1 register. refer to table 19-4 for counter clock rates to the brg. while the abd sequence takes place, the eusart state machine is held in idle. the rc1if interrupt is set once the fifth rising edge on rx1 is detected. the value in the rcreg1 needs to be read to clear the rc1if interrupt. the contents of rcreg1 should be discarded. table 19-4: brg counter clock rates 19.2.3.1 abd and eusart transmission since the brg clock is reversed during abd acquisi- tion, the eusart transmitter cannot be used during abd. this means that whenever the abden bit is set, txreg1 cannot be written to. users should also ensure that abden does not become set during a transmit sequence. failing to do this may result in unpredictable eusart operation. note 1: if the wue bit is set with the abden bit, auto-baud rate detection will occur on the byte following the break character. 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible due to bit error rates. overall system timing and communication baud rates must be taken into consideration when using the auto-baud rate detection feature. brg16 brgh brg counter clock 00 f osc /512 01 f osc /128 10 f osc /128 11 f osc /32 note: during the abd sequence, spbrg1 and spbrgh1 are both used as a 16-bit counter, independent of the brg16 setting. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 247 pic18f87j72 family figure 19-1: automatic baud rate calculation figure 19-2: brg overflow sequence brg value rx1 pin abden bit rc1if bit bit 0 bit 1 (interrupt) read rcreg1 brg clock start auto-cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note: the abd sequence requires the eusart module to be configured in asynchronous mode and wue = 0 . spbrg1 xxxxh 1ch spbrgh1 xxxxh 00h start bit 0 xxxxh 0000h 0000h ffffh brg clock abden bit rx1 pin abdovf bit brg value downloaded from: http:///
pic18f87j72 family ds39979a-page 248 preliminary ? 2010 microchip technology inc. 19.3 eusart asynchronous mode the asynchronous mode of operation is selected by clearing the sync bit (txsta1<4>). in this mode, the eusart uses standard non-return-to-zero (nrz) for- mat (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip dedicated 8-bit/16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the eusart transmits and receives the lsb first. the eusarts transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the brgh and brg16 bits (txsta1<2> and baudcon1<3>). parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. when operating in asynchronous mode, the eusart module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver auto-wake-up on sync break character 12-bit break character transmit auto-baud rate detection 19.3.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 19-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg1. the txreg1 register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg1 register (if available). once the txreg1 register transfers the data to the tsr register (occurs in one t cy ), the txreg1 register is empty and the tx1if flag bit (pir1<4>) is set. this interrupt can be enabled or disabled by setting or clear- ing the interrupt enable bit, tx1ie (pie1<4>). tx1if will be set regardless of the state of tx1ie; it cannot be cleared in software. tx1if is also not cleared immedi- ately upon loading txreg1, but becomes valid in the second instruction cycle following the load instruction. polling tx1if immediately following a load of txreg1 will return invalid results. while tx1if indicates the status of the txreg1 register, another bit, trmt (txsta1<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr register is empty. no inter- rupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. to set up an asynchronous transmission: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit, sync, and setting bit, spen. 3. if interrupts are desired, set enable bit, tx1ie. 4. if 9-bit transmission is desired, set transmit bit, tx9; can be used as address/data bit. 5. enable the transmission by setting bit, txen, which will also set bit, tx1if. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit, tx9d. 7. load data to the txreg1 register (starts transmission). 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 19-3: eusart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. 2: flag bit, tx1if, is set when enable bit, txen, is set. tx1if tx1ie interrupt txen baud rate clk spbrg1 baud rate generator tx9d msb lsb data bus txreg1 register tsr register (8) 0 tx9 trmt spen tx1 pin pin buffer and control 8 ????????? spbrgh1 brg16 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 249 pic18f87j72 family figure 19-4: asynchronous transmission figure 19-5: asynchronous transmission (back to back) table 19-5: registers associated wi th asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 adif rc1if tx1if sspif tmr2if tmr1if 52 pie1 adie rc1ie tx1ie sspie tmr2ie tmr1ie 52 ipr1 adip rc1ip tx1ip sspip tmr2ip tmr1ip 52 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 51 txreg1 eusart transmit register 51 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 51 baudcon1 abdovf rcmt rxdtp txckp brg16 wue abden 53 spbrgh1 eusart baud rate generator register high byte 53 spbrg1 eusart baud rate generator register low byte 51 latg u2od u1od latg4 latg3 latg2 latg1 latg0 52 legend: = unimplemented locations read as 0 . shaded cells are not used for asynchronous transmission. word 1 word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg1 brg output (shift clock) tx1 (pin) tx1if bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy word 1 stop bit transmit shift reg. write to txreg1 brg output (shift clock) tx1 (pin) tx1if bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy start bit downloaded from: http:///
pic18f87j72 family ds39979a-page 250 preliminary ? 2010 microchip technology inc. 19.3.2 eusart asynchronous receiver the receiver block diagram is shown in figure 19-6. the data is received on the rx1 pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit, sync, and setting bit, spen. 3. if interrupts are desired, set enable bit, rc1ie. 4. if 9-bit reception is desired, set bit, rx9. 5. enable the reception by setting bit, cren. 6. flag bit, rc1if, will be set when reception is complete and an interrupt will be generated if enable bit, rc1ie, was set. 7. read the rcsta1 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg1 register. 9. if any error occurred, clear the error by clearing enable bit, cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 19.3.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rc1ip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rc1if bit will be set when reception is complete. the interrupt will be acknowledged if the rc1ie and gie bits are set. 8. read the rcsta1 register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg1 to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 19-6: eusart receive block diagram x64 baud rate clk baud rate generator rx1 pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg1 register fifo interrupt rc1if rc1ie data bus 8 ? 64 ? 16 or stop start (8) 7 1 0 rx9 ??????? spbrg1 spbrgh1 brg16 or ? 4 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 251 pic18f87j72 family figure 19-7: asynchronous reception table 19-6: registers associated with asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 adif rc1if tx1if sspif tmr2if tmr1if 52 pie1 adie rc1ie tx1ie sspie tmr2ie tmr1ie 52 ipr1 adip rc1ip tx1ip sspip tmr2ip tmr1ip 52 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 51 rcreg1 eusart receive register 51 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 51 baudcon1 abdovf rcmt rxdtp txckp brg16 wue abden 53 spbrgh1 eusart baud rate generator register high byte 51 spbrg1 eusart baud rate generator register low byte 51 legend: = unimplemented locations read as 0 . shaded cells are not used for asynchronous reception. start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx1 (pin) rcv buffer reg rcv shift reg read rcv buffer reg rcreg1 rc1if (interrupt flag) oerr bit cren bit word 1 rcreg1 word 2 rcreg1 stop bit note: this timing diagram shows three words appearing on the rx1 input. the rcreg1 (rec eive buffer register) is read after the third word causing the oerr (overrun) bit to be set. downloaded from: http:///
pic18f87j72 family ds39979a-page 252 preliminary ? 2010 microchip technology inc. 19.3.4 auto-wake-up on sync break character during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper byte reception cannot be per- formed. the auto-wake-up feature allows the controller to wake-up, due to activity on the rx1/dt1 line, while the eusart is operating in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit (baudcon<1>). once set, the typical receive sequence on rx1/dt1 is disabled and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rx1/dt1 line. (this coincides with the start of a sync break or a wake-up signal character for the lin/j2602 protocol.) following a wake-up event, the module generates an rc1if interrupt. the interrupt is generated synchro- nously to the q clocks in normal operating modes (figure 19-8) and asynchronously, if the device is in sleep mode (figure 19-9). the interrupt condition is cleared by reading the rcreg1 register. the wue bit is automatically cleared once a low-to-high transition is observed on the rx1 line following the wake-up event. at this point, the eusart module is in idle mode and returns to normal operation. this signals to the user that the sync break event is over. 19.3.4.1 special considerations using auto-wake-up since auto-wake-up functions by sensing rising edge transitions on rx1/dt1, information with any state changes before the stop bit may signal a false end-of-character (eoc and cause data or framing errors. therefore, to work properly, the initial character in the transmission must be all 0 s. this can be 00h (8 bits) for standard rs-232 devices, or 000h (12 bits) for lin/j2602 bus. oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., xt or hs mode). the sync break (or wake-up signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. 19.3.4.2 special considerations using the wue bit the timing of wue and rc1if events may cause some confusion when it comes to determining the validity of received data. as noted, setting the wue bit places the eusart in an idle mode. the wake-up event causes a receive interrupt by setting the rc1if bit. the wue bit is cleared after this when a rising edge is seen on rx1/dt1. the interrupt condition is then cleared by reading the rcreg1 register. ordinarily, the data in rcreg1 will be dummy data and should be discarded. the fact that the wue bit has been cleared (or is still set) and the rc1if flag is set should not be used as an indicator of the integrity of the data in rcreg1. users should consider implementing a parallel method in firmware to verify received data integrity. to assure that no actual data is lost, check the rcmt bit to verify that a receive operation is not in process. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode. figure 19-8: auto-wake-up bit (wue) timings during normal operation figure 19-9: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit (1) rx1/dt1 line rc1if cleared due to user read of rcreg1 note 1: the eusart remains in idle while the wue bit is set. bit set by user auto-cleared q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit (2) rx1/dt1 line rc1if cleared due to user read of rcreg1 sleep command executed note 1: if the wake-up event requires long oscillator warm-up time, the auto-clear of the wue bit can occur while th e stposc signal is still active. this sequence should not depend on the presence of q clocks. 2: the eusart remains in idle while the wue bit is set. sleep ends auto-cleared note 1 bit set by user downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 253 pic18f87j72 family 19.3.5 break character sequence the enhanced usart module has the capability of sending the special break character sequences that are required by the lin/j2602 bus standard. the break character transmit consists of a start bit, followed by twelve 0 bits and a stop bit. the frame break character is sent whenever the sendb and txen bits (txsta<3> and txsta<5>) are set while the transmit shift register is loaded with data. note that the value of data written to txreg1 will be ignored and all 0 s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin/j2602 specification). note that the data value written to the txreg1 for the break character is ignored. the write simply serves the purpose of initiating the proper sequence. the trmt bit indicates when the transmit operation is active or idle, just as it does during normal transmis- sion. see figure 19-10 for the timing of the break character sequence. 19.3.5.1 break and sync transmit sequence the following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin/j2602 bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to set up the break character. 3. load the txreg1 with a dummy character to initiate transmission (the value is ignored). 4. write 55h to txreg1 to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware. the sync character now transmits in the preconfigured mode. when the txreg1 becomes empty, as indicated by the tx1if, the next data byte can be written to txreg1. 19.3.6 receiving a break character the enhanced usart module can receive a break character in two ways. the first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. this allows for the stop bit transition to be at the correct sampling location (13 bits for break versus start bit and 8 data bits for typical data). the second method uses the auto-wake-up feature described in section 19.3.4 auto-wake-up on sync break character . by enabling this feature, the eusart will sample the next two transitions on rx1/dt1, cause an rc1if interrupt and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud rate detect feature. for both methods, the user can set the abd bit once the tx1if interrupt is observed. figure 19-10: send break character sequence write to txreg1 brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break tx1if bit (transmit buffer reg. empty flag) tx1 (pin) trmt bit (transmit shift reg. empty flag) sendb (transmit shift reg. empty flag) sendb sampled here auto-cleared dummy write downloaded from: http:///
pic18f87j72 family ds39979a-page 254 preliminary ? 2010 microchip technology inc. 19.4 eusart synchronous master mode the synchronous master mode is entered by setting the csrc bit (txsta<7>). in this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit, sync (txsta<4>). in addition, enable bit, spen (rcsta1<7>), is set in order to configure the tx1 and rx1 pins to ck1 (clock) and dt1 (data) lines, respectively. the master mode indicates that the processor trans- mits the master clock on the ck1 line. clock polarity is selected with the txckp bit (baudcon<4>). setting txckp sets the idle state on ck1 as high, while clear- ing the bit sets the idle state as low. this option is provided to support microwire devices with this module. 19.4.1 eusart synchronous master transmission the eusart transmitter block diagram is shown in figure 19-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg1. the txreg1 register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg1 (if available). once the txreg1 register transfers the data to the tsr register (occurs in one t cycle ), the txreg1 is empty and the tx1if flag bit (pir1<4>) is set. the interrupt can be enabled or disabled by setting or clear- ing the interrupt enable bit, tx1ie (pie1<4>). tx1if is set regardless of the state of enable bit, tx1ie; it can- not be cleared in software. it will reset only when new data is loaded into the txreg1 register. while flag bit, tx1if, indicates the status of the txreg1 register, another bit, trmt (txsta<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to deter- mine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits, sync, spen and csrc. 3. if interrupts are desired, set enable bit, tx1ie. 4. if 9-bit transmission is desired, set bit, tx9. 5. enable the transmission by setting bit, txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit, tx9d. 7. start transmission by loading data to the txreg1 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 19-11: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx1/dt1/seg28 write to txreg1 reg tx1if bit (interrupt flag) txen bit 1 1 word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrg1 = 0 ; continuous transmission of two 8-bit words. pin rc6/tx1/ck1/seg27 pin (txckp = 0 ) (txckp = 1 ) rc6/tx1/ck1/seg27 pin downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 255 pic18f87j72 family figure 19-12: synchronous transmission (through txen) table 19-7: registers associated with synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 adif rc1if tx1if sspif tmr2if tmr1if 52 pie1 adie rc1ie tx1ie sspie tmr2ie tmr1ie 52 ipr1 adip rc1ip tx1ip sspip tmr2ip tmr1ip 52 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 51 txreg1 eusart transmit register 51 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 51 baudcon1 abdovf rcmt rxdtp txckp brg16 wue abden 53 spbrgh1 eusart baud rate gene rator register high byte 53 spbrg1 eusart baud rate generator register low byte 51 latg u2od u1od latg4 latg3 latg2 latg1 latg0 52 legend: = unimplemented, read as 0 . shaded cells are not used for synchronous master transmission. rc7/rx1/dt1/seg28 pin rc6/tx1/ck1/seg27 pin write to txreg1 reg tx1if bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit downloaded from: http:///
pic18f87j72 family ds39979a-page 256 preliminary ? 2010 microchip technology inc. 19.4.2 eusart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the single receive enable bit, sren (rcsta1<5>), or the continuous receive enable bit, cren (rcsta1<4>). data is sampled on the rx1 pin on the falling edge of the clock. if enable bit, sren, is set, only a single word is received. if enable bit, cren, is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits, sync, spen and csrc. 3. ensure bits, cren and sren, are clear. 4. if interrupts are desired, set enable bit, rc1ie. 5. if 9-bit reception is desired, set bit, rx9. 6. if a single reception is required, set bit, sren. for continuous reception, set bit, cren. 7. interrupt flag bit, rc1if, will be set when recep- tion is complete and an interrupt will be generated if the enable bit, rc1ie, was set. 8. read the rcsta1 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg1 register. 10. if any error occurred, clear the error by clearing bit, cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 19-13: synchronous reception (master mode, sren) table 19-8: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 adif rc1if tx1if sspif tmr2if tmr1if 52 pie1 adie rc1ie tx1ie sspie tmr2ie tmr1ie 52 ipr1 adip rc1ip tx1ip sspip tmr2ip tmr1ip 52 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 51 rcreg1 eusart receive register 51 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 51 baudcon1 abdovf rcmt rxdtp txckp brg16 wue abden 53 spbrgh1 eusart baud rate generator register high byte 53 spbrg1 eusart baud rate generator register low byte 51 legend: = unimplemented, read as 0 . shaded cells are not used for synchronous master reception. cren bit rc7/rx1/dt1/ rc6/tx1/ck1/seg27 write to sren bit sren bit rc1if bit (interrupt) read rcreg1 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit, sren = 1 , and bit, brgh = 0 . rc6/tx1/ck1/seg27 seg28 pin pin (txckp = 0 ) pin (txckp = 1 ) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 257 pic18f87j72 family 19.5 eusart synchronous slave mode synchronous slave mode is entered by clearing bit, csrc (txsta<7>). this mode differs from the synchronous master mode in that the shift clock is supplied externally at the ck1 pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any low-power mode. 19.5.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of sleep mode. if two words are written to the txreg1 and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in the txreg1 register. c) flag bit, tx1if, will not be set. d) when the first word has been shifted out of tsr, the txreg1 register will transfer the second word to the tsr and flag bit, tx1if, will now be set. e) if enable bit, tx1ie, is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits, sync and spen, and clearing bit, csrc. 2. clear bits, cren and sren. 3. if interrupts are desired, set enable bit, tx1ie. 4. if 9-bit transmission is desired, set bit, tx9. 5. enable the transmission by setting enable bit, txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit, tx9d. 7. start transmission by loading data to the txreg1 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 19-9: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 adif rc1if tx1if sspif tmr2if tmr1if 52 pie1 adie rc1ie tx1ie sspie tmr2ie tmr1ie 52 ipr1 adip rc1ip tx1ip sspip tmr2ip tmr1ip 52 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 51 txreg1 eusart transmit register 51 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 51 baudcon1 abdovf rcmt rxdtp txckp brg16 wue abden 53 spbrgh1 eusart baud rate generator register high byte 53 spbrg1 eusart baud rate generator register low byte 51 latg u2od u1od latg4 latg3 latg2 latg1 latg0 52 legend: = unimplemented, read as 0 . shaded cells are not used for synchronous slave transmission. downloaded from: http:///
pic18f87j72 family ds39979a-page 258 preliminary ? 2010 microchip technology inc. 19.5.2 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of sleep or any idle mode, and bit, sren, which is a dont care in slave mode. if receive is enabled by setting the cren bit prior to entering sleep or any idle mode, then a word may be received while in this low-power mode. once the word is received, the rsr register will transfer the data to the rcreg1 register; if the rc1ie enable bit is set, the interrupt generated will wake the chip from the low-power mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits, sync and spen, and clearing bit, csrc. 2. if interrupts are desired, set enable bit, rc1ie. 3. if 9-bit reception is desired, set bit, rx9. 4. to enable reception, set enable bit, cren. 5. flag bit, rc1if, will be set when reception is complete. an interrupt will be generated if enable bit, rc1ie, was set. 6. read the rcsta1 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg1 register. 8. if any error occurred, clear the error by clearing bit, cren. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 19-10: registers associated wi th synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 adif rc1if tx1if sspif tmr2if tmr1if 52 pie1 adie rc1ie tx1ie sspie tmr2ie tmr1ie 52 ipr1 adip rc1ip tx1ip sspip tmr2ip tmr1ip 52 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 51 rcreg1 eusart receive register 51 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 51 baudcon1 abdovf rcmt rxdtp txckp brg16 wue abden 53 spbrgh1 eusart baud rate generator register high byte 53 spbrg1 eusart baud rate generator register low byte 51 legend: = unimplemented, read as 0 . shaded cells are not used for synchronous slave reception. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 259 pic18f87j72 family 20.0 addressable universal synchronous asynchronous receiver transmitter (ausart) the addressable universal synchronous asynchro- nous receiver transmitter (ausart) module is very similar in function to the enhanced usart module, discussed in the previous chapter. it is provided as an additional channel for serial communication with external devices, for those situations that do not require auto-baud detection or lin/j2602 bus support. the ausart can be configured in the following modes: asynchronous (full-duplex) synchronous C master (half-duplex) synchronous C slave (half-duplex) the pins of the ausart module are multiplexed with the functions of portg (rg1/tx2/ck2 and rg2/rx2/dt2/v lcap 1, respectively). in order to configure these pins as an ausart: pen bit (rcsta2<7>) must be set (= 1 ) txen bit (txsta2<5>) must also be set (= 1 ) to configure tx2/ck2 to transmit trisg<2> bit must be set (= 1 ) trisg<1> bit must be cleared (= 0 ) for asynchronous and synchronous master modes trisg<1> bit must be set (= 1 ) for synchronous slave mode the driver for the tx2 output pin can also be optionally configured as an open-drain output. this feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. the open-drain output option is controlled by the u2od bit (latg<7>). setting the bit configures the pin for open-drain operation. 20.1 control registers the operation of the addressable usart module is controlled through two registers: txsta2 and rxsta2. these are detailed in register 20-1 and register 20-2, respectively. note: the ausart control will automatically reconfigure the pin from input to output as needed. downloaded from: http:///
pic18f87j72 family ds39979a-page 260 preliminary ? 2010 microchip technology inc. register 20-1: txsta2: ausart transm it status and control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 csrc: clock source select bit asynchronous mode: dont care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: ausart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as 0 bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 261 pic18f87j72 family register 20-2: rcsta2: ausart receive stat us and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx2/dt2 and tx2/ck2 pins as serial port pins; txen must also be set to configure tx2/ck2 to transmit) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : dont care. synchronous mode C master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode C slave: dont care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit, cren, is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enables interrupt and loads the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 9-bit (rx9 = 0 ) : dont care. bit 2 ferr: framing error bit 1 = framing error (can be cleared by reading rcreg2 register and receiving next v alid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be an address/data bit or a parity bit and must be calculated by user firmware. downloaded from: http:///
pic18f87j72 family ds39979a-page 262 preliminary ? 2010 microchip technology inc. 20.2 ausart baud rate generator (brg) the brg is a dedicated, 8-bit generator that supports both the asynchronous and synchronous modes of the ausart. the spbrg2 register controls the period of a free-running timer. in asynchronous mode, the brgh (txsta<2>) bit also controls the baud rate. in synchronous mode, brgh is ignored. table 20-1 shows the formula for computation of the baud rate for different ausart modes, which only apply in master mode (internally generated clock). given the desired baud rate and f osc , the nearest integer value for the spbrg2 register can be calculated using the formulas in table 20-1. from this, the error in baud rate can be determined. an example calculation is shown in example 20-1. typical baud rates and error values for the various asynchronous modes are shown in table 20-2. it may be advantageous to use the high baud rate (brgh = 1 ) to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. writing a new value to the spbrg2 register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 20.2.1 operation in power-managed modes the device clock is used to generate the desired baud rate. when one of the power-managed modes is entered, the new clock source may be operating at a different frequency. this may require an adjustment to the value in the spbrg2 register. 20.2.2 sampling the data on the rx2 pin is sampled three times by a majority detect circuit to determine if a high or a low level is present on the rx2 pin. table 20-1: baud rate formulas example 20-1: calculating baud rate error table 20-2: registers associated with the baud rate generator configuration bits brg/ausart mode baud rate formula sync brgh 00 asynchronous f osc /[64 (n + 1)] 01 asynchronous f osc /[16 (n + 1)] 1x synchronous f osc /[4 (n + 1)] legend: x = dont care, n = value of spbrg2 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page txsta2 csrc tx9 txen sync b r g h trmt tx9d 54 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 54 spbrg2 ausart baud rate generator register 54 legend: shaded cells are not used by the brg. for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, brgh = 0 : desired baud rate = f osc /(64 ([spbrg2] + 1)) solving for spbrg2: x = ((f osc /desired baud rate)/64) C 1 = ((16000000/9600)/64) C 1 = [25.042] = 25 calculated baud rate=16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate C desi red baud rate)/de sired baud rate = (9615 C 9600)/9600 = 0.16% downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 263 pic18f87j72 family table 20-3: baud rates for asynchronous modes brgh = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz baud rate (k) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0 . 3 1.2 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 brgh = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz baud rate (k) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 9.6 8.929 -6.99 6 19.2 20.833 8.51 2 57.6 62.500 8.51 0 115.2 62.500 -45.75 0 baud rate (k) brgh = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0 . 3 1 . 2 2.4 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 baud rate (k) brgh = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 19.2 19.231 0.16 12 57.6 62.500 8.51 3 115.2 125.000 8.51 1 downloaded from: http:///
pic18f87j72 family ds39979a-page 264 preliminary ? 2010 microchip technology inc. 20.3 ausart asynchronous mode the asynchronous mode of operation is selected by clearing the sync bit (txsta2<4>). in this mode, the ausart uses standard non-return-to-zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the ausart transmits and receives the lsb first. the ausarts transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the brgh bit (txsta2<2>). parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. when operating in asynchronous mode, the ausart module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 20.3.1 ausart asynchronous transmitter the ausart transmitter block diagram is shown in figure 20-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg2. the txreg2 register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg2 register (if available). once the txreg2 register transfers the data to the tsr register (occurs in one t cy ), the txreg2 register is empty and the tx2if flag bit (pir3<4>) is set. this interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, tx2ie (pie3<4>). tx2if will be set regardless of the state of tx2ie; it cannot be cleared in software. tx2if is also not cleared immediately upon loading txreg2, but becomes valid in the second instruction cycle following the load instruction. polling tx2if immediately following a load of txreg2 will return invalid results. while tx2if indicates the status of the txreg2 register, another bit, trmt (txsta2<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr register is empty. no inter- rupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsr register is empty. to set up an asynchronous transmission: 1. initialize the spbrg2 register for the appropriate baud rate. set or clear the brgh bit, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit, sync, and setting bit, spen. 3. if interrupts are desired, set enable bit, tx2ie. 4. if 9-bit transmission is desired, set transmit bit, tx9. can be used as address/data bit. 5. enable the transmission by setting bit, txen, which will also set bit, tx2if. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit, tx9d. 7. load data to the txreg2 register (starts transmission). 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 20-1: ausart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. 2: flag bit, tx2if, is set when enable bit, txen, is set. tx2if tx2ie interrupt txen baud rate clk spbrg2 baud rate generator tx9d msb lsb data bus txreg2 register tsr register (8) 0 tx9 trmt spen tx2 pin pin buffer and control 8 ????????? downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 265 pic18f87j72 family figure 20-2: asynchronous transmission figure 20-3: asynchronous transmission (back to back) table 20-4: registers associated wi th asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir3 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif 52 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie 52 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip 52 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 54 txreg2 ausart transmit register 54 txsta2 csrc tx9 txen sync brgh trmt tx9d 54 spbrg2 ausart baud rate generator register 54 latg u2od u1od latg4 latg3 latg2 latg1 latg0 52 legend: = unimplemented locations read as 0 . shaded cells are not used for asynchronous transmission. word 1 word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg2 brg output (shift clock) tx2 (pin) tx2if bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy word 1 stop bit transmit shift reg. write to txreg2 brg output (shift clock) tx2 (pin) tx2if bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy start bit downloaded from: http:///
pic18f87j72 family ds39979a-page 266 preliminary ? 2010 microchip technology inc. 20.3.2 ausart asynchronous receiver the receiver block diagram is shown in figure 20-4. the data is received on the rx2 pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrg2 register for the appropriate baud rate. set or clear the brgh bit, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit, sync, and setting bit, spen. 3. if interrupts are desired, set enable bit, rc2ie. 4. if 9-bit reception is desired, set bit, rx9. 5. enable the reception by setting bit, cren. 6. flag bit, rc2if, will be set when reception is complete and an interrupt will be generated if enable bit, rc2ie, was set. 7. read the rcsta2 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg2 register. 9. if any error occurred, clear the error by clearing enable bit, cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 20.3.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrg2 register for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rc2ip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rc2if bit will be set when reception is complete. the interrupt will be acknowledged if the rc2ie and gie bits are set. 8. read the rcsta2 register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg2 to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 20-4: ausart receive block diagram x64 baud rate clk baud rate generator rx2 pin pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg2 register fifo interrupt rc2if rc2ie data bus 8 ? 64 ? 16 or stop start (8) 7 1 0 rx9 ??????? spbrg2 or ? 4 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 267 pic18f87j72 family figure 20-5: asynchronous reception table 20-5: registers associated with asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir3 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif 52 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie 52 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip 52 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 54 rcreg2 ausart receive register 54 txsta2 csrc tx9 txen sync b r g h trmt tx9d 54 spbrg2 ausart baud rate generator register 54 legend: = unimplemented locations read as 0 . shaded cells are not used for asynchronous reception. start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx2 (pin) rcv buffer reg rcv shift reg read rcv buffer reg rcreg2 rc2if (interrupt flag) oerr bit cren word 1 rcreg2 word 2 rcreg2 stop bit note: this timing diagram shows three words appearing on the rx2 input. the rcreg2 (receive buffer register) is read after the third word causing the oerr (overrun) bit to be set. downloaded from: http:///
pic18f87j72 family ds39979a-page 268 preliminary ? 2010 microchip technology inc. 20.4 ausart synchronous master mode the synchronous master mode is entered by setting the csrc bit (txsta2<7>). in this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit, sync (txsta2<4>). in addition, enable bit, spen (rcsta2<7>), is set in order to configure the tx2 and rx2 pins to ck2 (clock) and dt2 (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck2 line. 20.4.1 ausart synchronous master transmission the ausart transmitter block diagram is shown in figure 20-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register: txreg2. the txreg2 register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg2 (if available). once the txreg2 register transfers the data to the tsr register (occurs in one t cycle ), the txreg2 is empty and the tx2if flag bit (pir3<4>) is set. the interrupt can be enabled or disabled by setting or clear- ing the interrupt enable bit, tx2ie (pie3<4>). tx2if is set regardless of the state of enable bit, tx2ie; it cannot be cleared in software. it will reset only when new data is loaded into the txreg2 register. while flag bit, tx2if, indicates the status of the txreg2 register, another bit, trmt (txsta2<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to deter- mine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrg2 register for the appropriate baud rate. 2. enable the synchronous master serial port by setting bits, sync, spen and csrc. 3. if interrupts are desired, set enable bit, tx2ie. 4. if 9-bit transmission is desired, set bit, tx9. 5. enable the transmission by setting bit, txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit, tx9d. 7. start transmission by loading data to the txreg2 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 20-6: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rx2/dt2 pin tx2/ck2 pin write to txreg2 reg tx2if bit (interrupt flag) txen bit 1 1 word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrg2 = 0 ; continuous transmission of two 8-bit words. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 269 pic18f87j72 family figure 20-7: synchronous transmission (through txen) table 20-6: registers associated with synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir3 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif 52 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie 52 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip 52 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 54 txreg2 ausart transmit register 54 txsta2 csrc tx9 txen sync brgh trmt tx9d 54 spbrg2 ausart baud rate generator register 54 latg u2od u1od latg4 latg3 latg2 latg1 latg0 52 legend: = unimplemented, read as 0 . shaded cells are not used for synchronous master transmission. rx2/dt2 pin tx2/ck2 pin write to txreg2 reg tx2if bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit downloaded from: http:///
pic18f87j72 family ds39979a-page 270 preliminary ? 2010 microchip technology inc. 20.4.2 ausart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the single receive enable bit, sren (rcsta2<5>), or the continuous receive enable bit, cren (rcsta2<4>). data is sampled on the rx2 pin on the falling edge of the clock. if enable bit, sren, is set, only a single word is received. if enable bit, cren, is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrg2 register for the appropriate baud rate. 2. enable the synchronous master serial port by setting bits, sync, spen and csrc. 3. ensure bits, cren and sren, are clear. 4. if interrupts are desired, set enable bit, rc2ie. 5. if 9-bit reception is desired, set bit, rx9. 6. if a single reception is required, set bit, sren. for continuous reception, set bit, cren. 7. interrupt flag bit, rc2if, will be set when recep- tion is complete and an interrupt will be generated if the enable bit, rc2ie, was set. 8. read the rcsta2 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg2 register. 10. if any error occurred, clear the error by clearing bit, cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 20-8: synchronous reception (master mode, sren) table 20-7: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir3 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif 52 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie 52 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip 52 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 54 rcreg2 ausart receive register 54 txsta2 csrc tx9 txen sync brgh trmt tx9d 54 spbrg2 ausart baud rate generator register 54 legend: = unimplemented, read as 0 . shaded cells are not used for synchronous master reception. cren bit rx2/dt2 pin tx2/ck2 pin write to bit sren sren bit rc2if bit (interrupt) read rcreg2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 271 pic18f87j72 family 20.5 ausart synchronous slave mode synchronous slave mode is entered by clearing bit, csrc (txsta2<7>). this mode differs from the synchronous master mode in that the shift clock is supplied externally at the ck2 pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any low-power mode. 20.5.1 ausart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg2 and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in the txreg2 register. c) flag bit, tx2if, will not be set. d) when the first word has been shifted out of tsr, the txreg2 register will transfer the second word to the tsr and flag bit, tx2if, will now be set. e) if enable bit, tx2ie, is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits, sync and spen, and clearing bit, csrc. 2. clear bits, cren and sren. 3. if interrupts are desired, set enable bit, tx2ie. 4. if 9-bit transmission is desired, set bit, tx9. 5. enable the transmission by setting enable bit, txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit, tx9d. 7. start transmission by loading data to the txreg2 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 20-8: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir3 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif 52 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie 52 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip 52 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 54 txreg2 ausart transmit register 54 txsta2 csrc tx9 txen sync brgh trmt tx9d 54 spbrg2 ausart baud rate generator register 54 latg u2od u1od latg4 latg3 latg2 latg1 latg0 52 legend: = unimplemented, read as 0 . shaded cells are not used for synchronous slave transmission. downloaded from: http:///
pic18f87j72 family ds39979a-page 272 preliminary ? 2010 microchip technology inc. 20.5.2 ausart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of sleep or any idle mode, and bit sren, which is a dont care in slave mode. if receive is enabled by setting the cren bit prior to entering sleep, or any idle mode, then a word may be received while in this low-power mode. once the word is received, the rsr register will transfer the data to the rcreg2 register; if the rc2ie enable bit is set, the interrupt generated will wake the chip from low-power mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits, sync and spen, and clearing bit, csrc. 2. if interrupts are desired, set enable bit, rc2ie. 3. if 9-bit reception is desired, set bit, rx9. 4. to enable reception, set enable bit, cren. 5. flag bit, rc2if, will be set when reception is complete. an interrupt will be generated if enable bit, rc2ie, was set. 6. read the rcsta2 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg2 register. 8. if any error occurred, clear the error by clearing bit, cren. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 20-9: registers associated wi th synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir3 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif 52 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie 52 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip 52 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 54 rcreg2 ausart receive register 54 txsta2 csrc tx9 txen sync brgh trmt tx9d 54 spbrg2 ausart baud rate generator register 54 legend: = unimplemented, read as 0 . shaded cells are not used for synchronous slave reception. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 273 pic18f87j72 family 21.0 12-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 12 inputs for all pic18f87j72 family devices. this module allows conversion of an analog input signal to a corresponding 12-bit digital number. the module has these registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a/d control register 2 (adcon2) the adcon0 register, shown in register 21-1, controls the operation of the a/d module. the adcon1 register, shown in register 21-2, configures the functions of the port pins. the adcon2 register, shown in register 21-3, configures the a/d clock source, programmed acquisition time and justification. register 21-1: adcon0: a/ d control register 0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcal chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 adcal: a/d calibration bit 1 = calibration is performed on the next a/d conversion 0 = normal a/d converter operation (no calibration is performed) bit 6 unimplemented: read as 0 bit 5-2 chs<3:0>: analog channel select bits 0000 = channel 00 (an0) 0001 = channel 01 (an1) 0010 = channel 02 (an2) 0011 = channel 03 (an3) 0100 = channel 04 (an4) 0101 = channel 05 (an5) 0110 = channel 06 (an6) 0111 = channel 07 (an7) 1000 = channel 08 (an8) 1001 = channel 09 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 11xx = unused bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion is in progress 0 = a/d is idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled downloaded from: http:///
pic18f87j72 family ds39979a-page 274 preliminary ? 2010 microchip technology inc. register 21-2: adcon1: a/ d control register 1 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trigsel vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 trigsel: special trigger select bit 1 = selects the special trigger from the ctmu 0 = selects the special trigger from the ccp2 bit 6 unimplemented: read as 0 bit 5 vcfg1: voltage reference configuration bit (v ref - source) 1 =v ref - (an2) 0 =av ss bit 4 vcfg0: voltage reference configuration bit (v ref + source) 1 =v ref + (an3) 0 =av dd bit 3-0 pcfg<3:0>: a/d port configuration control bits: a = analog input d = digital i/o pcfg<3:0> an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 aaaaaaaaaaaa 0001 aaaaaaaaaaaa 0010 aaaaaaaaaaaa 0011 aaaaaaaaaaaa 0100 daaaaaaaaaaa 0101 ddaaaaaaaaaa 0110 dddaaaaaaaaa 0111 ddddaaaaaaaa 1000 dddddaaaaaaa 1001 ddddddaaaaaa 1010 dddddddaaaaa 1011 ddddddddaaaa 1100 dddddddddaaa 1101 ddddddddddaa 1110 ddddddddddda 1111 dddddddddddd downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 275 pic18f87j72 family register 21-3: adcon2: a/ d control register 2 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as 0 bit 5-3 acqt<2:0>: a/d acquisition time select bits 111 = 20 t ad 110 = 16 t ad 101 = 12 t ad 100 = 8 t ad 011 = 6 t ad 010 = 4 t ad 001 = 2 t ad 000 = 0 t ad (1) bit 2-0 adcs<2:0>: a/d conversion clock select bits 111 = f rc (clock derived from a/d rc oscillator) (1) 110 = f osc /64 101 = f osc /16 100 = f osc /4 011 = f rc (clock derived from a/d rc oscillator) (1) 010 = f osc /32 001 = f osc /8 000 = f osc /2 note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion. downloaded from: http:///
pic18f87j72 family ds39979a-page 276 preliminary ? 2010 microchip technology inc. the analog reference voltage is software selectable to either the devices positive and negative supply voltage (av dd and av ss ) or the voltage level on the ra3/an3/ v ref + and ra2/an2/v ref - pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d conversion clock must be derived from the a/ds internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. each port pin associated with the a/d converter can be configured as an analog input or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is complete, the result is loaded into the adresh:adresl register pair, the go/done bit (adcon0<1>) is cleared and the a/d interrupt flag bit, adif, is set. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. the value in the adresh:adresl register pair is not modified for a power-on reset. these registers will contain unknown data after a power-on reset. the block diagram of the a/d module is shown in figure 21-1. figure 21-1: a/d block diagram (1,2) (input voltage) v ain v ref + reference voltage av dd vcfg<1:0> chs<3:0> an7an6 an4 an3 an2 an1 an0 01110110 0100 0011 0010 0001 0000 12-bit a/d v ref - av ss converter an11 an10 an9 an8 10111010 1001 1000 note 1: channels, an15 through an12, are not available on pic18f87j62 devices. 2: i/o pins have diode protection to v dd and v ss . an5 0101 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 277 pic18f87j72 family after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as inputs. to determine acquisition time, see section 21.1 a/d acquisition requirements . after this acquisition time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to do an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d acquisition time (adcon2) select a/d conversion clock (adcon2) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time (if required). 4. start conversion: set go/done bit (adcon0<1>) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear adif bit, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. figure 21-2: analog input model v ain c pin r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic ?? 1k sampling switch ss r ss c hold = 25 pf v ss sampling switch 123 4 (k ? ) v dd 100 na legend: c pin v t i leakage r ic ssc hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss downloaded from: http:///
pic18f87j72 family ds39979a-page 278 preliminary ? 2010 microchip technology inc. 21.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 21-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor, c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k ? . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 21-1 may be used. this equation assumes that 1/2 lsb error is used (1,024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. equation 21-3 shows the calculation of the minimum required acquisition time, t acq . this calculation is based on the following application system assumptions: equation 21-1: acquisition time equation 21-2: a/d minimum charging time equation 21-3: calculating the minimum required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. c hold =25 pf rs = 2.5 k ?? conversion error ? 1/2 lsb v dd =3v ? rss = 2 k ? temperature = 85 ? c (system max.) t acq = amplifier settling time + holding capacitor charging time + temperature coeffici ent =t amp + t c + t coff v hold = (v ref C (v ref /2048)) (1 C e (-t c /c hold (r ic + r ss + r s )) ) or t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) t acq =t amp + t c + t coff t amp =0.2 ? s t coff = (temp C 25 ? c)(0.02 ? s/ ? c) (85 ? c C 25 ? c)(0.02 ? s/ ? c) 1.2 ? s temperature coefficient is only required for temperatures > 25 ? c. below 25 ? c, t coff = 0 ms. t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) ? s -(25 pf) (1 k ? + 2 k ? + 2.5 k ? ) ln(0.0004883) ? s 1.05 ? s t acq =0.2 ? s + 1 ? s + 1.2 ? s 2.4 ? s downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 279 pic18f87j72 family 21.2 selecting and configuring automatic acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensur- ing the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this occurs when the acqt<2:0> bits (adcon2<5:3>) remain in their reset state ( 000 ) and is compatible with devices that do not offer programmable acquisition times. if desired, the acqt bits can be set to select a programmable acquisition time for the a/d module. when the go/done bit is set, the a/d module continues to sample the input for the selected acquisition time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 21.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 11 t ad per 12-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : 2 t osc 4 t osc 8 t osc 16 t osc 32 t osc 64 t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible but greater than the minimum t ad . table 21-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 21-1: t ad vs. device operating frequencies 21.4 configuring analog port pins the adcon1, trisa, trisf and trish registers control the operation of the a/d port pins. the port pins needed as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs<3:0> bits and the tris bits. ad clock source (t ad )m a x i m u m device frequency operation adcs<2:0> 2 t osc 000 2.86 mhz 4 t osc 100 5.71 mhz 8 t osc 001 11.43 mhz 16 t osc 101 22.86 mhz 32 t osc 010 40.0 mhz 64 t osc 110 40.0 mhz rc (2) x11 1.00 mhz (1) note 1: the rc source has a typical t ad time of 4 ? s. 2: for device frequencies above 1 mhz, the device must be in sleep mode for the entire conversion or the a/d accuracy may be out of specification. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an analog input. analog levels on a digitally configured input will be accurately converted. 2: analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the devices specification limits. downloaded from: http:///
pic18f87j72 family ds39979a-page 280 preliminary ? 2010 microchip technology inc. 21.5 a/d conversions figure 21-1 shows the operation of the a/d converter after the go/done bit has been set and the acqt<2:0> bits are cleared. a conversion is started after the following instruction to allow entry into sleep mode before the conversion begins. figure 21-2 shows the operation of the a/d converter after the go/done bit has been set. the acqt<2:0> bits are set to 010 and a 4 t ad acquisition time is selected before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/ d result register pair will not be updated with the partially completed a/d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. 21.6 use of the ccp2 trigger an a/d conversion can be started by the special event trigger of the ccp2 module. this requires that the ccp2m<3:0> bits (ccp2con<3:0>) be programmed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d acquisition and conversion, and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving adresh:adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user or an appropriate t acq time is selected before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the special event trigger will be ignored by the a/d module, but will still reset the timer1 (or timer3) counter. figure 21-1: a/d conversion t ad cycles (acqt<2:0> = 000 , t acq = 0 ) figure 21-2: a/d conversion t ad cycles (acqt<2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy C t ad adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input conversion starts b2 b11 b8 b7 b6 b5 b4 b3 b10 b9 on the following cycle: discharge t ad 13 t ad 12 b0 b1 t ad 1 (typically 200 ns) 1 2 3 4 5 6 7 8 13 set go/done bit (holding capacitor is disconnected) 9 12 conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b11 b8 b7 b6 b5 b4 b1 b10 b9 adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input on the following cycle: t ad 1 discharge 10 11 b3 b2 (typically 200 ns) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 281 pic18f87j72 family 21.7 a/d converter calibration the a/d converter in the pic18f87j72 family of devices includes a self-calibration feature which compensates for any offset generated within the module. the calibration process is automated and is initiated by setting the adcal bit (adcon0<7>). the next time the go/done bit is set, the module will per- form a dummy conversion (which means it is reading none of the input channels) and store the resulting value internally to compensate for the offset. thus, subsequent offsets will be compensated. the calibration process assumes that the device is in a relatively steady-state operating condition. if a/d calibration is used, it should be performed after each device reset or if there are other major changes in operating conditions. 21.8 operation in power-managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power-managed mode. if the a/d is expected to operate while the device is in a power-managed mode, the acqt<2:0> and adcs<2:0> bits in adcon2 should be updated in accordance with the power-managed mode clock that will be used. after the power-managed mode is entered (either of the power-managed run modes), an a/d acquisition or conversion may be started. once an acquisition or conversion is started, the device should continue to be clocked by the same power-managed mode clock source until the conversion has been completed. if desired, the device may be placed into the corresponding power-managed idle mode during the conversion. if the power-managed mode clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in sleep mode requires the a/d rc clock to be selected. if bits, acqt<2:0>, are set to 000 and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. the idlen and scsx bits in the osccon register must have already been cleared prior to starting the conversion. table 21-2: summary of a/d registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir1 a d i f rc1if tx1if sspif tmr2if tmr1if 52 pie1 a d i e rc1ie tx1ie sspie tmr2ie tmr1ie 52 ipr1 a d i p rc1ip tx1ip sspip tmr2ip tmr1ip 52 pir3 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif 52 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie 52 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip 52 adresh a/d result register high byte 51 adresl a/d result register low byte 51 adcon0 adcal chs3 chs2 chs1 chs0 go/done adon 51 adcon1 trigsel vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 51 adcon2 adfm acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 51 ccp2con dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 53 porta ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 52 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 52 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 5 2 trisf trisf5 trisf4 trisf5 t risf4 trisf3 trisf2 trisf1 5 2 legend: = unimplemented, read as 0 . shaded cells are not used for a/d conversion. note 1: ra<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as 0 . downloaded from: http:///
pic18f87j72 family ds39979a-page 282 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 283 pic18f87j72 family 22.0 dual-channel, 24-bit analog front end (afe) the dual-channel, 24-bit analog front end (afe) is an integrated, high-performance analog subsystem that has been tailored for energy metering and power measurement applications. the afe contains two synchronous sampling delta-sigma analog-to-digital converters ( ??? adc), two pgas, a phase delay compensation block, an internal voltage reference and a dedicated, high-speed 20 mhz spi compatible serial interface. a functional block diagram of the afe is shown in figure 22-1. the a/d converters contain a proprietary dithering algorithm for reduced idle tones and improved thd. each converter is preceded by a pga, allowing for weak signal amplification and true differential voltage inputs to the converters. this allows the afe to inter- face with a large variety of voltage and current sensors including shunts, current transformers, rogowski coils and hall effect sensors. afe data and control functions are accessed through a dedicated register map. the map contains 24-bit wide data words for each adc (readable as 8-bit registers), as well as five writable control registers to program amplifier gain, oversampling, phase, resolution, dither- ing, shutdown, reset and communication features. communication is largely simplified with various continuous read modes that can be accessed through the serial interface and with a separate data ready pin that can directly be connected to a microcontrollers irq input. because of the complexity of and comprehensive options available on the afe, a detailed explanation of all of its functional elements is not provided in this chapter. these are described in appendix b: dual-channel, 24-bit afe reference . this chapter explains the important points of configuring and using the afe in a pic18f8xj72 based application. direct links to relevant information in the afe reference are provided throughout the chapter for the readers convenience. figure 22-1: dual-channel analog front end functional diagram ch0+ ch0- ch1+ ch1- sdoa sdia scka dual-ds adc analog digital sinc 3 - + pga mclk clkia dr areset digital spi interface clock generation sinc 3 - + pga modulator amclk dmclk/drclk dmclk phase shifter phase <7:0> osr<1:0> pre<1:0> data_ch0<23:0> data_ch1<23:0> sdn<1:0>, reset<1:0>, gain<7:0> csa refin+/out+ refin - sav dd sav ss sv ss sv dd por sv dd monitoring por modulator v ref + v ref -/ vrefext voltage reference v ref + - d-s d-s f downloaded from: http:///
pic18f87j72 family ds39979a-page 284 preliminary ? 2010 microchip technology inc. 22.1 functional overview while it is convenient to think of the dual-channel afe as a high-precision adc, there are actually many more components involved. the main components are described below. the dual-channel afe reference provides more in-depth information on each. 22.1.1 delta-sigma adc architecture each delta-sigma adc is an oversampling converter that incorporates a built-in modulator which is digitizing the quantity of charge integrated by the modulator loop. the quantizer is the block that is performing the analog-to-digital conversion. the quantizer is typically 1-bit, or a simple comparator, which helps to maintain the linearity performance of the adc (the dac structure is, in this case, inherently linear). multi-bit quantizers help to lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the osr which leads to better snr figures. however, typically, the linearity of such architectures is more difficult to achieve since the dac is no more simple to realize and its linearity limits the thd of such adcs. the 5-level quantizer is a flash adc composed of 4 comparators arranged with equally spaced thresholds and a thermometer coding. the afe also includes pro- prietary 5-level dac architecture that is inherently linear for improved thd figures. the resulting channel data is either a 16-bit or 24-bit word, presented in 23-bit or 15-bit plus sign, twos complement format and is msb (left) justified. 22.1.2 analog inputs (chn+/-) the analog inputs can be connected directly to current and voltage transducers. each input pin is protected by specialized esd structures that are certified to pass 7 kv hbm and 400v mm contact charge. these structures allow bipolar 6v continuous voltage with respect to sav ss , to be present at their inputs without the risk of permanent damage. 22.1.3 programmable gain amplifiers (pga) the two programmable gain amplifiers (pgas) reside at the front-end of each delta-sigma adc. they have two functions: translate the common-mode of the input from savss to an internal level between sav ss and sav dd , and amplify the input differential signal. the translation of the common-mode does not change the differential signal, but recenters the common-mode so that the input signal can be properly amplified. the pga block can be used to amplify very low signals, but the differential input range of the delta-sigma modulator must not be exceeded. 22.1.4 sinc 3 filter both adcs include a decimation filter that is a third-order sinc (or notch) filter. this filter processes the multi-bit stream into either 16-bit or 24-bit words, depending on the configuration chosen. the settling time of the filter is three dmclk periods. the resolution achievable at the output of the sinc filter (the output of the adc) is dependent on the oversampling ratio selected. 22.1.4.1 internal voltage reference the afe contains an internal voltage reference source specially designed to minimize drift over temperature. this internal v ref supplies reference voltage to both channels. the typical value of this voltage reference is 2.37v 2%. the internal reference has a very low typi- cal temperature coefficient of 12 ppm/c, allowing the output codes to have minimal variation with respect to temperature since they are proportional to (1/v ref ). the output pin for the internal voltage reference is refin+/out. optionally, the afe can be configured to use an exter- nal voltage reference supplied on the refin+ and refin- pins. 22.1.5 phase delay block the afe incorporates a phase delay generator which ensures that the two adcs are converting the inputs with a fixed delay between them. the two adcs are synchronously sampling but the averaging of modulator outputs is delayed, so that the sinc filter outputs (thus, the adc outputs) show a fixed phase delay, configured by the phase register. 22.1.6 internal afe clock the afe uses an external clock signal to operate its internal digital logic. the afe includes a clock genera- tion chain of back-to-back dividers to produce a range of sampling frequencies. 22.1.7 serial interface the afe uses an spi-compatible slave serial interface. its operation is discussed in section 22.3 serial interface . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 285 pic18f87j72 family 22.2 afe register map the dual-channel afe uses its own internal registers for data and control. this memory is not mapped to the microcontrollers sfr space, but is accessed through the afes serial interface. the memory space is divided into eight registers: two 24-bit registers, one for the data of each adc five 8-bit control registers one reserved 8-bit register address although the data registers are 24 bits wide, they may be directly addressed as three different 8-bit registers. the complete memory map is listed in table 22-1. all registers are fully described in section b.6 internal registers of the afe reference. registers may be read singly in a single read opera- tion; continuously, as part of a group of registers; or continuously, by type (i.e., data registers vs. control registers). the type of read operation is handled through the afes serial interface by selecting the type of read operation. the grouping of registers is shown in table 22-2. a complete description of the different read operations and how to implement them is described in section b.5.3 reading from the device of the afe reference. . table 22-2: register map grouping for continuous read modes table 22-1: afe register map address name bits r/w description 00h data_ch0 24 r channel 0 adc data <23:0>, msb first 03h data_ch1 24 r channel 1 adc data <23:0>, msb first 06h reserved 8 reserved; ignore reads, do not write 07h phase 8 r/w phase delay configuration register 08h gain 8 r/w gain configuration register 09h status/com 8 r/w status/communication register 0ah config1 8 r/w configuration register 1 0bh config2 8 r/w configuration register 2 function address read<1:0> 01 10 11 data_ch0 00h group type loop entire register map 01h 02h data_ch1 03h group 04h 05h phase 07h group type gain 08h status/com 09h group config1 0ah config2 0bh downloaded from: http:///
pic18f87j72 family ds39979a-page 286 preliminary ? 2010 microchip technology inc. 22.3 serial interface 22.3.1 overview all communication with the dual-channel afe is handled through its serial interface; this includes the exchange of data with the pic18f8xj72 device itself. this arrangement allows the afe to direct data with other microcontrollers on an spi bus in complex appli- cations, and work cooperatively with other spi enabled analog devices. the serial interface is an spi-compatible slave inter- face, compatible with spi modes, 0,0 and 1,1. data is clocked out of the afe on the falling edge of scka and, clocked into the device on the rising edge of scka. in these modes, scka can idle either high or low. a complete discussion of the serial interface is pro- vided in section b.5 serial interface description of the afe reference. 22.3.2 control byte the first byte transmitted to the afe is always a control byte. this byte is composed of three fields (figure 22-2): two address bits (a<6:5>, the msbs) five register address bits (a<4:0>) one read/write bit (r/w , the lsbs) the afe interface is device-addressable (through a<6:5>), so that multiple devices can be present on the same spi bus with no data bus contention. this functionality allows external spi master devices on the bus, such as another microcontroller, to read and share data. it also enables three-phase power metering systems containing two additional analog front end devices, controlled by a single spi bus (single cs , sck, sdi and sdo pins). the spi device address bits of the pic18f87j72 interface are always 00 ; they cannot be changed. figure 22-2: control byte a read on undefined addresses gives an output of all zeros on the first and all subsequent transmitted bytes. writing to an undefined address has no effect and does not increment the address counter either. 22.3.3 reading from the device the first data byte read is the one defined by the address given in the control byte. after this first byte is transmitted, if the csa pin is held low, the communica- tion continues and the address of the next transmitted byte is determined by the configuration of the interface, set by the read bits in the status/com register. 22.3.4 writing to the device the first data byte written is the one defined by the address given in the control byte. the write communication automatically increments the address for subsequent bytes. the address of the next transmitted byte within the same communication (csa stays low) is the next address defined on the register map. at the end of the register map, the address loops to the beginning of the register map. writing a non-writable register has no effect. the sdoa pin remains in a high-impedance state during a write communication. 22.3.5 continuous communication and looping on address sets if the user wishes to read back one or both of the adc channels continuously, the internal address counter of the afe can be set to loop on specific register sets. this method also makes it possible to continuously read specific register groups, one of the register types or all of the registers. in each case, one control byte on sdia starts the communication. the part stays within the same loop until csa returns high. continuous communication is described in more detail in section b.5.7 continuous communication, looping on address sets of the afe reference. 22.3.6 data ready pin (dr ) in addition to the standard spi interface pins (sdia, sdoa, scka and csa ), the afe provides an addi- tional data ready (dr ) signal. this signifies to an external device when conversion data is available. the dr signal, available on the pin of the same name, is an active-low pulse at the end of a channel conversion, with a period that is equal to the drclk clock period and with a width equal to one dmclk period. the dr pin can be configured to operate in different modes that are defined by the availability of conversion data on the adc channels. the various data ready modes and configuration options for the dr pin are described in section b.5.9 data ready pin (dr) of the afe reference. a6 a5 a4 a3 a2 a1 a0 r/w read write bit register device address bits address bits downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 287 pic18f87j72 family 22.4 afe connections the dual-channel afe has multiple data and power con- nections that are independent of the digital side of the microcontroller. these connections are required to use the afe, and are in addition to the connection and layout connections provided in section 2.0 guidelines for getting started with pic18fj microcontrollers . all of the connections required for proper operation of the afe are shown in figure 22-3. 22.4.1 voltage and ground connections the afe has independent voltage supply requirements that differ from the rest of the microcontroller. digital cir- cuits are supplied through the sv dd pin, which requires a voltage of 2.7v to 5.5v. typically, sv dd can be tied to 3.3v, the same as the v dd and av dd pins. analog cir- cuits are separately supplied through the sav dd pin, which requires a voltage of 4.5v to 5.5v (5v 10%). independent ground returns are provided through the svss and savss pins, respectively. as with the microcontrollers v dd /v ss and av dd /av ss pins, bypass capacitors are required on the afe power and return pin pairs. requirements for these capacitors are identical to those for the v dd /v ss and av dd /av ss pins. it is recommended that designs using pic18f87j72 family devices incorporate a separate ground return path for analog circuits. savss, as well as other afe analog pins (e.g., refin-) that require grounding, should be tied to this analog return. sv ss can be tied to the digital ground, along with v ss and av ss . the ana- log and digital grounds may be tied to a single point at the power source. figure 22-3: required connections for afe operation pic18f8xj72 sdia gpio (1) sdo sdi ch1- sav ss refin+/out refin- dr scka sdoa key (all values are recommendations): c1 and c2: 0.1 ? f, 20v ceramic c3 and c4: 100 nf, 20v ceramic. bold lines show spi connections. note 1: any available i/o pins may be used to control areset and csa . the software examples discussed in this chapter use rd0 and rd7, respectively. 2: the software examples discussed in this chapter use ccp1 to generate the afe clock source. other clock sources may be used, as required. gpio (1) areset csa int0 sck ccp1 (2) clkia c3 c4 ch1+ ch0- ch0+ differential analog inputs sv ss sav dd sv dd c1 c2 analog gnd sv dd (3.3v) sav dd (5v) downloaded from: http:///
pic18f87j72 family ds39979a-page 288 preliminary ? 2010 microchip technology inc. 22.4.2 serial interface connections the afe uses its own dedicated serial peripheral interface (spi) to both send output data from its a/d converters, and send and receive control information. the interface allows the afe to operate directly with other microcontrollers and analog peripherals that use spi on a common serial bus. to use the interface, the following connections are required between the afe and the mssp module: from sdo (rc5) to sdia from sdi (rc4) to sdoa from sck (rc3) to scka in addition, the afe requires a chip select signal on the csa pin (active-low) to function properly. the chip select signal can be supplied by any available i/o pin. 22.4.3 other interface connections in addition to the spi connections, the afe requires three other digital signals for proper control: the data ready (dr ) output, asserted low to signal that a conversion has been completed and is ready to be transferred; a module reset (areset ), asserted low to inde- pendently force the afe into a por event; and a clock for the afes digital circuits, supplied on the clkia pin. to use the data ready, tie the dr pin to an external interrupt pin, such as int0. asserting dr will cause an interrupt, the isr for which can be used to read the afes data through the spi. note that whatever inter- rupt trigger is used, it must be properly configured to trigger when the pin is asserted low. for the reset input, use an available i/o pin to drive areset low when needed. for the afe clock signal, any suitable clock signal in the proper frequency range (1 mhz to 5 mhz) can be used. one convenient and low pin count method is to use a ccp module in pwm mode to generate an appropriate clock, then connect the modules output pin to clkia. 22.4.4 analog inputs the analog signals to be converted to digital values are connected to the pins of ch0 and/or ch1. each chan- nel has inverting and non-inverting inputs (chn- and chn+, respectively), and is fully differential. limits and absolute maximums for the inputs are described in section 29.0 electrical characteristics . the refin+/out and refin- pins are used to supply an external voltage reference to the afe; the refin+/out pin can also be configured to provide voltage generated by the afes internal voltage refer- ence. if the internal voltage reference is enabled, bypass capacitors to analog ground are recommended for the refin+/out pin. the refin- pin should be directly connected to analog ground (as shown in figure 22-3). 22.5 using the afe to configure the afe and read a/d conversion data, follow this sequence: 1. initialize the mssp module: a) configure for spi master mode, in either spi mode 0,0 (ckp = 0 , cke = 1 ) or mode 1,1 (ckp = 1 , cke = 0 ). b) configure trisc for sck and sdo as out- puts, and sdi as input. 2. reset the afe by pulling areset low. 3. pull c sa high. 4. disable the chip select signals of all the devices connected to the same spi bus. 5. pull csa low, then write the register address with command (read or write selection) to the afe through the spi. as long as csa is enabled, the address will increment automatically after each spi transfer is completed. after sending the address and command, the registers of the afe can be written or read. disable csa after read or write to a set of afe registers. 6. when the dr signal is asserted, signalling that an a/d conversion is complete, use an interrupt routine to read the data from one or both chan- nels. the overall method is similar to that for reading other afe registers over the spi, described in step 5. note that spi operations to read or write the afes reg- isters can be performed even without providing clkia to the afe. the clkia signal is required to perform a/d conversions and make the data ready (dr ) signal available after conversions are done. note: the first byte sent to the afe upon initialization must always be a control byte. see appendix b.5 serial interface description for more information. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 289 pic18f87j72 family example 22-1 provides a general outline for imple- menting a driver routine for the afe. example 22-2 through example 22-5 show the details for each step. the example shown here assumes the following loopback connections: rc4 (sdi) to sdoa rc5 (sdo) to sdia rc3 (sck) to scka rd0 to areset rd7 to csa rc2 (ccp1) to clkia rb0 (int0) to dr aside from the spi, which is determined by the microcontrollers single mssp module, the other connections may change based on the particular appli- cations requirements. for example, the afe clock on clkia is generated from the pwm of ccp1 in this demonstration; other clock sources may be available. users should modify the individual code segments accordingly. example 22-1: overall structure for using the afe /////////////////////////////////////////////////////////////////////////////////////////////// // outline of a typical driver routine for the dual-channel afe. /////////////////////////////////////////////////////////////////////////////////////////////// #include "p18f87j72.h" void main(void) { /////////////////////////////////////////////////////////////////////////////////// // step 1:initialize mssp (example 22-2) //////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////// // step 2: issue reset to afe (example 22-2) ///////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////// // steps 3: disable all chip selects on all spi devices (example 22-2) //////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////// // step 4: write to afe registers; read back (optionally) to confirm settings (example 22-4) //////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////// // step 5: configure ccp1 to serve as afe clock source (example 22-3) ///////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////// ///step 6: configure interrupt int0 for use with dr pin (example 22-3) ///////////////////////////////////////////////////////////////////////////////////////////// while(1); } ///////////////////////////////////////////////////////////////////////////////////////////// //step 7: isr for reading afe data (example 22-5) //////////////////////////////////////////////////////////////////////////////////////////// downloaded from: http:///
pic18f87j72 family ds39979a-page 290 preliminary ? 2010 microchip technology inc. example 22-2: initializing the mssp module example 22-3: afe clock source and interrupt configuration /////////////////////////////////////////////////////////////////////////////////// // step 1: initialize the mssp in spi master mode to access the afe // connections: sck--scka, sdi--sdoa, sdo--sdia //////////////////////////////////////////////////////////////////////////////////// sspcon1bits.ckp = 1; // spi mode 1,1: idle state for sck is high, sspcon1bits.cke = 0; // data transmitted on transition from idle to active state // sspcon1bits.ckp = 0; // if spi mode 0,0 is used instead, sck idle state is low, // sspcon1bits.cke = 1; // data trasmitted on transition from active to idle state sspcon1bits.sspen = 1; // enable spi triscbits.trisc3 = 0; // define sck pin as output triscbits.trisc4 = 1; // define sdi pin as input triscbits.trisc5 = 0; // define sdo pin as output /////////////////////////////////////////////////////////////////////////////// // step 2: issue reset to afe. areset pin is connected to rd0 in this example ///////////////////////////////////////////////////////////////////////////////////// latdbits.latd0 = 0; trisdbits.trisd0=0; // put the delta sigma adc module in reset latdbits.latd0 = 1; // release the delta sigma adc module from reset //////////////////////////////////////////////////////////////////////////////////// // step 3: // disable all chip selects for all devices connected to spi, including chip select // for the afe. csa is connected to rd7 in this example //////////////////////////////////////////////////////////////////////////////////// trisdbits.trisd7=0;latdbits.latd7=1; /////////////////////////////////////////////////////////////////////////////////////////////// // step 5: set up clock to afe. // connections: in this example clkia is connected to ccp1. /////////////////////////////////////////////////////////////////////////////////////////////// ccp1con |= 0b00001100; // ccpxm3:ccpxm0 11xx=pwm mode ccpr1l=0x01; // 50% duty cycle clock triscbits.trisc2 = 0; // make rc2 output; rc2 is connected to clkia of afe t2conbits.tmr2on = 0; // stop timer2 registers to por state pr2 = 0x01; // set period t2conbits.tmr2on = 1; // turn on pwm1 /////////////////////////////////////////////////////////////////////////////////////////////// // step 6: interrupt configuration // dr output of afe can be used as interrupt. it can be connected to any external interrupt, // like int0. it can be declared as low or high priority interrupt. // this example configures int0 (connected to dr)as a high-priority interrupt. /////////////////////////////////////////////////////////////////////////////////////////////// rconbits.ipen=1; //priority interrupt intcon2bits.rbpu=0; //enable int0 pull-up; required intcon2bits.intedg0=0; //falling edge select; dr is active low pulse intconbits.gieh = 1; //enable high pririty interrupts intconbits.int0ie = 1; //enable int0 interrupt downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 291 pic18f87j72 family example 22-4: writing and reading afe registers through the mssp /////////////////////////////////////////////////////////////////////////////////////////////// // step 4: write to afe registers // initialize the afe by writing to phase, gain, status, config1 and config2 registers. // below is an example. the registers can be programmed with values as required // by the application. /////////////////////////////////////////////////////////////////////////////////////////////// latdbits.latd7=0; //chipselect enable for delta sigma adc if (sspstatbits.bf==1) dummy_read=sspbuf; sspbuf = 0x0e; //address and write command for gain register // a6-a5--->00;a4-a0---->0x07;r/w---0 for write while(!sspstatbits.bf); dummy_read=sspbuf; //dummy read to clear buffer full status bit sspbuf =0x00; //phase register: no delay while(!sspstatbits.bf); dummy_read=sspbuf; sspbuf =0x04; //address automatically incremented gain register //ch1 gain 16, ch0 gain 1, no boost while(!sspstatbits.bf); dummy_read=sspbuf; sspbuf = 0xa0; //address automatically incremented status register //default values while(!sspstatbits.bf); dummy_read=sspbuf; sspbuf = 0x10; //address automatically incrementeddata for config1 register //no dither, other values are default while(!sspstatbits.bf); dummy_read=sspbuf; sspbuf = 0x01; //address automatically incremented data for config2 register //clkext bit should be always programmed to 1 while(!sspstatbits.bf); dummy_read=sspbuf; latdbits.latd7=1; //disable chip select after read/write of each set of registers /////////////////////////////////////////////////////////////////////////////////////////////// // read from afe registers to verify; this step is optional and does not affect afe operation. // as an example, only gain, status, config1 and config2 are read. /////////////////////////////////////////////////////////////////////////////////////////////// latdbits.latd7=0; //chip select enable for afe sspbuf = 0x11; //address and read command for gain register // a6-a5--->00;a4-a0---->0x08;r/w---1 for read while(!sspstatbits.bf); dummy_read=sspbuf; //dummy read to clear buffer full status bit sspbuf =0x00; while(!sspstatbits.bf); d_s_adc_data1=sspbuf; //data from gain register sspbuf =0x00; while(!sspstatbits.bf); d_s_adc_data2=sspbuf; //data from status register, address automatically incremented sspbuf =0x00; while(!sspstatbits.bf); d_s_adc_data3=sspbuf; //data from config1 register, address automatically incremented sspbuf = 0x00; while(!sspstatbits.bf); d_s_adc_data4=sspbuf; //data from config2 register, address automatically incremented latdbits.latd7=1; //disable chip select after read/write of each set of registers downloaded from: http:///
pic18f87j72 family ds39979a-page 292 preliminary ? 2010 microchip technology inc. example 22-5: reading data from afe during interrupt ///////////////////////////////////////////////////////////////////////////////////////////// // step 7: reading afe results in interrupt routine. // adc is configured in 16-bit result mode, thus 16-bit result of each channel can be read. // in this example dr is connected to int0; after each convesion, dr issues interrupt to int0. // int0 is configured as high priority interrupt //////////////////////////////////////////////////////////////////////////////////////////// #pragma interrupt high_isr_routine void high_isr_routine(void) { char d_s_adc_data1=0,d_s_adc_data2=0,d_s_adc_data3=0,d_s_adc_data4=0,dummy_read=0; if((intconbits.int0if)&&(intconbits.int0ie)) { // disable all chip selects of other devices connected to spi latdbits.latd7=0; //chip select enable for delta sigma adc ssp1buf = 0x01; //address and read command for channel0 result msb register while(!sspstatbits.bf); dummy_read=sspbuf; //dummy read to clear buffer full status bit sspbuf =0x00; while(!sspstatbits.bf); d_s_adc_data1=sspbuf; //data from channel0 msb sspbuf = 0x00; while(!sspstatbits.bf); d_s_adc_data2=sspbuf; //data from channel0 lsb, address automatically incremented sspbuf = 0x00; while(!sspstatbits.bf); d_s_adc_data3=sspbuf; //data from channel1 msb, address automatically incremented sspbuf = 0x00; while(!sspstatbits.bf); d_s_adc_data4=sspbuf; //data from channel1 lsb, address automatically incremented latdbits.latd7=1; //disable chip select after read/write of registers intconbits.int0if=0; //clear int0if for next interrupt } } #pragma code high_isr=0x08 void high_isr(void) { _asm goto high_isr_routine _endasm } downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 293 pic18f87j72 family 23.0 comparator module the analog comparator module contains two comparators that can be configured in a variety of ways. the inputs can be selected from the analog inputs multiplexed with pins, rf1 through rf6, as well as the on-chip voltage reference (see section 24.0 comparator voltage reference module ). the digi- tal outputs (normal or inverted) are available at the pin level and can also be read through the control register. the cmcon register (register 23-1) selects the comparator input and output configuration. block diagrams of the various comparator configurations are shown in figure 23-1. register 23-1: cmcon: comparat or module control register r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 c2out : comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out : comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv : comparator 2 output inversion bit 1 = c2 output is inverted 0 = c2 output is not inverted bit 4 c1inv : comparator 1 output inversion bit 1 = c1 output is inverted 0 = c1 output is not inverted bit 3 cis : comparator input switch bit when cm<2:0> = 110 : 1 =c1 v in - connects to rf5/an10/cv ref /seg23/c1inb c2 v in - connects to rf3/an8/seg21/c2inb 0 =c1 v in - connects to rf6/an11/seg24/c1ina c2 v in - connects to rf4/an9/seg22/c2ina bit 2-0 cm<2:0> : comparator mode bits figure 23-1 shows the comparator modes and the cm<2:0> bit settings. downloaded from: http:///
pic18f87j72 family ds39979a-page 294 preliminary ? 2010 microchip technology inc. 23.1 comparator configuration there are eight modes of operation for the compara- tors, shown in figure 23-1. the cm<2:0> bits of the cmcon register are used to select these modes. the trisf register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in section 29.0 electrical characteristics . figure 23-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change; otherwise, a false interrupt may occur. c1 v in - v in + off (read as 0 ) comparator outputs disabled aa cm<2:0> = 000 c2 v in - v in + off (read as 0 ) aa c1 v in - v in + c1out two independent comparators aa cm<2:0> = 010 c2 v in - v in + c2out aa c1 v in - v in + c1out two common reference comparators aa cm<2:0> = 100 c2 v in - v in + c2out ad c2 v in - v in + off (read as 0 ) one independent comparator with output dd cm<2:0> = 001 c1 v in - v in + c1out aa c1 v in - v in + off (read as 0 ) comparators off (por default value) dd cm<2:0> = 111 c2 v in - v in + off (read as 0 ) dd c1 v in - v in + c1out four inputs multiplexed to two comparators aa cm<2:0> = 110 c2 v in - v in + c2out aa from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 v in - v in + c1out two common reference comparators with outputs aa cm<2:0> = 101 c2 v in - v in + c2out ad a = analog input, port reads zeros always d = digital input cis (cmcon<3>) is the comparator input switch cv ref c1 v in - v in + c1out two independent comparators with outputs aa cm<2:0> = 011 c2 v in - v in + c2out aa rf1/an6/c2out*/seg19 rf2/an7/c1out*/seg20 * setting the trisf<2:1> bits will disable the comparator outputs by configuring the pins as inputs. c1inac1inb c2ina c2inb c1inb c2inac2inb c1ina c1ina c1inb c2ina rf2/an7/c1out*/seg20 rf1/an6/c2out*/seg19 rf2/an7/c1out*/ seg20 c1ina c1inb c2inac2inb c1ina c1inb c2ina c2inb c1ina c1inb c2inac2inb c1ina c1inb c2ina c2inb c1ina c1inb c2ina c2inb c2inb downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 295 pic18f87j72 family 23.2 comparator operation a single comparator is shown in figure 23-2, along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 23-2 represent the uncertainty due to input offsets and response time. 23.3 comparator reference depending on the comparator operating mode, either an external or internal voltage reference may be used. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is adjusted accordingly (figure 23-2). figure 23-2: single comparator 23.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 23.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module. this module is described in more detail in section 24.0 comparator voltage reference module . the internal reference is only available in the mode where four inputs are multiplexed to two comparators (cm<2:0> = 110 ). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 23.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal ref- erence is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used (see section 29.0 electrical characteristics ). 23.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the rf1 and rf2 i/o pins. when enabled, multiplexers in the output path of the rf1 and rf2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 23-3 shows the comparator output block diagram. the trisf bits will still function as an output enable/ disable for the rf1 and rf2 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<5:4>). C + v in + v in - output output v in - v in + note 1: when reading the port register, all pins configured as analog inputs will read as 0 . pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. downloaded from: http:///
pic18f87j72 family ds39979a-page 296 preliminary ? 2010 microchip technology inc. figure 23-3: comparator output block diagram 23.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir2<6>) is the comparator interrupt flag. the cmif bit must be reset by clearing it. since it is also possible to write a 1 to this register, a simulated interrupt may be initiated. both the cmie bit (pie2<6>) and the peie bit (intcon<6>) must be set to enable the interrupt. in addition, the gie bit (intcon<7>) must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit, cmif. a mismatch condition will continue to set flag bit, cmif. reading cmcon will end the mismatch condition and allow flag bit, cmif, to be cleared. 23.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional, if enabled. this interrupt will wake-up the device from sleep mode, when enabled. each operational comparator will consume additional current, as shown in the comparator specifications. to minimize power consumption while in sleep mode, turn off the comparators (cm<2:0> = 111 ) before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 23.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator modules to be turned off (cm<2:0> = 111 ). however, the input pins (rf3 through rf6) are configured as analog inputs by default on device reset. the i/o configuration for these pins is determined by the setting of the pcfg<3:0> bits (adcon1<3:0>). therefore, device current is minimized when analog inputs are present at reset time. dq en to rf1 or rf2 pin bus data set multiplex cmif bit -+ port pins read cmcon reset from other comparator cxinv dq en cl note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir2<6>) interrupt flag may not get set. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 297 pic18f87j72 family 23.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 23-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 23-4: comparator analog input model table 23-1: registers associat ed with comparator module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 49 pir2 oscfif cmif bclif lvdif tmr3if 5 2 pie2 oscfie cmie bclie lvdie tmr3ie 5 2 ipr2 oscfip cmip bclip lvdip tmr3ip 5 2 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 51 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 51 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 5 2 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 5 2 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 5 2 legend: = unimplemented, read as 0 . shaded cells are unused by the comparator module. va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 100 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage comparator input downloaded from: http:///
pic18f87j72 family ds39979a-page 298 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 299 pic18f87j72 family 24.0 comparator voltage reference module the comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. a block diagram of the module is shown in figure 24-1. the resistor ladder is segmented to provide two ranges of cv ref values and has a power-down function to conserve power when the reference is not being used. the modules supply reference can be provided from either device v dd /v ss or an external voltage reference. 24.1 configuring the comparator voltage reference the comparator voltage reference module is controlled through the cvrcon register (register 24-1). the comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. the range to be used is selected by the cvrr bit (cvrcon<5>). the primary difference between the ranges is the size of the steps selected by the cv ref selection bits (cvr<3:0>), with one range offering finer resolution. the equations used to calculate the output of the comparator voltage reference are as follows: if cvrr = 1 : cv ref = ((cvr<3:0>)/24) x (cv rsrc ) if cvrr = 0 : cv ref = (cv rsrc /4) + ((cvr<3:0>)/32) x (cv rsrc ) the comparator reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref - that are multiplexed with ra2 and ra3. the voltage source is selected by the cvrss bit (cvrcon<4>). the settling time of the comparator voltage reference must be considered when changing the cv ref output (see table 29-3 in section 29.0 electrical characteristics ). register 24-1: cvrcon: comparator vo ltage reference control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe (1) cvrr cvrss cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 cvren : comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe : comparator v ref output enable bit (1) 1 =cv ref voltage level is also output on the rf5/an10/cv ref /seg23/c1inb pin 0 =cv ref voltage is disconnected from the rf5/an10/cv ref /seg23/c1inb pin bit 5 cvrr : comparator v ref range selection bit 1 = 0 to 0.667 cv rsrc , with cv rsrc /24 step size (low range) 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size (high range) bit 4 cvrss : comparator v ref source selection bit 1 = comparator reference source, cv rsrc = (v ref +) C (v ref -) 0 = comparator reference source, cv rsrc = v dd C v ss bit 3-0 cvr<3:0>: comparator v ref value selection bits (0 ? (cvr<3:0>) ? 15) when cvrr = 1 : cv ref = ((cvr<3:0>)/24) ? (cv rsrc ) when cvrr = 0 : cv ref = (cv rsrc /4) + ((cvr<3:0>)/32) ? (cv rsrc ) note 1: cvroe overrides the trisf<5> bit setting. downloaded from: http:///
pic18f87j72 family ds39979a-page 300 preliminary ? 2010 microchip technology inc. figure 24-1: comparator voltage reference block diagram 24.2 voltage reference accuracy/error the full range of voltage reference cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 24-1) keep cv ref from approaching the refer- ence source rails. the voltage reference is derived from the reference source; therefore, the cv ref output changes with fluctuations in that source. the tested absolute accuracy of the voltage reference can be found in section 29.0 electrical characteristics . 24.3 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the cvrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 24.4 effects of a reset a device reset disables the voltage reference by clearing bit, cvren (cvrcon<7>). this reset also disconnects the reference from the ra2 pin by clearing bit, cvroe (cvrcon<6>) and selects the high-voltage range by clearing bit, cvrr (cvrcon<5>). the cvr value select bits are also cleared. 24.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the rf5 pin if the cvroe bit is set. enabling the voltage reference out- put onto ra2 when it is configured as a digital input will increase current consumption. connecting rf5 as a digital output with cvrss enabled will also increase current consumption. the rf5 pin can be used as a simple d/a output with limited drive capability. due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to v ref . figure 24-2 shows an example buffering technique. 16-to-1 mux cvr<3:0> 8r r cvren cvrss = 0 v dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 rr r r r r 16 steps cvrr cv ref downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 301 pic18f87j72 family figure 24-2: comparator voltage reference output buffer example table 24-1: registers associated with comparator voltage reference name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 51 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 51 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 5 2 legend: = unimplemented, read as 0 . shaded cells are not used with the comparator voltage reference. cv ref output +C cv ref module voltage reference output impedance r (1) rf5 note 1: r is dependent upon the comparator voltage refe rence bits, cvrcon<5> and cvrcon<3:0>. pic18f87j72 downloaded from: http:///
pic18f87j72 family ds39979a-page 302 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 303 pic18f87j72 family 25.0 charge time measurement unit (ctmu) the charge time measurement unit (ctmu) is a flexible analog module that provides accurate differen- tial time measurement between pulse sources, as well as asynchronous pulse generation. by working with other on-chip analog modules, the ctmu can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay. the ctmu is ideal for interfacing with capacitive-based sensors. the module includes the following key features: up to 13 channels available for capacitive or time measurement input on-chip precision current source four-edge input trigger sources polarity control for each edge source control of edge sequence control of response to edges time measurement resolution of 1 nanosecond high-precision time measurement time delay of external or internal signal asynchronous to system clock accurate current source suitable for capacitive measurement the ctmu works in conjunction with the a/d converter to provide up to 13 channels for time or charge measurement, depending on the specific device and the number of a/d channels available. when config- ured for time delay, the ctmu is connected to one of the analog comparators. the level-sensitive input edge sources can be selected from four sources: two external inputs or ccp1/ccp2 special event triggers. figure 25-1 provides a block diagram of the ctmu. figure 25-1: ctmu block diagram ctedg1 ctedg2 current source edge control logic ctmucon pulse generator a/d converter comparator 2 input ccp2 ccp1 current control itrim<5:0> irng<1:0> ctmuicon ctmu control logic edgen edgseqen edg1selx edg1pol edg2selx edg2pol edg1stat edg2stat tgen idissen cttrig a/d trigger ctpls comparator 2 output downloaded from: http:///
pic18f87j72 family ds39979a-page 304 preliminary ? 2010 microchip technology inc. 25.1 ctmu operation the ctmu works by using a fixed current source to charge a circuit. the type of circuit depends on the type of measurement being made. in the case of charge measurement, the current is fixed, and the amount of time the current is applied to the circuit is fixed. the amount of voltage read by the a/d is then a measure- ment of the capacitance of the circuit. in the case of time measurement, the current, as well as the capaci- tance of the circuit, is fixed. in this case, the voltage read by the a/d is then representative of the amount of time elapsed from the time the current source starts and stops charging the circuit. if the ctmu is being used as a time delay, both capaci- tance and current source are fixed, as well as the voltage supplied to the comparator circuit. the delay of a signal is determined by the amount of time it takes the voltage to charge to the comparator threshold voltage. 25.1.1 theory of operation the operation of the ctmu is based on the equation for charge: more simply, the amount of charge measured in coulombs in a circuit is defined as current in amperes ( i ) multiplied by the amount of time in seconds that the current flows ( t ). charge is also defined as the capaci- tance in farads ( c ) multiplied by the voltage of the circuit ( v ). it follows that: the ctmu module provides a constant, known current source. the a/d converter is used to measure ( v ) in the equation, leaving two unknowns: capacitance ( c ) and time ( t ). the above equation can be used to calcu- late capacitance or time, by either the relationship using the known fixed capacitance of the circuit: or by: using a fixed time that the current source is applied to the circuit. 25.1.2 current source at the heart of the ctmu is a precision current source, designed to provide a constant reference for measure- ments. the level of current is user-selectable across three ranges or a total of two orders of magnitude, with the ability to trim the output in 2% increments (nominal). the current range is selected by the irng<1:0> bits (ctmuicon<1:0>), with a value of 00 representing the lowest range. current trim is provided by the itrim<5:0> bits (ctmuicon<7:2>). these six bits allow trimming of the current source in steps of approximately 2% per step. note that half of the range adjusts the current source positively and the other half reduces the current source. a value of 000000 is the neutral position (no change). a value of 100000 is the maximum negative adjustment (approximately -62%) and 011111 is the maximum positive adjustment (approximately +62%). 25.1.3 edge selection and control ctmu measurements are controlled by edge events occurring on the modules two input channels. each channel, referred to as edge 1 and edge 2, can be con- figured to receive input pulses from one of the edge input pins (ctedg1 and ctedg2) or ccpx special event triggers. the input channels are level-sensitive, responding to the instantaneous level on the channel rather than a transition between levels. the inputs are selected using the edg1sel and edg2sel bit pairs (ctmuconl<3:2, 6:5>). in addition to source, each channel can be configured for event polarity using the edge2pol and edge1pol bits (ctmuconl<7,4>). the input channels can also be filtered for an edge event sequence (edge 1 occur- ring before edge 2) by setting the edgseqen bit (ctmuconh<2>). 25.1.4 edge status the ctmucon register also contains two status bits, edg2stat and edg1stat (ctmuconl<1:0>). their primary function is to show if an edge response has occurred on the corresponding channel. the ctmu automatically sets a particular bit when an edge response is detected on its channel. the level-sensitive nature of the input channels also means that the status bits become set immediately if the channels configura- tion is changed and is the same as the channels current state. the module uses the edge status bits to control the cur- rent source output to external analog modules (such as the a/d converter). current is only supplied to external modules when only one (but not both) of the status bits is set, and shuts current off when both bits are either set or cleared. this allows the ctmu to measure cur- rent only during the interval between edges. after both status bits are set, it is necessary to clear them before another measurement is taken. both bits should be cleared simultaneously, if possible, to avoid re-enabling the ctmu current source. in addition to being set by the ctmu hardware, the edge status bits can also be set by software. this is also the users application to manually enable or dis- able the current source. setting either one (but not both) of the bits enables the current source. setting or clearing both bits at once disables the source. ci dv dt ------ - ? = it ? cv . ? = tcv ? ?? i ? = cit ? ?? v ? = downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 305 pic18f87j72 family 25.1.5 interrupts the ctmu sets its interrupt flag (pir3<2>) whenever the current source is enabled, then disabled. an inter- rupt is generated only if the corresponding interrupt enable bit (pie3<2>) is also set. if edge sequencing is not enabled (i.e., edge 1 must occur before edge 2), it is necessary to monitor the edge status bits and determine which edge occurred last and caused the interrupt. 25.2 ctmu module initialization the following sequence is a general guideline used to initialize the ctmu module: 1. select the current source range using the irng bits (ctmuicon<1:0>). 2. adjust the current source trim using the itrim bits (ctmuicon<7:2>). 3. configure the edge input sources for edge 1 and edge 2 by setting the edg1sel and edg2sel bits (ctmuconl<3:2 and 6:5>). 4. configure the input polarities for the edge inputs using the edg1pol and edg2pol bits (ctmuconl<4,7>). the default configuration is for negative edge polarity (high-to-low transitions). 5. enable edge sequencing using the edgseqen bit (ctmuconh<2>). by default, edge sequencing is disabled. 6. select the operating mode (measurement or time delay) with the tgen bit. the default mode is time/capacitance measurement. 7. configure the module to automatically trigger an a/d conversion when the second edge event has occurred using the cttrig bit (ctmuconh<0>). the conversion trigger is disabled by default. 8. discharge the connected circuit by setting the idissen bit (ctmuconh<1>); after waiting a sufficient time for the circuit to discharge, clear idissen. 9. disable the module by clearing the ctmuen bit (ctmuconh<7>). 10. clear the edge status bits, edg2stat and edg1stat (ctmuconl<1:0>). 11. enable both edge inputs by setting the edgen bit (ctmuconh<3>). 12. enable the module by setting the ctmuen bit. depending on the type of measurement or pulse generation being performed, one or more additional modules may also need to be initialized and configured with the ctmu module: edge source generation: in addition to the external edge input pins, ccpx special event triggers can be used as edge sources for the ctmu. capacitance or time measurement: the ctmu module uses the a/d converter to measure the voltage across a capacitor that is connected to one of the analog input channels. pulse generation: when generating system clock independent output pulses, the ctmu module uses comparator 2 and the associated comparator voltage reference. 25.3 calibrating the ctmu module the ctmu requires calibration for precise measure- ments of capacitance and time, as well as for accurate time delay. if the application only requires measurement of a relative change in capacitance or time, calibration is usually not necessary. an example of this type of appli- cation would include a capacitive touch switch, in which the touch circuit has a baseline capacitance, and the added capacitance of the human body changes the overall capacitance of a circuit. if actual capacitance or time measurement is required, two hardware calibrations must take place: the current source needs calibration to set it to a precise current, and the circuit being measured needs calibration to measure and/or nullify all other capacitance other than that to be measured. 25.3.1 current source calibration the current source onboard the ctmu module has a range of 60% nominal for each of three current ranges. therefore, for precise measurements, it is possible to measure and adjust this current source by placing a high-precision resistor, r cal , onto an unused analog channel. an example circuit is shown in figure 25-2. the current source measurement is performed using the following steps: 1. initialize the a/d converter. 2. initialize the ctmu. 3. enable the current source by setting edg1stat (ctmuconl<0>). 4. issue settling time delay. 5. perform a/d conversion. 6. calculate the current source current using i=v/r cal , where r cal is a high-precision resistance and v is measured by performing an a/d conversion. downloaded from: http:///
pic18f87j72 family ds39979a-page 306 preliminary ? 2010 microchip technology inc. the ctmu current source may be trimmed with the trim bits in ctmuicon using an iterative process to get an exact desired current. alternatively, the nominal value without adjustment may be used; it may be stored by the software for use in all subsequent capacitive or time measurements. to calculate the value for r cal , the nominal current must be chosen, and then the resistance can be calculated. for example, if the a/d converter reference voltage is 3.3v, use 70% of full scale or 2.31v as the desired approximate voltage to be read by the a/d converter. if the range of the ctmu current source is selected to be 0.55 ? a, the resistor value needed is cal- culated as r cal = 2.31v/0.55 ? a , for a value of 4.2 m ? . similarly, if the current source is chosen to be 5.5 ? a, r cal would be 420,000 ? , and 42,000 ? if the current source is set to 55 ? a. figure 25-2: ctmu current source calibration circuit a value of 70% of full-scale voltage is chosen to make sure that the a/d converter was in a range that is well above the noise floor. keep in mind that if an exact cur- rent is chosen to incorporate the trimming bits from ctmuicon, the resistor value of r cal may need to be adjusted accordingly. r cal may be also adjusted to allow for available resistor values. r cal should be of the highest precision available, keeping in mind the amount of precision needed for the circuit that the ctmu will be used to measure. a recommended minimum would be 0.1% tolerance. the following examples show one typical method for performing a ctmu current calibration. example 25-1 demonstrates how to initialize the a/d converter and the ctmu. this routine is typical for applications using both modules. example 25-2 demonstrates one method for the actual calibration routine. note that this method manually triggers the a/d converter, which is done to demonstrate the entire stepwise process. it is also possible to automatically trigger the conversion by setting the ctmus cttrig bit (ctmuconh<0>). a/d converter ctmu anx r cal current source a/d trigger mux a/d pic18f87j72 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 307 pic18f87j72 family example 25-1: setup for ctmu calibration routines #include "p18cxxx.h" /**************************************************************************/ /*setup ctmu *****************************************************************/ /**************************************************************************/ void setup(void) { //ctmucon - ctmu control register ctmuconh = 0x00; //make sure ctmu is disabled ctmuconl = 0x90; //ctmu continues to run when emulator is stopped,ctmu continues //to run in idle mode,time generation mode disabled, edges are blocked //no edge sequence order, analog current source not grounded, trigger //output disabled, edge2 polarity = positive level, edge2 source = //source 0, edge1 polarity = positive level, edge1 source = source 0, // set edge status bits to zero //ctmuicon - ctmu current control register ctmuicon = 0x01; //0.55ua, nominal - no adjustment /**************************************************************************/ //setup ad converter; /**************************************************************************/ trisa=0x04; //set channel 2 as an input // configured an2 as an analog channel // ancon0 ancon0 = 0xfb; // ancon1 ancon1 = 0x1f; // adcon1 adcon1bits.adfm=1; // resulst format 1= right justified adcon1bits.adcal=0; // normal a/d conversion operation adcon1bits.acqt=1; // acquition time 7 = 20tad 2 = 4tad 1=2tad adcon1bits.adcs=2; // clock conversion bits 6= fosc/64 2=fosc/32 ancon1bits.vbgen=1; // turn on the bandgap needed for rev a0 parts // adcon0 adcon0bits.vcfg0 =0; // vref+ = avdd adcon0bits.vcfg1 =0; // vref- = avss adcon0bits.chs=2; // select adc channel adcon0bits.adon=1; // turn on adc } downloaded from: http:///
pic18f87j72 family ds39979a-page 308 preliminary ? 2010 microchip technology inc. example 25-2: current calibration routine #include "p18cxxx.h" #define count 500 //@ 8mhz = 125us. #define delay for(i=0;i ? 2010 microchip technology inc. preliminary ds39979a-page 309 pic18f87j72 family 25.3.2 capacitance calibration there is a small amount of capacitance from the inter- nal a/d converter sample capacitor as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. a measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. the measurement is then performed using the following steps: 1. initialize the a/d converter and the ctmu. 2. set edg1stat (= 1 ). 3. wait for a fixed delay of time, t . 4. clear edg1stat. 5. perform an a/d conversion. 6. calculate the stray and a/d sample capacitances: where i is known from the current source measurement step, t is a fixed delay and v is measured by performing an a/d conversion. this measured value is then stored and used for calculations of time measurement, or subtracted for capacitance measurement. for calibration, it is expected that the capacitance of c stray + c ad is approximately known. c ad is approximately 4 pf. an iterative process may need to be used to adjust the time, t , that the circuit is charged to obtain a reasonable voltage reading from the a/d converter. the value of t may be determined by setting c offset to a theoretical value, then solving for t . for example, if c stray is theoretically calculated to be 11 pf, and v is expected to be 70% of v dd , or 2.31v, then t would be: or 63 ? s. see example 25-3 for a typical routine for ctmu capacitance calibration. c offset c stray c ad + it ? ?? v ? == (4 pf + 11 pf) 2.31v/0.55 ? a downloaded from: http:///
pic18f87j72 family ds39979a-page 310 preliminary ? 2010 microchip technology inc. example 25-3: capacitance calibration routine #include "p18cxxx.h" #define count 25 //@ 8mhz intfrc = 62.5 us. #define etime count*2.5 //time in us #define delay for(i=0;i ? 2010 microchip technology inc. preliminary ds39979a-page 311 pic18f87j72 family 25.4 measuring capacitance with the ctmu there are two separate methods of measuring capaci- tance with the ctmu. the first is the absolute method, in which the actual capacitance value is desired. the second is the relative method, in which the actual capacitance is not needed, rather an indication of a change in capacitance is required. 25.4.1 absolute capacitance measurement for absolute capacitance measurements, both the current and capacitance calibration steps found in section 25.3 calibrating the ctmu module should be followed. capacitance measurements are then performed using the following steps: 1. initialize the a/d converter. 2. initialize the ctmu. 3. set edg1stat. 4. wait for a fixed delay, t . 5. clear edg1stat. 6. perform an a/d conversion. 7. calculate the total capacitance, c total = (i * t)/v , where i is known from the current source measurement step ( section 25.3.1 current source calibration ), t is a fixed delay and v is measured by performing an a/d conversion. 8. subtract the stray and a/d capacitance ( c offset from section 25.3.2 capacitance calibration ) from c total to determine the measured capacitance. 25.4.2 relative charge measurement an application may not require precise capacitance measurements. for example, when detecting a valid press of a capacitance-based switch, detecting a relative change of capacitance is of interest. in this type of appli- cation, when the switch is open (or not touched), the total capacitance is the capacitance of the combination of the board traces, the a/d converter, etc. a larger voltage will be measured by the a/d converter. when the switch is closed (or is touched), the total capacitance is larger due to the addition of the capacitance of the human body to the above listed capacitances and a smaller voltage will be measured by the a/d converter. detecting capacitance changes is easily accomplished with the ctmu using these steps: 1. initialize the a/d converter and the ctmu. 2. set edg1stat. 3. wait for a fixed delay. 4. clear edg1stat. 5. perform an a/d conversion. the voltage measured by performing the a/d conver- sion is an indication of the relative capacitance. note that in this case, no calibration of the current source or circuit capacitance measurement is needed. see example 25-4 for a sample software routine for a capacitive touch switch. downloaded from: http:///
pic18f87j72 family ds39979a-page 312 preliminary ? 2010 microchip technology inc. example 25-4: routine for capacitive touch switch #include "p18cxxx.h" #define count 500 //@ 8mhz = 125us. #define delay for(i=0;i opensw - trip + hyst) { switchstate = unpressed; } } downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 313 pic18f87j72 family 25.5 measuring time with the ctmu module time can be precisely measured after the ratio ( c/i ) is measured from the current and capacitance calibration step by following these steps: 1. initialize the a/d converter and the ctmu. 2. set edg1stat. 3. set edg2stat. 4. perform an a/d conversion. 5. calculate the time between edges as t = (c/i) * v , where i is calculated in the current calibration step ( section 25.3.1 current source calibration ), c is calculated in the capacitance calibration step ( section 25.3.2 capacitance calibration ) and v is measured by performing the a/d conversion. it is assumed that the time measured is small enough that the capacitance c offset provides a valid voltage to the a/d converter. for the smallest time measurement, always set the a/d channel select register (ad1chs) to an unused a/d channel; the corresponding pin for which is not connected to any circuit board trace. this minimizes added stray capacitance, keeping the total circuit capacitance close to that of the a/d converter itself (25 pf). to measure longer time intervals, an external capacitor may be connected to an a/d channel, and this channel selected when making a time measurement. figure 25-3: typical connections and internal configuration for time measurement a/d converter ctmu ctedg1 ctedg2 an x output pulse edg1 edg2 c ad r pr current source pic18f87j72 downloaded from: http:///
pic18f87j72 family ds39979a-page 314 preliminary ? 2010 microchip technology inc. 25.6 creating a delay with the ctmu module a unique feature on board the ctmu module is its ability to generate system clock independent output pulses based on an external capacitor value. this is accom- plished using the internal comparator voltage reference module, comparator 2 input pin and an external capaci- tor. the pulse is output onto the ctpls pin. to enable this mode, set the tgen bit. see figure 25-4 for an example circuit. c pulse is chosen by the user to determine the output pulse width on ctpls. the pulse width is calculated by t =( c pulse / i )* v , where i is known from the current source measurement step ( section 25.3.1 current source calibration ) and v is the internal reference voltage (cv ref ). an example use of this feature is for interfacing with variable capacitive-based sensors, such as a humidity sensor. as the humidity varies, the pulse-width output on ctpls will vary. the ctpls output pin can be con- nected to an input capture pin and the varying pulse width is measured to determine the humidity in the application. follow these steps to use this feature: 1. initialize comparator 2. 2. initialize the comparator voltage reference. 3. initialize the ctmu and enable time delay generation by setting the tgen bit. 4. set edg1stat. 5. when c pulse charges to the value of the voltage reference trip point, an output pulse is generated on ctpls. figure 25-4: typical connections and internal configuration for pulse dela y generation 25.7 operation during sleep/idle modes 25.7.1 sleep mode and deep sleep modes when the device enters any sleep mode, the ctmu module current source is always disabled. if the ctmu is performing an operation that depends on the current source when sleep mode is invoked, the operation may not terminate correctly. capacitance and time measurements may return erroneous values. 25.7.2 idle mode the behavior of the ctmu in idle mode is determined by the ctmusidl bit (ctmuconh<5>). if ctmusidl is cleared, the module will continue to operate in idle mode. if ctmusidl is set, the modules current source is disabled when the device enters idle mode. if the module is performing an operation when idle mode is invoked, in this case, the results will be similar to those with sleep mode. 25.8 effects of a reset on ctmu upon reset, all registers of the ctmu are cleared. this leaves the ctmu module disabled, its current source is turned off and all configuration options return to their default settings. the module needs to be re-initialized following any reset. if the ctmu is in the process of taking a measurement at the time of reset, the measurement will be lost. a partial charge may exist on the circuit that was being measured, and should be properly discharged before the ctmu makes subsequent attempts to make a measurement. the circuit is discharged by setting and then clearing the idissen bit (ctmuconh<1>) while the a/d converter is connected to the appropriate channel. c2 cv ref ctpls current source comparator ctmu ctedg1 c2inb c delay edg1 pic18f87j72 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 315 pic18f87j72 family 25.9 registers there are three control registers for the ctmu: ctmuconh ctmuconl ctmuicon the ctmuconh and ctmuconl registers (register 25-1 and register 25-2) contain control bits for configuring the ctmu module edge source selec- tion, edge source polarity selection, edge sequencing, a/d trigger, analog circuit capacitor discharge and enables. the ctmuicon register (register 25-3) has bits for selecting the current source range and current source trim. register 25-1: ctmuconh: ct mu control high register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ctmuen ctmusidl tgen edgen edgseqen idissen cttrig bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 ctmuen: ctmu enable bit 1 = module is enabled 0 = module is disabled bit 6 unimplemented: read as 0 bit 5 ctmusidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 4 tgen: time generation enable bit 1 = enables edge delay generation 0 = disables edge delay generation bit 3 edgen: edge enable bit 1 = edges are not blocked 0 = edges are blocked bit 2 edgseqen: edge sequence enable bit 1 = edge 1 event must occur before edge 2 event can occur 0 = no edge sequence is needed bit 1 idissen: analog current source control bit 1 = analog current source output is grounded 0 = analog current source output is not grounded bit 0 cttrig: trigger control bit 1 = trigger output is enabled 0 = trigger output is disabled downloaded from: http:///
pic18f87j72 family ds39979a-page 316 preliminary ? 2010 microchip technology inc. register 25-2: ctmuconl: ct mu control low register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 edg2pol edg2sel1 edg2sel0 edg1pol ed g1sel1 edg1sel0 edg2stat edg1stat bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 edg2pol: edge 2 polarity select bit 1 = edge 2 is programmed for a positive edge response 0 = edge 2 is programmed for a negative edge response bit 6-5 edg2sel<1:0>: edge 2 source select bits 11 = ctedg1 pin 10 = ctedg2 pin 01 = ccp1 special event trigger 00 = ccp2 special event trigger bit 4 edg1pol: edge 1 polarity select bit 1 = edge 1 is programmed for a positive edge response 0 = edge 1 is programmed for a negative edge response bit 3-2 edg1sel<1:0>: edge 1 source select bits 11 = ctedg1 pin 10 = ctedg2 pin 01 = ccp1 special event trigger 00 = ccp2 special event trigger bit 1 edg2stat: edge 2 status bit 1 = edge 2 event has occurred 0 = edge 2 event has not occurred bit 0 edg1stat: edge 1 status bit 1 = edge 1 event has occurred 0 = edge 1 event has not occurred downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 317 pic18f87j72 family table 25-1: registers associated with ctmu module register 25-3: ctmuicon: ctmu current control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 itrim5 itrim4 itrim3 itrim2 itrim1 itrim0 irng1 irng0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-2 itrim<5:0>: current source trim bits 011111 = maximum positive change from nominal current 011110 . . . 000001 = minimum positive change from nominal current 000000 = nominal current output specified by irng<1:0> 111111 = minimum negative change from nominal current .. . 100010 100001 = maximum negative change from nominal current bit 1-0 irng<1:0>: current source range select bits 11 = 100 x base current 10 = 10 x base current 01 = base current level (0.55 ? a nominal) 00 = current source disabled name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page: ctmuconh ctmuen ctmusidl tgen edgen edgseqen idissen cttrig ctmuconl edg2pol edg2sel1 edg2sel0 edg1p ol edg1sel1 edg1sel0 edg2stat edg1stat ctmuicon itrim5 itrim4 itrim3 itrim2 itrim1 itrim0 irng1 irng0 legend: = unimplemented, read as 0 . shaded cells are not used during ccp operation. downloaded from: http:///
pic18f87j72 family ds39979a-page 318 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 319 pic18f87j72 family 26.0 special features of the cpu pic18f87j72 family devices include several features intended to maximize reliability and minimize cost through elimination of external components. these are: oscillator selection resets: - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) fail-safe clock monitor two-speed start-up code protection in-circuit serial programming the oscillator can be configured for the application depending on frequency, power, accuracy and cost. all of the options are discussed in detail in section 3.0 oscillator configurations . a complete discussion of device resets and interrupts is available in previous sections of this data sheet. in addition to their power-up and oscillator start-up timers provided for resets, the pic18f87j72 family of devices has a configurable watchdog timer which is controlled in software. the inclusion of an internal rc oscillator also provides the additional benefits of a fail-safe clock monitor (fscm) and two-speed start-up. fscm provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. two-speed start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. all of these features are enabled and configured by setting the appropriate configuration register bits. 26.1 configuration bits the configuration bits can be programmed (read as 0 ), or left unprogrammed (read as 1 ), to select various device configurations. these bits are mapped starting at program memory location, 300000h. a complete list is shown in table 26-2. a detailed explanation of the various bit functions is provided in register 26-1 through register 26-6. 26.1.1 considerations for configuring pic18f87j72 family devices devices of the pic18f87j72 family do not use persis- tent memory registers to store configuration information. the configuration bytes are implemented as volatile memory which means that configuration data must be programmed each time the device is powered up. configuration data is stored in the three words at the top of the on-chip program memory space, known as the flash configuration words. it is stored in program memory in the same order shown in table 26-2, with config1l at the lowest address and config3h at the highest. the data is automatically loaded in the proper configuration registers during device power-up. when creating applications for these devices, users should always specifically allocate the location of the flash configuration word for configuration data. this is to make certain that program code is not stored in this address when the code is compiled. the volatile memory cells used for the configuration bits always reset to 1 on power-on resets. for all other types of reset events, the previously programmed values are maintained and used without reloading from program memory. the four most significant bits of config1h, config2h and config3h in program memory should also be 1111 . this makes these configuration words appear to be nop instructions in the remote event that their locations are ever executed by accident. since configuration bits are not implemented in the corresponding locations, writing 1 s to these locations has no effect on device operation. to prevent inadvertent configuration changes during code execution, all programmable configuration bits are write-once. after a bit is initially programmed during a power cycle, it cannot be written to again. changing a device configuration requires that power to the device be cycled. table 26-1: mapping of the flash configuration words to the configuration registers configuration byte code space address configuration register address config1l xxxf8h 300000h config1h xxxf9h 300001h config2l xxxfah 300002h config2h xxxfbh 300003h config3l xxxfch 300004h config3h xxxfdh 300005h downloaded from: http:///
pic18f87j72 family ds39979a-page 320 preliminary ? 2010 microchip technology inc. table 26-2: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value (1) 300000h config1l debug xinst stvren w d t e n 111- ---1 300001h config1h (2) (2) (2) (2) (3) cp0 ---- 01-- 300002h config2l ieso fcmen lpt1osc t1dig fosc2 fosc1 fosc0 11-1 1111 300003h config2h (2) (2) (2) (2) wdtps3 wdtps2 wdtps1 wdtps0 ---- 1111 300004h config3l (2) (2) (2) (2) r t c o s c ---- --1- 300005h config3h (2) (2) (2) (2) ccp2mx ---- ---1 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 01xx xxxx (4) 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0101 0000 (4) legend: x = unknown, - = unimplemented. shaded cells are unimplemented, read as 0 . note 1: values reflect the unprogrammed state as received from t he factory and following power-on resets. in all other reset states, the configuration bytes maintain their previously programmed states. 2: the value of these bits in program memory should always be 1 . this ensures that the location is executed as a nop if it is accidentally executed. 3: this bit should always be maintained as 0 . 4: these registers are read-only and cannot be programmed by the user. see re gister 26-7 for device-specific values for devid1. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 321 pic18f87j72 family register 26-1: config1l: configuration register 1 low (byte address 300000h) r/wo-1 r/wo-1 r/wo-1 u-0 u-0 u-0 u-0 r/wo-1 debug xinst stvren w d t e n bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as 0 -n = value when device is unprogrammed 1 = bit is set 0 = bit is cleared bit 7 debug : background debugger enable bit 1 = background debugger is disabled; rb6 and rb7 are configured as general purpose i/o pins 0 = background debugger is enabled; rb6 and rb7 are dedicated to in-circuit debug bit 6 xinst: extended instruction set enable bit 1 = instruction set extension and indexed addressing mode are enabled 0 = instruction set extension and indexed addressing mode are disabled (legacy mode) bit 5 stvren : stack overflow/underflow reset enable bit 1 = reset on stack overflow/underflow is enabled 0 = reset on stack overflow/underflow is disabled bit 4-1 unimplemented: read as 0 bit 0 wdten: watchdog timer enable bit 1 = wdt is enabled 0 = wdt is disabled (control is placed on swdten bit) register 26-2: config1h: co nfiguration register 1 hi gh (byte address 300001h) u-0 u-0 u-0 u-0 u-0 r/wo-1 u-0 u-0 (1) (1) (1) (1) (2) cp0 bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as 0 -n = value when device is unprogrammed 1 = bit is set 0 = bit is cleared bit 7-3 unimplemented: read as 0 bit 2 cp0: code protection bit 1 = program memory is not code-protected 0 = program memory is code-protected bit 1-0 unimplemented: read as 0 note 1: the value of these bits in program memory should always be 1 . this ensures that the location is executed as a nop if it is accidentally executed. 2: this bit should always be maintained as 0 . downloaded from: http:///
pic18f87j72 family ds39979a-page 322 preliminary ? 2010 microchip technology inc. register 26-3: config2l: configuration register 2 low (byte address 300002h) r/wo-1 r/wo-1 u-0 r/wo-1 r/wo-1 r/wo-1 r/wo-1 r/wo-1 ieso fcmen lpt1osc t1dig fosc2 fosc1 fosc0 bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as 0 -n = value when device is unprogrammed 1 = bit is set 0 = bit is cleared bit 7 ieso: two-speed start-up (internal/external oscillator switchover) control bit 1 = two-speed start-up is enabled 0 = two-speed start-up is disabled bit 6 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor is enabled 0 = fail-safe clock monitor is disabled bit 5 unimplemented: read as 0 bit 4 lpt1osc: t1osc/sosc power sele ction configuration bit 1 = high-power t1osc/sosc circuit is selected 0 = low-power t1osc/sosc circuit is selected bit 3 t1dig: t1cki for digital input clock enable bit 1 = t1cki is available as a digital input without enabling t1oscen 0 = t1cki is not available as a digital input without enabling t1oscen bit 2-0 fosc<2:0>: oscillator selection bits 111 = ecpll osc1/osc2 as primary; ecpll oscillator with pll is enabled; clko on ra6 110 = ec osc1/osc2 as primary; external clock with f osc /4 output 101 = hspll osc1/osc2 as primary; high-speed crystal/resonator with software pll control 100 = hs osc1/osc2 as primary; high-speed crystal/resonator 011 = intpll1 internal oscillator block with software pll control; f osc /4 output 010 = intio1 internal oscillator block with f osc /4 output on ra6 and i/o on ra7 001 = intpll2 internal oscillator block with software pll control and i/o on ra6 and ra7 000 = intio2 internal oscillator block with i/o on ra6 and ra7 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 323 pic18f87j72 family register 26-4: config2h: configuration register 2 high (byte address 300003h) u-0 u-0 u-0 u-0 r/wo-1 r/wo-1 r/wo-1 r/wo-1 (1) (1) (1) (1) wdtps3 wdtps2 wdtps1 wdtps0 bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as 0 -n = value when device is unprogrammed 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented: read as 0 bit 3-0 wdtps<3:0>: watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 note 1: the value of these bits in program memory should always be 1 . this ensures that the location is executed as a nop if it is accidentally executed. register 26-5: config3l : configuration register 3 low (byte address 300004h) u-0 u-0 u-0 u-0 u-0 u-0 r/wo-1 u-0 (1) (1) (1) (1) r t c o s c bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as 0 -n = value when device is unprogrammed 1 = bit is set 0 = bit is cleared bit 7-2 unimplemented: read as 0 bit 1 rtcosc: rtcc reference clock select bit 1 = rtcc uses t1osc/t1cki as the reference clock 0 = rtcc uses intrc as the reference clock bit 0 unimplemented: read as 0 note 1: the value of these bits in program memory should always be 1 . this ensures that the location is executed as a nop if it is accidentally executed. downloaded from: http:///
pic18f87j72 family ds39979a-page 324 preliminary ? 2010 microchip technology inc. register 26-6: config3h: configuration register 3 high (byte address 300005h) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/wo-1 (1) (1) (1) (1) ccp2mx bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as 0 -n = value when device is unprogrammed 1 = bit is set 0 = bit is cleared bit 7-1 unimplemented: read as 0 bit 0 ccp2mx: ccp2 mux bit 1 = ccp2 is multiplexed with rc1 0 = ccp2 is multiplexed with re7 note 1: the value of these bits in program memory should always be 1 . this ensures that the location is executed as a nop if it is accidentally executed. register 26-7: devid1: device id register 1 rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = read-only bit bit 7-5 dev<2:0>: device id bits 011 = pic18f87j72 010 = pic18f86j72 bit 4-0 rev<4:0>: revision id bits these bits are used to indicate the device revision. register 26-8: devid2: device id register 2 rrrrrrrr dev10 (1) dev9 (1) dev8 (1) dev7 (1) dev6 (1) dev5 (1) dev4 (1) dev3 (1) bit 7 bit 0 legend: r = read-only bit bit 7-0 dev<10:3>: device id bits (1) these bits are used with the dev<2:0> bits in the device id register 1 to identify the part number. 0101 0000 = pic18f87j72 family devices note 1: the values for dev<10:3> may be shared with other device families. the specific device is always identified by using the entire dev<10:0> bit sequence. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 325 pic18f87j72 family 26.2 watchdog timer (wdt) for pic18f87j72 family devices, the wdt is driven by the intrc oscillator. when the wdt is enabled, the clock source is also enabled. the nominal wdt period is 4 ms and has the same stability as the intrc oscillator. the 4 ms period of the wdt is multiplied by a 16-bit postscaler. any output of the wdt postscaler is selected by a multiplexer, controlled by the wdtps bits in configuration register 2h. available periods range from 4 ms to 131.072 seconds (2.18 minutes). the wdt and postscaler are cleared whenever a sleep or clrwdt instruction is executed, or a clock failure (primary or timer1 oscillator) has occurred. 26.2.1 control register the wdtcon register (register 26-9) is a readable and writable register. the swdten bit enables or dis- ables wdt operation. this allows software to override the wdten configuration bit and enable the wdt only if it has been disabled by the configuration bit. figure 26-1: wdt block diagram note 1: the clrwdt and sleep instructions clear the wdt and postscaler counts when executed. 2: when a clrwdt instruction is executed, the postscaler count will be cleared. intrc oscillator wdt wake-up from reset wdt wdt counter programmable postscaler 1:1 to 1:32,768 enable wdt wdtps<3:0> swdten clrwdt 4 power-managed reset all device resets sleep intrc control ? 128 modes downloaded from: http:///
pic18f87j72 family ds39979a-page 326 preliminary ? 2010 microchip technology inc. table 26-3: summary of watchdog timer registers register 26-9: wdtcon: watchd og timer control register r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 regslp (1) s w d t e n (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 regslp: voltage regulator low-power operation enable bit (1) 1 = on-chip regulator enters low-power operation when device enters sleep mode 0 = on-chip regulator continues to operate normally in sleep mode bit 6-1 unimplemented : read as 0 bit 0 swdten: software controlled watchdog timer enable bit (2) 1 = watchdog timer is on 0 = watchdog timer is off note 1: the regslp bit is automatically cleared when a low-voltage detect condition occurs. 2: this bit has no effect if the configuration bit, wdten, is enabled. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page rcon ipen cm ri to pd por bor 50 wdtcon regslp s w d t e n 5 0 legend: = unimplemented, read as 0 . shaded cells are not used by the watchdog timer. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 327 pic18f87j72 family 26.3 on-chip voltage regulator all of the pic18f87j72 family devices power their core digital logic at a nominal 2.5v. for designs that are required to operate at a higher typical voltage, such as 3.3v, all devices in the pic18f87j72 family incorporate an on-chip regulator that allows the device to run its core logic from v dd . the regulator is controlled by the envreg pin. tying v dd to the pin enables the regulator, which in turn, pro- vides power to the core from the other v dd pins. when the regulator is enabled, a low-esr filter capacitor must be connected to the v ddcore /v cap pin (figure 26-2). this helps to maintain the stability of the regulator. the recommended value for the filter capac- itor is provided in section 29.3 dc characteristics: pic18f87j72 family (industrial) . if envreg is tied to v ss , the regulator is disabled. in this case, separate power for the core logic, at a nomi- nal 2.5v, must be supplied to the device on the v ddcore /v cap pin to run the i/o pins at higher voltage levels, typically 3.3v. alternatively, the v ddcore /v cap and v dd pins can be tied together to operate at a lower nominal voltage. refer to figure 26-2 for possible configurations. 26.3.1 voltage regulation and low-voltage detection when it is enabled, the on-chip regulator provides a constant voltage of 2.5v nominal to the digital core logic. the regulator can provide this level from a v dd of about 2.5v, all the way up to the devices v ddmax . it does not have the capability to boost v dd levels below 2.5v. in order to prevent brown-out conditions, when the voltage drops too low for the regulator, the regulator enters tracking mode. in tracking mode, the regulator output follows v dd , with a typical voltage drop of 100 mv. the on-chip regulator includes a simple low-voltage detect (lvd) circuit. if v dd drops too low to maintain approximately 2.45v on v ddcore , the circuit sets the low-voltage detect interrupt flag, lvdif (pir2<2>), and clears the regslp (wdtcon<7>) bit if it was set. this can be used to generate an interrupt and puts the application into a low-power operational mode or triggers an orderly shutdown. low-voltage detection is only available when the regulator is enabled. figure 26-2: connections for the on-chip regulator v dd envreg v ddcore /v cap v ss 3.3v (1) 2.5v (1) v dd envreg v ddcore /v cap v ss c f 3.3v regulator enabled (envreg tied to v dd ): regulator disabled (envreg tied to ground): v dd envreg v ddcore /v cap v ss 2.5v (1) regulator disabled (v dd tied to v ddcore ): note 1: these are typical operating voltages. for the full operating ranges of v dd and v ddcore , refer to section 29.1 dc characteristics: supply voltage pic18f87j72 family (industrial) . pic18f87j72 pic18f87j72 pic18f87j72 downloaded from: http:///
pic18f87j72 family ds39979a-page 328 preliminary ? 2010 microchip technology inc. 26.3.2 on-chip regulator and bor when the on-chip regulator is enabled, pic18f87j72 family devices also have a simple brown-out reset capability. if the voltage supplied to the regulator falls to a level that is inadequate to maintain a regulated output for full-speed operation, the regulator reset circuitry will generate a brown-out reset. this event is captured by the bor flag bit (rcon<0>). the operation of the bor is described in more detail in section 5.4 brown-out reset (bor) and section 5.4.1 detecting bor . 26.3.3 power-up requirements the on-chip regulator is designed to meet the power-up requirements for the device. if the application does not use the regulator, then strict power-up conditions must be adhered to. while powering up, v ddcore must never exceed v dd by 0.3 volts. 26.3.4 operation in sleep mode when enabled, the on-chip regulator always consumes a small incremental amount of current over i dd . this includes when the device is in sleep mode, even though the core digital logic does not require power. to provide additional savings in applications where power resources are critical, the regulator can be configured to automatically disable itself whenever the device goes into sleep mode. this feature is controlled by the regslp bit (wdtcon<7>). setting this bit disables the regulator in sleep mode and reduces its current consumption to a minimum. substantial sleep mode power savings can be obtained by setting the regslp bit, but device wake-up time will increase in order to ensure the regulator has enough time to stabilize. the regslp bit is automatically cleared by hardware when a low-voltage detect condition occurs. the regslp bit can be set again in software, which would continue to keep the voltage regulator in low-power mode. this, however, is not recommended if any write operations to the flash will be performed. 26.4 two-speed start-up the two-speed start-up feature helps to minimize the latency period, from oscillator start-up to code execu- tion, by allowing the microcontroller to use the intrc oscillator as a clock source until the primary clock source is available. it is enabled by setting the ieso configuration bit. two-speed start-up should be enabled only if the primary oscillator mode is hs or hspll (crystal-based) modes. since the ec and ecpll modes do not require an ost start-up delay, two-speed start-up should be disabled. when enabled, resets and wake-ups from sleep mode cause the device to configure itself to run from the inter- nal oscillator block as the clock source, following the time-out of the power-up timer after a power-on reset is enabled. this allows almost immediate code execution while the primary oscillator starts and the ost is running. once the ost times out, the device automatically switches to pri_run mode. in all other power-managed modes, two-speed start-up is not used. the device will be clocked by the currently selected clock source until the primary clock source becomes available. the setting of the ieso bit is ignored. figure 26-3: timing transition for two-speed start-up (intrc to hspll) q1 q3 q4 osc1 peripheral program pc pc + 2 intrc pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. wake from interrupt event t pll (1) 12 n-1n clock osts bit set transition t ost (1) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 329 pic18f87j72 family 26.4.1 special considerations for using two-speed start-up while using the intrc oscillator in two-speed start-up, the device still obeys the normal command sequences for entering power-managed modes, including serial sleep instructions (refer to section 4.1.4 multiple sleep commands ). in prac- tice, this means that user code can change the scs<1:0> bit settings or issue sleep instructions before the ost times out. this would allow an applica- tion to briefly wake-up, perform routine housekeeping tasks and return to sleep before the device starts to operate from the primary oscillator. user code can also check if the primary clock source is currently providing the device clocking by checking the status of the osts bit (osccon<3>). if the bit is set, the primary oscillator is providing the clock. otherwise, the internal oscillator block is providing the clock during wake-up from reset or sleep mode. 26.5 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. the fscm function is enabled by setting the fcmen configuration bit. when fscm is enabled, the intrc oscillator runs at all times to monitor clocks to peripherals and provides a backup clock in the event of a clock failure. clock monitoring (shown in figure 26-4) is accomplished by creating a sample clock signal, which is the intrc out- put divided by 64. this allows ample time between fscm sample clocks for a peripheral clock edge to occur. the peripheral device clock and the sample clock are presented as inputs to the clock monitor (cm) latch. the cm is set on the falling edge of the device clock source but cleared on the rising edge of the sample clock. figure 26-4: fscm block diagram clock failure is tested for on the falling edge of the sample clock. if a sample clock falling edge occurs while cm is still set, a clock failure has been detected (figure 26-5). this causes the following: the fscm generates an oscillator fail interrupt by setting bit, oscfif (pir2<7>); the device clock source is switched to the internal oscillator block (osccon is not updated to show the current clock source C this is the fail-safe condition); and the wdt is reset. during switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing-sensitive applications. in these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. this can be done to attempt a partial recovery or execute a controlled shutdown. see section 4.1.4 multiple sleep commands and section 26.4.1 special considerations for using two-speed start-up for more details. the fscm will detect failures of the primary or secondary clock sources only. if the internal oscillator block fails, no failure would be detected, nor would any action be possible. 26.5.1 fscm and the watchdog timer both the fscm and the wdt are clocked by the intrc oscillator. since the wdt operates with a separate divider and counter, disabling the wdt has no effect on the operation of the intrc oscillator when the fscm is enabled. as already noted, the clock source is switched to the intrc clock when a clock failure is detected. this may mean a substantial change in the speed of code execu- tion. if the wdt is enabled with a small prescale value, a decrease in clock speed allows a wdt time-out to occur and a subsequent device reset. for this reason, fail-safe clock monitor events also reset the wdt and postscaler, allowing it to start timing from when execu- tion speed was changed and decreasing the likelihood of an erroneous time-out. if the interrupt is disabled, subsequent interrupts while in idle mode will cause the cpu to begin executing instructions while being clocked by the intrc source. peripheral intrc 64 s c q (32 ? s) 488 hz (2.048 ms) clock monitor latch (cm) (edge-triggered) clock failure detected source clock q downloaded from: http:///
pic18f87j72 family ds39979a-page 330 preliminary ? 2010 microchip technology inc. figure 26-5: fscm timing diagram 26.5.2 exiting fail-safe operation the fail-safe condition is terminated by either a device reset or by entering a power-managed mode. on reset, the controller starts the primary clock source specified in configuration register 2h (with any required start-up delays that are required for the oscil- lator mode, such as ost or pll timer). the intrc oscillator provides the device clock until the primary clock source becomes ready (similar to a two-speed start-up). the clock source is then switched to the primary clock (indicated by the osts bit in the osccon register becoming set). the fail-safe clock monitor then resumes monitoring the peripheral clock. the primary clock source may never become ready during start-up. in this case, operation is clocked by the intosc multiplexer. the osccon register will remain in its reset state until a power-managed mode is entered. 26.5.3 fscm interrupts in power-managed modes by entering a power-managed mode, the clock multiplexer selects the clock source selected by the osccon register. fail-safe clock monitoring of the power-managed clock source resumes in the power-managed mode. if an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. if enabled (oscfif = 1 ), code execution will be clocked by the intrc multiplexer. an automatic transition back to the failed clock source will not occur. 26.5.4 por or wake-up from sleep the fscm is designed to detect oscillator failure at any point after the device has exited power-on reset (por) or low-power sleep mode. when the primary device clock is either ec or intrc mode, monitoring can begin immediately following these events. for hs or hspll modes, the situation is somewhat dif- ferent. since the oscillator may require a start-up time considerably longer than the fscm sample clock time, a false clock failure may be detected. to prevent this, the internal oscillator block is automatically configured as the device clock and functions until the primary clock is stable (the ost and pll timers have timed out). this is identical to two-speed start-up mode. once the primary clock is stable, the intrc returns to its role as the fscm source. as noted in section 26.4.1 special considerations for using two-speed start-up , it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. when the new power-managed mode is selected, the primary clock is disabled. oscfif cm output device clock output sample clock failure detected oscillator failure note: the device clock is normally at a much higher frequen cy than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test note: the same logic that prevents false oscillator failure interrupts on por, or wake from sleep, will also prevent the detection of the oscillators failure to start at all following these events. this can be avoided by monitoring the osts bit and using a timing routine to determine if the oscillator is taking too long to start. even so, no oscillator failure interrupt will be flagged. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 331 pic18f87j72 family 26.6 program verification and code protection for all devices in the pic18f87j72 family of devices, the on-chip program memory space is treated as a single block. code protection for this block is controlled by one configuration bit, cp0. this bit inhibits external reads and writes to the program memory space. it has no direct effect in normal execution mode. 26.6.1 configuration register protection the configuration registers are protected against untoward changes or reads in two ways. the primary protection is the write-once feature of the configuration bits, which prevents reconfiguration once the bit has been programmed during a power cycle. to safeguard against unpredictable events, configuration bit changes resulting from individual cell-level disruptions (such as esd events) will cause a parity error and trigger a device reset. the data for the configuration registers is derived from the flash configuration words in program memory. when the cp0 bit set, the source data for device configuration is also protected as a consequence. 26.7 in-circuit serial programming pic18f87j72 family microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 26.8 in-circuit debugger when the debug configuration bit is programmed to a 0 , the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? ide. when the microcontroller has this feature enabled, some resources are not available for general use. table 26-4 shows which resources are required by the background debugger. table 26-4: debugger resources i/o pins: rb6, rb7 stack: 2 levels program memory: 512 bytes data memory: 10 bytes downloaded from: http:///
pic18f87j72 family ds39979a-page 332 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 333 pic18f87j72 family 27.0 instruction set summary the pic18f87j72 family of devices incorporates the standard set of 75 pic18 core instructions, as well as an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software stack. the extended set is discussed later in this section. 27.1 standard instruction set the standard pic18 mcu instruction set adds many enhancements to the previous pic ? mcu instruction sets, while maintaining an easy migration from these pic mcu instruction sets. most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: byte-oriented operations bit-oriented operations literal operations control operations the pic18 instruction set summary in table 27-2 lists byte-oriented , bit-oriented , literal and control operations. table 27-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by f) 2. the destination of the result (specified by d) 3. the accessed memory (specified by a) the file register designator, f, specifies which file reg- ister is to be used by the instruction. the destination designator, d, specifies where the result of the operation is to be placed. if d is zero, the result is placed in the wreg register. if d is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by f) 2. the bit in the file register (specified by b) 3. the accessed memory (specified by a) the bit field designator, b, selects the number of the bit affected by the operation, while the file register desig- nator, f, represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: a literal value to be loaded into a file register (specified by k) the desired fsr register to load the literal value into (specified by f) no operand required (specified by ) the control instructions may use some of the following operands: a program memory address (specified by n) the mode of the call or return instructions (specified by s) the mode of the table read and table write instructions (specified by m) no operand required (specified by ) all instructions are a single word, except for four double-word instructions. these instructions were made double-word to contain the required information in 32 bits. in the second word, the 4 msbs are 1 s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . the double-word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 ? s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 ? s. two-word branch instructions (if true) would take 3 ? s. figure 27-1 shows the general formats that the instruc- tions can have. all examples use the convention nnh to represent a hexadecimal number. the instruction set summary, shown in table 27-2, lists the standard instructions recognized by the microchip mpasm tm assembler. section 27.1.1 standard instruction set provides a description of each instruction. downloaded from: http:///
pic18f87j72 family ds39979a-page 334 preliminary ? 2010 microchip technology inc. table 27-1: opcode field descriptions field description a ram access bit: a = 0 : ram location in access ram (bsr register is ignored) a = 1 : ram bank is specified by bsr register bbb bit address within an 8-bit file register (0 to 7). bsr bank select register. used to select the current ram bank. c, dc, z, ov, n alu status bits: c arry, d igit c arry, z ero, ov erflow, n egative. d destination select bit: d = 0 : store result in wreg d = 1 : store result in file register f dest destination: either the wreg register or the specified register file location. f 8-bit register file address (00h to ff h), or 2-bit fsr designator (0h to 3h). f s 12-bit register file address (000h to fffh). this is the source address. f d 12-bit register file address (000h to ff fh). this is the destination address. gie global interrupt enable bit. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label label name. mm the mode of the tblptr register for the table read and table write instructions. only used with table read and table write instructions: * no change to register (such as tblptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tblptr with table reads and writes) n the relative address (2s complement number) for relative branch instructions or the direct address for call/branch and return instructions. pc program counter. pcl program counter low byte. pch program counter high byte. pclath program counter high byte latch. pclatu program counter upper byte latch. pd power-down bit. prodh product of multiply high byte. prodl product of multiply low byte. s fast call/return mode select bit: s = 0 : do not update into/from shadow registers s = 1 : certain registers loaded into/from shadow registers (fast mode) tblptr 21-bit table pointer (points to a program memory location). tablat 8-bit table latch. to time-out bit. tos top-of-stack. u unused or unchanged. wdt watchdog timer. wreg working register (accumulator). x dont care ( 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. z s 7-bit offset value for indirect addressing of register files (source). z d 7-bit offset value for indirect addressing of register files (destination). { } optional argument. [text] indicates an indexed address. (text) the contents of text . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 335 pic18f87j72 family [expr] specifies bit n of the register indicated by the pointer expr . ? assigned to. < > register bit field. ? in the set of. italics user-defined term (font is courier new). table 27-1: opcode field descriptions (continued) field description downloaded from: http:///
pic18f87j72 family ds39979a-page 336 preliminary ? 2010 microchip technology inc. figure 27-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call , goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 7fh goto label 15 8 7 0 opcode s n<7:0> (literal) 15 12 11 0 1111 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 337 pic18f87j72 family table 27-2: pic18f87j72 family instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, af, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination) 2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 11 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0 . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if the program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. downloaded from: http:///
pic18f87j72 family ds39979a-page 338 preliminary ? 2010 microchip technology inc. bit-oriented operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, b, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 11 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffffffff ffff ffff ffff none none none none none 1, 2 1, 2 3, 4 3, 4 1, 2 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep nn n n n n n n n n, s n n s k s branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine 1st word 2nd word clear watchdog timer decimal adjust wreg go to address 1st word 2nd word no operation no operation pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnnnnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd 4 table 27-2: pic18f87j72 family instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0 . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if the program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 339 pic18f87j72 family literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw kk k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsr(f) 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 11 1 2 1 1 1 2 1 1 00000000 0000 1110 1111 0000 0000 0000 0000 0000 0000 11111011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 22 00000000 0000 0000 0000 0000 0000 0000 00000000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 27-2: pic18f87j72 family instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0 . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if the program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. downloaded from: http:///
pic18f87j72 family ds39979a-page 340 preliminary ? 2010 microchip technology inc. 27.1.1 standard instruction set addlw add literal to w syntax: addlw k operands: 0 ? k ? 255 operation: (w) + k ? w status affected: n, ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of w are added to the 8-bit literal k and the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example: addlw 15h before instruction w = 10h after instruction w = 25h addwf add w to f syntax: addwf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (w) + (f) ? dest status affected: n, ov, c, dc, z encoding: 0010 01da ffff ffff description: add w to register f. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: addwf reg, 0, 0 before instruction w = 17h reg = 0c2h after instruction w = 0d9h reg = 0c2h note: all pic18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. if a label is used, the instruction format then becomes: {label} i nstruction argument(s). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 341 pic18f87j72 family addwfc add w and carry bit to f syntax: addwfc f {,d {,a}} operands: 0 ? f ? 255 d ?? [0,1] a ?? [0,1] operation: (w) + (f) + (c) ? dest status affected: n,ov, c, dc, z encoding: 0010 00da ffff ffff description: add w, the carry flag and data memory location f. if d is 0 , the result is placed in w. if d is 1 , the result is placed in data memory location f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: addwfc reg, 0, 1 before instruction carry bit = 1 reg = 02h w=4 d h after instruction carry bit = 0 reg = 02h w = 50h andlw and literal with w syntax: andlw k operands: 0 ? k ? 255 operation: (w) .and. k ? w status affected: n, z encoding: 0000 1011 kkkk kkkk description: the contents of w are anded with the 8-bit literal k. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example: andlw 05fh before instruction w=a 3 h after instruction w = 03h downloaded from: http:///
pic18f87j72 family ds39979a-page 342 preliminary ? 2010 microchip technology inc. andwf and w with f syntax: andwf f {,d {,a}} operands: 0 ? f ? 255 d ?? [0,1] a ?? [0,1] operation: (w) .and. (f) ? dest status affected: n, z encoding: 0001 01da ffff ffff description: the contents of w are anded with register f. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: andwf reg, 0, 0 before instruction w = 17h reg = c2h after instruction w = 02h reg = c2h bc branch if carry syntax: bc n operands: -128 ? n ? 127 operation: if carry bit is 1 , (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is 1 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example: here bc 5 before instruction pc = address (here) after instruction if carry = 1 ; pc = address (here + 12) if carry = 0 ; pc = address (here + 2) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 343 pic18f87j72 family bcf bit clear f syntax: bcf f, b {,a} operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: 0 ? f status affected: none encoding: 1001 bbba ffff ffff description: bit b in register f is cleared. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example: bcf flag_reg, 7, 0 before instruction flag_reg = c7h after instruction flag_reg = 47h bn branch if negative syntax: bn n operands: -128 ? n ? 127 operation: if negative bit is 1 , (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is 1 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example: here bn jump before instruction pc = address (here) after instruction if negative = 1 ; pc = address (jump) if negative = 0 ; pc = address (here + 2) downloaded from: http:///
pic18f87j72 family ds39979a-page 344 preliminary ? 2010 microchip technology inc. bnc branch if not carry syntax: bnc n operands: -128 ? n ? 127 operation: if carry bit is 0 , (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is 0 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example: here bnc jump before instruction pc = address (here) after instruction if carry = 0 ; pc = address (jump) if carry = 1 ; pc = address (here + 2) bnn branch if not negative syntax: bnn n operands: -128 ? n ? 127 operation: if negative bit is 0 , (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is 0 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example: here bnn jump before instruction pc = address (here) after instruction if negative = 0 ; pc = address (jump) if negative = 1 ; pc = address (here + 2) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 345 pic18f87j72 family bnov branch if not overflow syntax: bnov n operands: -128 ? n ? 127 operation: if overflow bit is 0 , (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is 0 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example: here bnov jump before instruction pc = address (here) after instruction if overflow = 0 ; pc = address (jump) if overflow = 1 ; pc = address (here + 2) bnz branch if not zero syntax: bnz n operands: -128 ? n ? 127 operation: if zero bit is 0 , (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is 0 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example: here bnz jump before instruction pc = address (here) after instruction if zero = 0 ; pc = address (jump) if zero = 1 ; pc = address (here + 2) downloaded from: http:///
pic18f87j72 family ds39979a-page 346 preliminary ? 2010 microchip technology inc. bra unconditional branch syntax: bra n operands: -1024 ? n ? 1023 operation: (pc) + 2 + 2n ? pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2s complement number 2n to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation example: here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: bsf f, b {,a} operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: 1 ? f status affected: none encoding: 1000 bbba ffff ffff description: bit b in register f is set. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example: bsf flag_reg, 7, 1 before instruction flag_reg = 0ah after instruction flag_reg = 8ah downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 347 pic18f87j72 family btfsc bit test file, skip if clear syntax: btfsc f, b {,a} operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit b in register f is 0 , then the next instruction is skipped. if bit b is 0 , then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfsc: : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0 ; pc = address (true) if flag<1> = 1 ; pc = address (false) btfss bit test file, skip if set syntax: btfss f, b {,a} operands: 0 ? f ? 255 0 ? b < 7 a ?? [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit b in register f is 1 , then the next instruction is skipped. if bit b is 1 , then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: herefalse true btfss: : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0 ; pc = address (false) if flag<1> = 1 ; pc = address (true) downloaded from: http:///
pic18f87j72 family ds39979a-page 348 preliminary ? 2010 microchip technology inc. btg bit toggle f syntax: btg f, b {,a} operands: 0 ? f ? 255 0 ? b < 7 a ?? [0,1] operation: (f ) ? f status affected: none encoding: 0111 bbba ffff ffff description: bit b in data memory location f is inverted. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example: btg portc, 4, 0 before instruction: portc = 0111 0101 [75h] after instruction: portc = 0110 0101 [65h] bov branch if overflow syntax: bov n operands: -128 ? n ? 127 operation: if overflow bit is 1 , (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is 1 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example: here bov jump before instruction pc = address (here) after instruction if overflow = 1 ; pc = address (jump) if overflow = 0 ; pc = address (here + 2) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 349 pic18f87j72 family bz branch if zero syntax: bz n operands: -128 ? n ? 127 operation: if zero bit is 1 , (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is 1 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example: here bz jump before instruction pc = address (here) after instruction if zero = 1 ; pc = address (jump) if zero = 0 ; pc = address (here + 2) call subroutine call syntax: call k {,s} operands: 0 ? k ? 1048575 s ?? [0,1] operation: (pc) + 4 ? tos, k ? pc<20:1>; if s = 1 (w) ? ws, (status) ? statuss, (bsr) ? bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 11101111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2-mbyte memory range. first, return address (pc+ 4) is pushed onto the return stack. if s = 1 , the w, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if s = 0 , no update occurs. then, the 20-bit value k is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal k<7:0>, push pc to stack read literal k<19:8>, write to pc no operation no operation no operation no operation example: here call there,1 before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = w bsrs = bsr statuss = status downloaded from: http:///
pic18f87j72 family ds39979a-page 350 preliminary ? 2010 microchip technology inc. clrf clear f syntax: clrf f {,a} operands: 0 ? f ? 255 a ?? [0,1] operation: 000h ? f, 1 ? z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example: clrf flag_reg,1 before instruction flag_reg = 5ah after instruction flag_reg = 00h clrwdt clear watchdog timer syntax: clrwdt operands: none operation: 000h ? wdt, 000h ? wdt postscaler, 1 ? to , 1 ? pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the post- scaler of the wdt. status bits, to and pd , are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 00h wdt postscaler = 0 to = 1 pd = 1 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 351 pic18f87j72 family comf complement f syntax: comf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: f ? dest status affected: n, z encoding: 0001 11da ffff ffff description: the contents of register f are complemented. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: comf reg, 0, 0 before instruction reg = 13h after instruction reg = 13h w=e c h cpfseq compare f with w, skip if f = w syntax: cpfseq f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (f) C (w), skip if (f) = (w) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location f to the contents of w by performing an unsigned subtraction. if f = w , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfseq reg, 0 nequal : equal : before instruction pc address = here w= ? reg = ? after instruction if reg = w; pc = address (equal) if reg ? w; pc = address (nequal) downloaded from: http:///
pic18f87j72 family ds39979a-page 352 preliminary ? 2010 microchip technology inc. cpfsgt compare f with w, skip if f > w syntax: cpfsgt f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (f) C ?? w), skip if (f) > (w) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location f to the contents of the w by performing an unsigned subtraction. if the contents of f are greater than the contents of wreg , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfsgt reg, 0 ngreater : greater : before instruction pc = address (here) w= ? after instruction if reg ? w; pc = address (greater) if reg ? w; pc = address (ngreater) cpfslt compare f with w, skip if f < w syntax: cpfslt f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (f) C ?? w), skip if (f) < (w) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location f to the contents of w by performing an unsigned subtraction. if the contents of f are less than the contents of w, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfslt reg, 1 nless : less : before instruction pc = address (here) w= ? after instruction if reg < w; pc = address (less) if reg ? w; pc = address (nless) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 353 pic18f87j72 family daw decimal adjust w register syntax: daw operands: none operation: if [w<3:0> > 9] or [dc = 1 ], then (w<3:0>) + 6 ? w<3:0>; else (w<3:0>) ? w<3:0> if [w<7:4> > 9] or [c = 1 ], then (w<7:4>) + 6 ? w<7:4>; c = ? 1 ; else (w<7:4>) ? w<7:4> status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in w, resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register w process data write w example 1: daw before instruction w=a 5 h c= 0 dc = 0 after instruction w = 05h c= 1 dc = 0 example 2: before instruction w=c e h c= 0 dc = 0 after instruction w = 34h c= 1 dc = 0 decf decrement f syntax: decf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) C 1 ? dest status affected: c, dc, n, ov, z encoding: 0000 01da ffff ffff description: decrement register f. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: decf cnt, 1, 0 before instruction cnt = 01h z= 0 after instruction cnt = 00h z= 1 downloaded from: http:///
pic18f87j72 family ds39979a-page 354 preliminary ? 2010 microchip technology inc. decfsz decrement f, skip if 0 syntax: decfsz f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) C 1 ? dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register f are decremented. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f. if the result is 0 , the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here decfsz cnt, 1, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt C 1 if cnt = 0 ; pc = address (continue) if cnt ? 0 ; pc = address (here + 2) dcfsnz decrement f, skip if not 0 syntax: dcfsnz f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) C 1 ? dest, skip if result ? 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register f are decremented. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f. if the result is not 0 , the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here dcfsnz temp, 1, 0 zero : nzero : before instruction temp = ? after instruction temp = temp C 1, if temp = 0 ; pc = address (zero) if temp ? 0 ; pc = address (nzero) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 355 pic18f87j72 family goto unconditional branch syntax: goto k operands: 0 ? k ? 1048575 operation: k ? pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 11101111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2-mbyte memory range. the 20-bit value k is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal k<7:0>, no operation read literal k<19:8>, write to pc no operation no operation no operation no operation example: goto there after instruction pc = address (there) incf increment f syntax: incf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest status affected: c, dc, n, ov, z encoding: 0010 10da ffff ffff description: the contents of register f are incremented. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: incf cnt, 1, 0 before instruction cnt = ffh z= 0 c= ? dc = ? after instruction cnt = 00h z= 1 c= 1 dc = 1 downloaded from: http:///
pic18f87j72 family ds39979a-page 356 preliminary ? 2010 microchip technology inc. incfsz increment f, skip if 0 syntax: incfsz f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register f are incremented. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f. if the result is 0 , the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here incfsz cnt, 1, 0 nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0 ; pc = address (zero) if cnt ? 0 ; pc = address (nzero) infsnz increment f, skip if not 0 syntax: infsnz f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest, skip if result ? 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register f are incremented. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f. if the result is not 0 , the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here infsnz reg, 1, 0 zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg ? 0 ; pc = address (nzero) if reg = 0 ; pc = address (zero) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 357 pic18f87j72 family iorlw inclusive or literal with w syntax: iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? w status affected: n, z encoding: 0000 1001 kkkk kkkk description: the contents of w are ored with the eight-bit literal k. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example: iorlw 35h before instruction w=9 a h after instruction w=b f h iorwf inclusive or w with f syntax: iorwf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (w) .or. (f) ? dest status affected: n, z encoding: 0001 00da ffff ffff description: inclusive or w with register f. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: iorwf result, 0, 1 before instruction result = 13h w = 91h after instruction result = 13h w = 93h downloaded from: http:///
pic18f87j72 family ds39979a-page 358 preliminary ? 2010 microchip technology inc. lfsr load fsr syntax: lfsr f, k operands: 0 ? f ? 2 0 ? k ? 4095 operation: k ? fsrf status affected: none encoding: 11101111 11100000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal k is loaded into the file select register pointed to by f. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal k msb process data write literal k msb to fsrfh decode read literal k lsb process data write literal k to fsrfl example: lfsr 2, 3abh after instruction fsr2h = 03h fsr2l = abh movf move f syntax: movf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: f ? dest status affected: n, z encoding: 0101 00da ffff ffff description: the contents of register f are moved to a destination dependent upon the status of d. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f. location f can be anywhere in the 256-byte bank. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write w example: movf reg, 0, 0 before instruction reg = 22h w= f f h after instruction reg = 22h w = 22h downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 359 pic18f87j72 family movff move f to f syntax: movff f s ,f d operands: 0 ? f s ? 4095 0 ? f d ? 4095 operation: (f s ) ? f d status affected: none encoding: 1st word (source) 2nd word (destin.) 11001111 ffffffff ffffffff ffff s ffff d description: the contents of source register f s are moved to destination register f d . location of source f s can be anywhere in the 4096-byte data space (000h to fffh) and location of destination f d can also be anywhere from 000h to fffh. either source or destination can be w (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register f (src) process data no operation decode no operation no dummy read no operation write register f (dest) example: movff reg1, reg2 before instruction reg1 = 33h reg2 = 11h after instruction reg1 = 33h reg2 = 33h movlb move literal to low nibble in bsr syntax: movlw k operands: 0 ? k ? 255 operation: k ? bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the eight-bit literal k is loaded into the bank select register (bsr). the value of bsr<7:4> always remains 0 regardless of the value of k 7 :k 4 . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write literal k to bsr example: movlb 5 before instruction bsr register = 02h after instruction bsr register = 05h downloaded from: http:///
pic18f87j72 family ds39979a-page 360 preliminary ? 2010 microchip technology inc. movlw move literal to w syntax: movlw k operands: 0 ? k ? 255 operation: k ? w status affected: none encoding: 0000 1110 kkkk kkkk description: the eight-bit literal k is loaded into w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example: movlw 5ah after instruction w=5 a h movwf move w to f syntax: movwf f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (w) ? f status affected: none encoding: 0110 111a ffff ffff description: move data from w to register f. location f can be anywhere in the 256-byte bank. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example: movwf reg, 0 before instruction w=4 f h reg = ffh after instruction w=4 f h reg = 4fh downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 361 pic18f87j72 family mullw multiply literal with w syntax: mullw k operands: 0 ? k ? 255 operation: (w) x k ? prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of w and the 8-bit literal k. the 16-bit result is placed in the prodh:prodl register pair. prodh contains the high byte. w is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write registers prodh: prodl example: mullw 0c4h before instruction w= e 2 h prodh = ? prodl = ? after instruction w= e 2 h prodh = adh prodl = 08h mulwf multiply w with f syntax: mulwf f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (w) x (f) ? prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of w and the register file location f. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both w and f are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write registers prodh: prodl example: mulwf reg, 1 before instruction w= c 4 h reg = b5h prodh = ? prodl = ? after instruction w= c 4 h reg = b5h prodh = 8ah prodl = 94h downloaded from: http:///
pic18f87j72 family ds39979a-page 362 preliminary ? 2010 microchip technology inc. negf negate f syntax: negf f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (f ) + 1 ? f status affected: n, ov, c, dc, z encoding: 0110 110a ffff ffff description: location f is negated using twos complement. the result is placed in the data memory location f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example: negf reg, 1 before instruction reg = 0011 1010 [3ah] after instruction reg = 1100 0110 [c6h] nop no operation syntax: nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000xxxx 0000xxxx 0000xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example: none. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 363 pic18f87j72 family pop pop top of return stack syntax: pop operands: none operation: (tos) ? bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example: pop goto new before instruction tos = 0031a2h stack (1 level down) = 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: push operands: none operation: (pc + 2) ? tos status affected: none encoding: 0000 0000 0000 0101 description: the pc + 2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implementing a software stack by modifying tos and then pushing it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc + 2 onto return stack no operation no operation example: push before instruction tos = 345ah pc = 0124h after instruction pc = 0126h tos = 0126h stack (1 level down) = 345ah downloaded from: http:///
pic18f87j72 family ds39979a-page 364 preliminary ? 2010 microchip technology inc. rcall relative call syntax: rcall n operands: -1024 ? n ? 1023 operation: (pc) + 2 ? tos, (pc) + 2 + 2n ? pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc + 2) is pushed onto the stack. then, add the 2s complement number 2n to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal n push pc to stack process data write to pc no operation no operation no operation no operation example: here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here + 2) reset reset syntax: reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example: reset after instruction registers = reset value flags* = reset value downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 365 pic18f87j72 family retfie return from interrupt syntax: retfie {s} operands: s ? [0,1] operation: (tos) ? pc, 1 ? gie/gieh or peie/giel; if s = 1 , (ws) ? w, (statuss) ? status, (bsrs) ? bsr, pclatu, pclath are unchanged status affected: gie/gieh, peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low-priority global interrupt enable bit. if s = 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers w, status and bsr. if s = 0 , no update of these registers occurs. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example: retfie 1 after interrupt pc = tos w= w s bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to w syntax: retlw k operands: 0 ? k ? 255 operation: k ? w, (tos) ? pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight-bit literal k. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal k process data pop pc from stack, write to w no operation no operation no operation no operation example: call table ; w contains table ; offset value ; w now has ; table value : table addwf pcl ; w = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction w = 07h after instruction w = value of kn downloaded from: http:///
pic18f87j72 family ds39979a-page 366 preliminary ? 2010 microchip technology inc. return return from subroutine syntax: return {s} operands: s ? [0,1] operation: (tos) ? pc; if s = 1 , (ws) ? w, (statuss) ? status, (bsrs) ? bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if s= 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers w, status and bsr. if s = 0 , no update of these registers occurs. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example: return after instruction: pc = tos rlcf rotate left f through carry syntax: rlcf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<7>) ? c, (c) ? dest<0> status affected: c, n, z encoding: 0011 01da ffff ffff description: the contents of register f are rotated one bit to the left through the carry flag. if d is 0 , the result is placed in w. if d is 1 , the result is stored back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: rlcf reg, 0, 0 before instruction reg = 1110 0110 c= 0 after instruction reg = 1110 0110 w = 1100 1100 c= 1 c register f downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 367 pic18f87j72 family rlncf rotate left f (no carry) syntax: rlncf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<7>) ? dest<0> status affected: n, z encoding: 0100 01da ffff ffff description: the contents of register f are rotated one bit to the left. if d is 0 , the result is placed in w. if d is 1 , the result is stored back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: rlncf reg, 1, 0 before instruction reg = 1010 1011 after instruction reg = 0101 0111 register f rrcf rotate right f through carry syntax: rrcf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<0>) ? c, (c) ? dest<7> status affected: c, n, z encoding: 0011 00da ffff ffff description: the contents of register f are rotated one bit to the right through the carry flag. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: rrcf reg, 0, 0 before instruction reg = 1110 0110 c= 0 after instruction reg = 1110 0110 w = 0111 0011 c= 0 c register f downloaded from: http:///
pic18f87j72 family ds39979a-page 368 preliminary ? 2010 microchip technology inc. rrncf rotate right f (no carry) syntax: rrncf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<0>) ? dest<7> status affected: n, z encoding: 0100 00da ffff ffff description: the contents of register f are rotated one bit to the right. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f. if a is 0 , the access bank will be selected, overriding the bsr value. if a is 1 , then the bank will be selected as per the bsr value. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example 1: rrncf reg, 1, 0 before instruction reg = 1101 0111 after instruction reg = 1110 1011 example 2: rrncf reg, 0, 0 before instruction w=? reg = 1101 0111 after instruction w = 1110 1011 reg = 1101 0111 register f setf set f syntax: setf f {,a} operands: 0 ? f ? 255 a ?? [0,1] operation: ffh ? f status affected: none encoding: 0110 100a ffff ffff description: the contents of the specified register are set to ffh. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example: setf reg,1 before instruction reg = 5ah after instruction reg = ffh downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 369 pic18f87j72 family sleep enter sleep mode syntax: sleep operands: none operation: 00h ? wdt, 0 ? wdt postscaler, 1 ? to , 0 ? pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. the watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example: sleep before instruction to =? pd =? after instruction to = 1 ? pd = 0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from w with borrow syntax: subfwb f {,d {,a}} operands: 0 ?? f ?? 255 d ? [0,1] a ? [0,1] operation: (w) C (f) C (c ) ?? dest status affected: n, ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register f and carry flag (borrow) from w (2s complement method). if d is 0 , the result is stored in w. if d is 1 , the result is stored in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example 1: subfwb reg, 1, 0 before instruction reg = 3 w=2 c= 1 after instruction reg = ff w=2 c= 0 z= 0 n = 1 ; result is negative example 2: subfwb reg, 0, 0 before instruction reg = 2 w=5 c= 1 after instruction reg = 2 w=3 c= 1 z= 0 n = 0 ; result is positive example 3: subfwb reg, 1, 0 before instruction reg = 1 w=2 c= 0 after instruction reg = 0 w=2 c= 1 z = 1 ; result is zero n= 0 downloaded from: http:///
pic18f87j72 family ds39979a-page 370 preliminary ? 2010 microchip technology inc. sublw subtract w from literal syntax: sublw k operands: 0 ?? k ?? 255 operation: k C (w) ?? w status affected: n, ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: w is subtracted from the eight-bit literal k. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example 1: sublw 02h before instruction w = 01h c= ? after instruction w = 01h c= 1 ; result is positive z= 0 n= 0 example 2: sublw 02h before instruction w = 02h c= ? after instruction w = 00h c= 1 ; result is zero z= 1 n= 0 example 3: sublw 02h before instruction w = 03h c= ? after instruction w = ffh ; (2s complement) c= 0 ; result is negative z= 0 n= 1 subwf subtract w from f syntax: subwf f {,d {,a}} operands: 0 ?? f ?? 255 d ? [0,1] a ? [0,1] operation: (f) C (w) ?? dest status affected: n, ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract w from register f (2s complement method). if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example 1: subwf reg, 1, 0 before instruction reg = 3 w=2 c= ? after instruction reg = 1 w=2 c = 1 ; result is positive z= 0 n= 0 example 2: subwf reg, 0, 0 before instruction reg = 2 w=2 c= ? after instruction reg = 2 w=0 c = 1 ; result is zero z= 1 n= 0 example 3: subwf reg, 1, 0 before instruction reg = 1 w=2 c= ? after instruction reg = ffh ;(2s complement) w=2 c = 0 ; result is negative z= 0 n= 1 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 371 pic18f87j72 family subwfb subtract w from f with borrow syntax: subwfb f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) C (w) C (c ) ?? dest status affected: n, ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract w and the carry flag (borrow) from register f (2s complement method). if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example 1: subwfb reg, 1, 0 before instruction reg = 19h (0001 1001) w =0dh (0000 1101) c= 1 after instruction reg = 0ch (0000 1011) w =0dh (0000 1101) c= 1 z= 0 n= 0 ; result is positive example 2: subwfb reg, 0, 0 before instruction reg = 1bh (0001 1011) w =1ah (0001 1010) c= 0 after instruction reg = 1bh (0001 1011) w = 00h c= 1 z= 1 ; result is zero n= 0 example 3: subwfb reg, 1, 0 before instruction reg = 03h (0000 0011) w =0eh (0000 1101) c= 1 after instruction reg = f5h (1111 0100) ; [2s comp] w =0eh (0000 1101) c= 0 z= 0 n= 1 ; result is negative swapf swap f syntax: swapf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f<3:0>) ? dest<7:4>, (f<7:4>) ? dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of register f are exchanged. if d is 0 , the result is placed in w. if d is 1 , the result is placed in register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: swapf reg, 1, 0 before instruction reg = 53h after instruction reg = 35h downloaded from: http:///
pic18f87j72 family ds39979a-page 372 preliminary ? 2010 microchip technology inc. tblrd table read syntax: tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) ? tablat; tblptr C no change if tblrd *+, (prog mem (tblptr)) ? tablat; (tblptr) + 1 ? tblptr if tblrd *-, (prog mem (tblptr)) ? tablat; (tblptr) C 1 ? tblptr if tblrd +*, (tblptr) + 1 ? tblptr; (prog mem (tblptr)) ? tablat status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. tblptr<0> = 0 :least significant byte of program memory word tblptr<0> = 1 :most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (continued) example 1: tblrd *+ ; before instruction tablat = 55h tblptr = 00a356h memory(00a356h) = 34h after instruction tablat = 34h tblptr = 00a357h example 2: tblrd +* ; before instruction tablat = aah tblptr = 01a357h memory(01a357h) = 12h memory(01a358h) = 34h after instruction tablat = 34h tblptr = 01a358h downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 373 pic18f87j72 family tblwt table write syntax: tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) ? holding register; tblptr C no change if tblwt*+, (tablat) ? holding register; (tblptr) + 1 ? tblptr if tblwt*-, (tablat) ? holding register; (tblptr) C 1 ? tblptr if tblwt+*, (tblptr) + 1 ? tblptr; (tablat) ? holding register status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction uses the 3 lsbs of tblptr to determine which of the 8 holding registers the tablat is written to. the holding registers are used to program the contents of program memory (p.m.). (refer to section 6.0 memory organization for additional details on programming flash memory.) the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0 :least significant byte of program memory word tblptr[0] = 1 :most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register) tblwt table write (continued) example 1: tblwt *+; before instruction tablat = 55h tblptr = 00a356h holding register (00a356h) = ffh after instructions (table write completion) tablat = 55h tblptr = 00a357h holding register (00a356h) = 55h example 2: tblwt +*; before instruction tablat = 34h tblptr = 01389ah holding register (01389ah) = ffh holding register (01389bh) = ffh after instruction (table write completion) tablat = 34h tblptr = 01389bh holding register (01389ah) = ffh holding register (01389bh) = 34h downloaded from: http:///
pic18f87j72 family ds39979a-page 374 preliminary ? 2010 microchip technology inc. tstfsz test f, skip if 0 syntax: tstfsz f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if f = 0 , the next instruction fetched during the current instruction execution is discarded and a nop is executed, making this a two-cycle instruction. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here tstfsz cnt, 1 nzero : zero : before instruction pc = address (here) after instruction if cnt = 00h, pc = address (zero) if cnt ? 00h, pc = address (nzero) xorlw exclusive or literal with w syntax: xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ?? w status affected: n, z encoding: 0000 1010 kkkk kkkk description: the contents of w are xored with the 8-bit literal k. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example: xorlw 0afh before instruction w=b 5 h after instruction w=1 a h downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 375 pic18f87j72 family xorwf exclusive or w with f syntax: xorwf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (w) .xor. (f) ?? dest status affected: n, z encoding: 0001 10da ffff ffff description: exclusive or the contents of w with register f. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in the register f. if a is 0 , the access bank is selected. if a is 1 , the bsr is used to select the gpr bank. if a is 0 and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: xorwf reg, 1, 0 before instruction reg = afh w=b 5 h after instruction reg = 1ah w=b 5 h downloaded from: http:///
pic18f87j72 family ds39979a-page 376 preliminary ? 2010 microchip technology inc. 27.2 extended instruction set in addition to the standard 75 instructions of the pic18 instruction set, the pic18f87j72 family of devices also provides an optional extension to the core cpu func- tionality. the added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of indexed literal offset addressing for many of the standard pic18 instructions. the additional features of the extended instruction set are enabled by default on unprogrammed devices. users must properly set or clear the xinst configura- tion bit during programming to enable or disable these features. the instructions in the extended set can all be classified as literal operations, which either manipulate the file select registers, or use them for indexed addressing. two of the instructions, addfsr and subfsr , each have an additional special instantiation for using fsr2. these versions ( addulnk and subulnk ) allow for automatic return after execution. the extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly c. among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. these include: dynamic allocation and deallocation of software stack space when entering and leaving subroutines function pointer invocation software stack pointer manipulation manipulation of variables located in a software stack a summary of the instructions in the extended instruc- tion set is provided in table 27-3. detailed descriptions are provided in section 27.2.2 extended instruction set . the opcode field descriptions in table 27-1 (page 334) apply to both the standard and extended pic18 instruction sets. 27.2.1 extended instruction syntax most of the extended instructions use indexed argu- ments, using one of the file select registers and some offset to specify a source or destination register. when an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets ([ ]). this is done to indicate that the argument is used as an index or offset. the mpasm? assembler will flag an error if it determines that an index or offset value is not bracketed. when the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. this is in addition to other changes in their syntax. for more details, see section 27.2.3.1 extended instruction syntax with standard pic18 commands . table 27-3: extensions to the pic18 instruction set note: the instruction set extension and the indexed literal offset addressing mode were designed for optimizing applications written in c; the user may likely never use these instructions directly in assembler. the syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. note: in the past, square brackets have been used to denote optional arguments in the pic18 and earlier instruction sets. in this text and going forward, optional arguments are denoted by braces ({ }). mnemonic, operands description cycles 16-bit instruction word status affected msb lsb addfsr addulnk callw movsf movss pushl subfsr subulnk f, k k z s , f d z s , z d k f, k k add literal to fsr add literal to fsr2 and return call subroutine using wreg move z s (source) to 1st word f d (destination) 2nd word move z s (source) to 1st word z d (destination) 2nd word store literal at fsr2, decrement fsr2 subtract literal from fsr subtract literal from fsr2 and return 12 2 2 2 1 1 2 11101110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzzffff 1zzz xzzz kkkk ffkk 11kk kkkkkkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk none none none none none none none none downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 377 pic18f87j72 family 27.2.2 extended instruction set addfsr add literal to fsr syntax: addfsr f, k operands: 0 ? k ? 63 f ? [ 0, 1, 2 ] operation: fsr(f) + k ? fsr(f) status affected: none encoding: 1110 1000 ffkk kkkk description: the 6-bit literal k is added to the contents of the fsr specified by f. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to fsr example: addfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 0422h addulnk add literal to fsr2 and return syntax: addulnk k operands: 0 ? k ? 63 operation: fsr2 + k ? fsr2, (tos) ?? pc status affected: none encoding: 1110 1000 11kk kkkk description: the 6-bit literal k is added to the contents of fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be thought of as a special case of the addfsr instruction, where f = 3 (binary 11 ); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to fsr no operation no operation no operation no operation example: addulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 0422h pc = (tos) note: all pic18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. if a label is used, the instruction format then becomes: {lab el} instruction argument(s). downloaded from: http:///
pic18f87j72 family ds39979a-page 378 preliminary ? 2010 microchip technology inc. callw subroutine call using wreg syntax: callw operands: none operation: (pc + 2) ? tos, (w) ? pcl, (pclath) ? pch, (pclatu) ? pcu status affected: none encoding: 0000 0000 0001 0100 description first, the return address (pc + 2) is pushed onto the return stack. next, the contents of w are written to pcl; the existing value is discarded. then, the contents of pclath and pclatu are latched into pch and pcu, respectively. the second cycle is executed as a nop instruction while the new next instruction is fetched. unlike call , there is no option to update w, status or bsr. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read wreg push pc to stack no operation no operation no operation no operation no operation example: here callw before instruction pc = address (here) pclath = 10h pclatu = 00h w = 06h after instruction pc = 001006h tos = address (here + 2) pclath = 10h pclatu = 00h w = 06h movsf move indexed to f syntax: movsf [z s ], f d operands: 0 ? z s ? 127 0 ? f d ? 4095 operation: ((fsr2) + z s ) ? f d status affected: none encoding: 1st word (source) 2nd word (destin.) 11101111 1011ffff 0zzzffff zzzz s ffff d description: the contents of the source register are moved to destination register f d . the actual address of the source register is determined by adding the 7-bit literal offset z s , in the first word, to the value of fsr2. the address of the destination register is specified by the 12-bit literal f d in the second word. both addresses can be anywhere in the 4096-byte data space (000h to fffh). the movsf instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode no operation no dummy read no operation write register f (dest) example: movsf [05h], reg2 before instruction fsr2 = 80h contents of 85h = 33h reg2 = 11h after instruction fsr2 = 80h contents of 85h = 33h reg2 = 33h downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 379 pic18f87j72 family movss move indexed to indexed syntax: movss [z s ], [z d ] operands: 0 ? z s ? 127 0 ? z d ? 127 operation: ((fsr2) + z s ) ? ((fsr2) + z d ) status affected: none encoding: 1st word (source) 2nd word (dest.) 11101111 1011xxxx 1zzzxzzz zzzz s zzzz d description the contents of the source register are moved to the destination register. the addresses of the source and destination registers are determined by adding the 7-bit literal offsets, z s or z d , respectively, to the value of fsr2. both registers can be located anywhere in the 4096-byte data memory space (000h to fffh). the movss instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. if the resultant destination address points to an indirect addressing register, the instruction will execute as a nop . words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode determine dest addr determine dest addr write to dest reg example: movss [05h], [06h] before instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 11h after instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 33h pushl store literal at fsr2, decrement fsr2 syntax: pushl k operands: 0 ??? k ? 255 operation: k ? (fsr2), fsr2 C 1 ? fsr2 status affected: none encoding: 1111 1010 kkkk kkkk description: the 8-bit literal k is written to the data memory address specified by fsr2. fsr2 is decremented by 1 after the operation. this instruction allows users to push values onto a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read k process data write to destination example: pushl 08h before instruction fsr2h:fsr2l = 01ech memory (01ech) = 00h after instruction fsr2h:fsr2l = 01ebh memory (01ech) = 08h downloaded from: http:///
pic18f87j72 family ds39979a-page 380 preliminary ? 2010 microchip technology inc. subfsr subtract literal from fsr syntax: subfsr f, k operands: 0 ? k ? 63 f ? [ 0, 1, 2 ] operation: fsrf C k ? fsrf status affected: none encoding: 1110 1001 ffkk kkkk description: the 6-bit literal k is subtracted from the contents of the fsr specified by f. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: subfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 03dch subulnk subtract literal from fsr2 and return syntax: subulnk k operands: 0 ? k ? 63 operation: fsr2 C k ? fsr2, (tos) ?? pc status affected: none encoding: 1110 1001 11kk kkkk description: the 6-bit literal k is subtracted from the contents of the fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be thought of as a special case of the subfsr instruction, where f = 3 (binary 11 ); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination no operation no operation no operation no operation example: subulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 03dch pc = (tos) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 381 pic18f87j72 family 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode in addition to eight new commands in the extended set, enabling the extended instruction set also enables indexed literal offset addressing ( section 6.6.1 indexed addressing with literal offset ). this has a significant impact on the way that many commands of the standard pic18 instruction set are interpreted. when the extended set is disabled, addresses embed- ded in opcodes are treated as literal memory locations: either as a location in the access bank (a = 0 ) or in a gpr bank designated by the bsr (a = 1 ). when the extended instruction set is enabled and a = 0 , however, a file register argument of 5fh or less is interpreted as an offset from the pointer value in fsr2 and not as a literal address. for practical purposes, this means that all instructions that use the access ram bit as an argument C that is, all byte-oriented and bit-oriented instructions, or almost half of the core pic18 instruc- tions C may behave differently when the extended instruction set is enabled. when the content of fsr2 is 00h, the boundaries of the access ram are essentially remapped to their original values. this may be useful in creating backward-compatible code. if this technique is used, it may be necessary to save the value of fsr2 and restore it when moving back and forth between c and assembly routines in order to preserve the stack pointer. users must also keep in mind the syntax requirements of the extended instruction set (see section 27.2.3.1 extended instruction syntax with standard pic18 commands ). although the indexed literal offset mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic opera- tion is carried out on the wrong register. users who are accustomed to the pic18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5fh or less are used for indexed literal offset addressing. representative examples of typical byte-oriented and bit-oriented instructions in the indexed literal offset mode are provided on the following page to show how execution is affected. the operand conditions shown in the examples are applicable to all instructions of these types. 27.2.3.1 extended instruction syntax with standard pic18 commands when the extended instruction set is enabled, the file register argument f in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value k. as already noted, this occurs only when f is less than or equal to 5fh. when an offset value is used, it must be indicated by square brackets ([ ]). as with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. omitting the brackets, or using a value greater than 5fh within the brackets, will generate an error in the mpasm? assembler. if the index argument is properly bracketed for indexed literal offset addressing, the access ram argument is never specified; it will automatically be assumed to be 0 . this is in contrast to standard operation (extended instruction set disabled), when a is set on the basis of the target address. declaring the access ram bit in this mode will also generate an error in the mpasm assembler. the destination argument d functions as before. in the latest versions of the mpasm assembler, language support for the extended instruction set must be explicitly invoked. this is done with either the command line option, /y , or the pe directive in the source listing. 27.2.4 considerations when enabling the extended instruction set it is important to note that the extensions to the instruc- tion set may not be beneficial to all users. in particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. additionally, the indexed literal offset addressing mode may create issues with legacy applications written to the pic18 assembler. this is because instructions in the legacy code may attempt to address registers in the access bank below 5fh. since these addresses are interpreted as literal offsets to fsr2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. when porting an application to the pic18f87j72 family, it is very important to consider the type of code. a large, re-entrant application that is written in c and would benefit from efficient compilation will do well when using the instruction set extensions. legacy applications that heavily use the access bank will most likely not benefit from using the extended instruction set. note: enabling the pic18 instruction set exten- sion may cause legacy applications to behave erratically or fail entirely. downloaded from: http:///
pic18f87j72 family ds39979a-page 382 preliminary ? 2010 microchip technology inc. addwf add w to indexed (indexed literal offset mode) syntax: addwf [k] {,d} operands: 0 ? k ? 95 d ? [0,1] operation: (w) + ((fsr2) + k) ? dest status affected: n, ov, c, dc, z encoding: 0010 01d0 kkkk kkkk description: the contents of w are added to the contents of the register indicated by fsr2, offset by the value k. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read k process data write to destination example: addwf [ofst] ,0 before instruction w = 17h ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 20h after instruction w = 37h contents of 0a2ch = 20h bsf bit set indexed (indexed literal offset mode) syntax: bsf [k], b operands: 0 ? f ? 95 0 ? b ? 7 operation: 1 ? ((fsr2) + k) status affected: none encoding: 1000 bbb0 kkkk kkkk description: bit b of the register indicated by fsr2, offset by the value k, is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example: bsf [flag_ofst], 7 before instruction flag_ofst = 0ah fsr2 = 0a00h contents of 0a0ah = 55h after instruction contents of 0a0ah = d5h setf set indexed (indexed literal offset mode) syntax: setf [k] operands: 0 ? k ? 95 operation: ffh ? ((fsr2) + k) status affected: none encoding: 0110 1000 kkkk kkkk description: the contents of the register indicated by fsr2, offset by k, are set to ffh. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read k process data write register example: setf [ofst] before instruction ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 00h after instruction contents of 0a2ch = ffh downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 383 pic18f87j72 family 27.2.5 special considerations with microchip mplab ? ide tools the latest versions of microchips software tools have been designed to fully support the extended instruction set for the pic18f87j72 family. this includes the mplab c18 c compiler, mpasm assembly language and mplab integrated development environment (ide). when selecting a target device for software development, mplab ide will automatically set default configuration bits for that device. the default setting for the xinst configuration bit is 1 , enabling the extended instruction set and indexed literal offset addressing. for proper execution of applications developed to take advantage of the extended instruction set, xinst must be set during programming. to develop software for the extended instruction set, the user must enable support for the instructions and the indexed addressing mode in their language tool(s). depending on the environment being used, this may be done in several ways: a menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project a command line option a directive in the source code these options vary between different compilers, assemblers and development environments. users are encouraged to review the documentation accompany- ing their development systems for the appropriate information. downloaded from: http:///
pic18f87j72 family ds39979a-page 384 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 385 pic18f87j72 family 28.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: integrated development environment - mplab ? ide software compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families simulators - mplab sim software simulator emulators - mplab real ice? in-circuit emulator in-circuit debuggers - mplab icd 3 - pickit? 3 debug express device programmers - pickit? 2 programmer - mplab pm3 device programmer low-cost demonstration/development boards, evaluation kits, and starter kits 28.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color-coded context a multiple project manager customizable data windows with direct edit of contents high-level source code debugging mouse over variable inspection drag and drop variables from source to watch windows extensive on-line help integration of select third party tools, such as iar c compilers the mplab ide allows you to: edit your source files (either c or assembly) one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. downloaded from: http:///
pic18f87j72 family ds39979a-page 386 preliminary ? 2010 microchip technology inc. 28.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchips pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 28.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchips pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 28.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user-defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process 28.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 28.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire device instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 387 pic18f87j72 family 28.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 28.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchips next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineers pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables. 28.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chips most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineers pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 28.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineers pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with users guide, lessons, tutorial, compiler and mplab ide software. downloaded from: http:///
pic18f87j72 family ds39979a-page 388 preliminary ? 2010 microchip technology inc. 28.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchips flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchips powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break- point, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with users guide, lessons, tutorial, compiler and mplab ide software. 28.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 28.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 389 pic18f87j72 family 29.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +100c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any digital only i/o pin or mclr with respect to v ss (except v dd ) ........................................... -0.3v to 5.6v voltage on any combined digital and analog pin with respect to v ss (except v dd and mclr )...... -0.3v to (v dd + 0.3v) voltage on v ddcore with respect to v ss ................................................................................................... -0.3v to 2.75v voltage on v dd with respect to v ss ........................................................................................................... -0.3v to 3.6v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ..............................................................................................................................250 ma maximum output current sunk by porta<7:6> and any portb and portc i/o pins.........................................25 ma maximum output current sunk by any portd, porte and portj i/o pins ..........................................................8 ma maximum output current sunk by porta<5:0> and any portf, portg and porth i/o pins ............................2 m a maximum output current sourced by porta<7:6> and any portb and portc i/o pins ...................................25 ma maximum output current sourced by any portd, porte and portj i/o pins .....................................................8 ma maximum output current sourced by porta<5:0> and any portf, portg and porth i/o pins .......................2 ma maximum current sunk by ? all ports combined.......................................................................................................200 ma voltage on afe sv dd ............................................................................................................................... .................7.0v afe digital inputs and outputs with respect to sav ss ..................................................................-0.6v to (sv dd + 0.6v) afe analog input with respect to sav ss ...................................................................................................... ....-6v to +6v afe v ref input with respect to sav ss .........................................................................................-0.6v to (sv dd + 0.6v) esd on the afe analog inputs (hbm (2) ,mm (3) ) ............................................................................................ 7.0 kv, 400v esd on all other afe pins (hbm (2) ,mm (3) ) ................................................................................................... 7.0 kv, 400v note 1: power dissipation is calculated as follows: pdis = v dd x {i dd C ? i oh } + ? {(v dd C v oh ) x i oh } + ? (v ol x i ol ) 2: human body model for esd testing. 3: machine model for esd testing. ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the devi ce at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. downloaded from: http:///
pic18f87j72 family ds39979a-page 390 preliminary ? 2010 microchip technology inc. figure 29-1: voltage-frequency graph, regulator enabled (industrial) (1) figure 29-2: voltage-frequency graph, regulator disabled (industrial) (1,2) frequency voltage (v dd ) 4.0v 2.0v 48 mhz 3.5v 3.0v 2.5v 3.6v 2.35v 0 note 1: when the on-chip regulator is enabled, its bor circuit will automatically trigger a device reset before v dd reaches a level at which full-speed operation is not possible. 8 mhz pic18f8xj72 frequency voltage (v ddcore ) 3.00v 2.00v 48 mhz 2.75v 2.50v 2.25v 2.7v 8 mhz 2.35v note 1: when the on-chip voltage regulator is disabled, v dd and v ddcore must be maintained so that v ddcore ?? v dd ?? 3.6v. pic18f8xj72 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 391 pic18f87j72 family 29.1 dc characteristics: supply voltage pic18f87j72 family (industrial) pic18f87j72 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min typ max units conditions d001 v dd supply voltage v ddcore 2.0 3.63.6 vv envreg tied to v ss envreg tied to v dd d001b v ddcore external supply for microcontroller core 2.0 2.70 v envreg tied to v ss d001c av dd analog supply voltage v dd C 0.3 v dd + 0.3 v d001d av ss analog ground potential v ss C 0.3 v ss + 0.3 v d002 v dr ram data retention voltage (1) 1.5 v d003 v por v dd start voltage to ensure internal power-on reset signal 0 . 7v s e e section 5.3 power-on reset (por) for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 v/ms see section 5.3 power-on reset (por) for details d005 v bor brown-out reset voltage 1 . 8v note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. downloaded from: http:///
pic18f87j72 family ds39979a-page 392 preliminary ? 2010 microchip technology inc. 29.2 dc characteristics: power-down and supply current pic18f87j72 family (industrial) pic18f87j72 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. device typ max units conditions power-down current (i pd ) (1) all devices 0.5 1.4 ? a -40c v dd = 2.0v (4) ( sleep mode) 0.1 1.4 ? a+ 2 5 c 0.8 6 ? a+ 6 0 c 5.5 10.2 ? a+ 8 5 c all devices 0.5 1.5 ? a -40c v dd = 2.5v (4) ( sleep mode) 0.1 1.5 ? a+ 2 5 c 18 ? a+ 6 0 c 6.8 12.6 ? a+ 8 5 c all devices 2.9 7 ? a -40c v dd = 3.3v (5) ( sleep mode) 3.6 7 ? a+ 2 5 c 4.1 10 ? a+ 6 0 c 9.6 19 ? a+ 8 5 c note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to +7 0c. extended temperature crystals are available at a much higher cost. 4: voltage regulator is disabled (envreg = 0 , tied to v ss ). 5: voltage regulator is enabled (envreg = 1 , tied to v dd , regslp = 1 ). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 393 pic18f87j72 family supply current (i dd ) (2,3) all devices 5 14.2 ? a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 31 khz ( rc_run mode, internal oscillator source) 5.5 14.2 ? a +25c 10 19.0 ? a +85c all devices 6.8 16.5 ? a -40c v dd = 2.5v, v ddcore = 2.5v (4) 7.6 16.5 ? a +25c 14 22.4 ? a +85c all devices 37 84 ? a -40c 51 84 ? a +25c v dd = 3.3v (5) 72 108 ? a +85c all devices 0.43 0.82 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 1 mhz ( rc_run mode, internal oscillator source) 0.47 0.82 ma +25c 0.52 0.95 ma +85c all devices 0.52 0.98 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) 0.57 0.98 ma +25c 0.63 1.10 ma +85c all devices 0.59 0.96 ma -40c 0.65 0.96 ma +25c v dd = 3.3v (5) 0.72 1.18 ma +85c all devices 0.88 1.45 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 4 mhz ( rc_run mode, internal oscillator source) 1 1.45 ma +25c 1.1 1.58 ma +85c all devices 1.2 1.72 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) 1.3 1.72 ma +25c 1.4 1.85 ma +85c all devices 1.3 2.87 ma -40c 1.4 2.87 ma +25c v dd = 3.3v (5) 1.5 2.96 ma +85c 29.2 dc characteristics: power-down and supply current pic18f87j72 family (industrial) (continued) pic18f87j72 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. device typ max units conditions note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. 4: voltage regulator is disabled (envreg = 0 , tied to v ss ). 5: voltage regulator is enabled (envreg = 1 , tied to v dd , regslp = 1 ). downloaded from: http:///
pic18f87j72 family ds39979a-page 394 preliminary ? 2010 microchip technology inc. supply current (i dd ) cont. (2,3) all devices 3 9.4 ? a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 31 khz ( rc_idle mode, internal oscillator source) 3.3 9.4 ? a +25c 8.5 17.2 ? a +85c all devices 4 10.5 ? a -40c v dd = 2.5v, v ddcore = 2.5v (4) 4.3 10.5 ? a +25c 10.3 19.5 ? a +85c all devices 34 82 ? a -40c 48 82 ? a +25c v dd = 3.3v (5) 69 105 ? a +85c all devices 0.33 0.75 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 1 mhz ( rc_idle mode, internal oscillator source) 0.37 0.75 ma +25c 0.41 0.84 ma +85c all devices 0.39 0.78 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) 0.42 0.78 ma +25c 0.47 0.91 ma +85c all devices 0.43 0.82 ma -40c 0.48 0.82 ma +25c v dd = 3.3v (5) 0.54 0.95 ma +85c all devices 0.53 0.98 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 4 mhz ( rc_idle mode, internal oscillator source) 0.57 0.98 ma +25c 0.61 1.12 ma +85c all devices 0.63 1.14 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) 0.67 1.14 ma +25c 0.72 1.25 ma +85c all devices 0.7 1.27 ma -40c 0.76 1.27 ma +25c v dd = 3.3v (5) 0.82 1.45 ma +85c 29.2 dc characteristics: power-down and supply current pic18f87j72 family (industrial) (continued) pic18f87j72 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. device typ max units conditions note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to +7 0c. extended temperature crystals are available at a much higher cost. 4: voltage regulator is disabled (envreg = 0 , tied to v ss ). 5: voltage regulator is enabled (envreg = 1 , tied to v dd , regslp = 1 ). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 395 pic18f87j72 family supply current (i dd ) cont. (2,3) all devices 0.17 0.35 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 1 mh z ( pri_run mode, ec oscillator) 0.18 0.35 ma +25c 0.20 0.42 ma +85c all devices 0.29 0.52 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) 0.31 0.52 ma +25c 0.34 0.61 ma +85c all devices 0.59 1.1 ma -40c 0.44 0.85 ma +25c v dd = 3.3v (5) 0.42 0.85 ma +85c all devices 0.70 1.25 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 4 mhz ( pri_run mode, ec oscillator) 0.75 1.25 ma +25c 0.79 1.36 ma +85c all devices 1.10 1.7 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) 1.10 1.7 ma +25c 1.12 1.82 ma +85c all devices 1.55 1.95 ma -40c 1.47 1.89 ma +25c v dd = 3.3v (5) 1.54 1.92 ma +85c all devices 9.9 14.8 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) f osc = 48 mh z ( pri_run mode, ec oscillator) 9.5 14.8 ma +25c 10.1 15.2 ma +85c all devices 13.3 23.2 ma -40c 12.2 22.7 ma +25c v dd = 3.3v (5) 12.1 22.7 ma +85c 29.2 dc characteristics: power-down and supply current pic18f87j72 family (industrial) (continued) pic18f87j72 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. device typ max units conditions note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. 4: voltage regulator is disabled (envreg = 0 , tied to v ss ). 5: voltage regulator is enabled (envreg = 1 , tied to v dd , regslp = 1 ). downloaded from: http:///
pic18f87j72 family ds39979a-page 396 preliminary ? 2010 microchip technology inc. supply current (i dd ) cont. (2,3) all devices 4.5 5.2 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) f osc = 4 mh z , 16 mhz internal ( pri_run hspll mode) 4.4 5.2 ma +25c 4.5 5.2 ma +85c all devices 5.7 6.7 ma -40c v dd = 3.3v (5) 5.5 6.3 ma +25c 5.3 6.3 ma +85c all devices 10.8 13.5 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) f osc = 10 mh z , 40 mhz internal ( pri_run hspll mode) 10.8 13.5 ma +25c 9.9 13.0 ma +85c all devices 13.4 24.1 ma -40c v dd = 3.3v (5) 12.3 20.2 ma +25c 11.2 19.5 ma +85c 29.2 dc characteristics: power-down and supply current pic18f87j72 family (industrial) (continued) pic18f87j72 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. device typ max units conditions note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to +7 0c. extended temperature crystals are available at a much higher cost. 4: voltage regulator is disabled (envreg = 0 , tied to v ss ). 5: voltage regulator is enabled (envreg = 1 , tied to v dd , regslp = 1 ). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 397 pic18f87j72 family supply current (i dd ) cont. (2,3) all devices 0.10 0.26 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 1 mhz ( pri_idle mode, ec oscillator) 0.07 0.18 ma +25c 0.09 0.22 ma +85c all devices 0.25 0.48 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) 0.13 0.30 ma +25c 0.10 0.26 ma +85c all devices 0.45 0.68 ma -40c 0.26 0.45 ma +25c v dd = 3.3v (5) 0.30 0.54 ma +85c all devices 0.36 0.60 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 4 mhz ( pri_idle mode, ec oscillator) 0.33 0.56 ma +25c 0.35 0.56 ma +85c all devices 0.52 0.81 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) 0.45 0.70 ma +25c 0.46 0.70 ma +85c all devices 0.80 1.15 ma -40c 0.66 0.98 ma +25c v dd = 3.3v (5) 0.65 0.98 ma +85c all devices 5.2 6.5 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) f osc = 48 mhz ( pri_idle mode, ec oscillator) 4.9 5.9 ma +25c 3.4 4.5 ma +85c all devices 6.2 12.4 ma -40c 5.9 11.5 ma +25c v dd = 3.3v (5) 5.8 11.5 ma +85c 29.2 dc characteristics: power-down and supply current pic18f87j72 family (industrial) (continued) pic18f87j72 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. device typ max units conditions note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. 4: voltage regulator is disabled (envreg = 0 , tied to v ss ). 5: voltage regulator is enabled (envreg = 1 , tied to v dd , regslp = 1 ). downloaded from: http:///
pic18f87j72 family ds39979a-page 398 preliminary ? 2010 microchip technology inc. supply current (i dd ) cont. (2,3) all devices 18 35 a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 32 khz (3) ( sec_run mode, timer1 as clock) 19 35 a +25c 28 49 a +85c all devices 20 45 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 21 45 a +25c 32 61 a +85c all devices 0.06 0.11 ma -40c 0.07 0.11 ma +25c v dd = 3.3v (5) 0.09 0.15 ma +85c all devices 14 28 a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 32 khz (3) ( sec_idle mode, timer1 as clock) 15 28 a +25c 24 43 a +85c all devices 15 31 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 16 31 a +25c 27 50 a +85c all devices 0.05 0.10 ma -40c 0.06 0.10 ma +25c v dd = 3.3v (5) 0.08 0.14 ma +85c 29.2 dc characteristics: power-down and supply current pic18f87j72 family (industrial) (continued) pic18f87j72 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. device typ max units conditions note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to +7 0c. extended temperature crystals are available at a much higher cost. 4: voltage regulator is disabled (envreg = 0 , tied to v ss ). 5: voltage regulator is enabled (envreg = 1 , tied to v dd , regslp = 1 ). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 399 pic18f87j72 family d022 module differential currents ( ? i wdt , ? i oscb , ? i ad ) watchdog timer 2.1 7.0 ? a -40c v dd = 2.0v, v ddcore = 2.0v (4) 2.2 7.0 ? a +25c 4.3 9.5 ? a +85c 3.0 8.0 ? a -40c v dd = 2.5v, v ddcore = 2.5v (4) 3.1 8.0 ? a +25c 5.5 10.4 ? a +85c 5.9 12.1 ? a -40c v dd = 3.3v 6.2 12.1 ? a +25c 6.9 13.6 ? a +85c d024 ( ? i lcd ) lcd module 2 (6,7) 5 a +25c v dd = 2.0v resistive ladder cpen = 0 ; cksel<1:0> = 00 ; cs<1:0> = 10 ; lp<3:0> = 0100 2.7 (6,7) 5 a +25c v dd = 2.5v 3.5 (6,7) 7 a +25c v dd = 3.0v 16 (7) 25 a +25c v dd = 2.0v charge pump bias<2:0> = 111 ; cpen = 1 ; cksel<1:0> = 11 ; cs<1:0> = 10 17 (7) 25 a +25c v dd = 2.5v 24 (7) 40 a +25c v dd = 3.0v d025 ( ? i oscb ) rtcc + timer1 osc. with 32 khz crystal (6) 0.9 4.0 ? a -10c v dd = 2.0v, v ddcore = 2.0v (4) 32 khz on timer1 (3) 1.0 4.5 ? a +25c 1.1 4.5 ? a +85c 1.1 4.5 ? a -10c v dd = 2.5v, v ddcore = 2.5v (4) 32 khz on timer1 (3) 1.2 5.0 ? a +25c 1.2 5.0 ? a +85c 1.6 6.5 ? a -10c v dd = 3.3v 32 khz on timer1 (3) 1.6 6.5 ? a +25c 2.1 8.0 ? a +85c d026 ( ? i ad ) a/d converter 3.0 10.0 ? a -40c to +85c v dd = 2.0v, v ddcore = 2.0v (4) a/d on, not converting 3.0 10.0 ? a -40c to +85c v dd = 2.5v, 29.2 dc characteristics: power-down and supply current pic18f87j72 family (industrial) (continued) pic18f87j72 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. device typ max units conditions note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. 4: voltage regulator is disabled (envreg = 0 , tied to v ss ). 5: voltage regulator is enabled (envreg = 1 , tied to v dd , regslp = 1 ). downloaded from: http:///
pic18f87j72 family ds39979a-page 400 preliminary ? 2010 microchip technology inc. 29.3 dc characteristics: pic18f87j72 family (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ? +85c for industrial param no. symbol characteristic min max units conditions v il input low voltage all i/o ports: d030 with ttl buffer v ss 0.15 v dd vv dd < 3.3v d030a 0.8 v 3.3v ? v dd ?? 3.6v d031 with schmitt trigger buffer v ss 0.2 v dd v d031a rc3 and rc4 only v ss 0.3 v dd vi 2 c? enabled d031b v ss 0.8 v smbus d032 mclr v ss 0.2 v dd v d033 osc1 v ss 0.3 v dd v hs, hspll modes d033a osc1 v ss 0.2 v dd v ec, ecpll modes d034 t13cki v ss 0.3 v v ih input high voltage i/o ports (not 5.5v tolerant): d040 with ttl buffer 0.25 v dd + 0.8v v dd vv dd < 3.3v d040a 2.0 v dd 3.3v ? v dd ?? 3.6v d041 with schmitt trigger buffer 0.8 v dd v dd v d041a rc3 and rc4 only 0.7 v dd v dd vi 2 c enabled d041b 2.1 v dd vsmbus i/o ports (5.5v tolerant): with ttl buffer 0.25 v dd + 0.8v 5.5 v v dd < 3.3v 2.0 5.5 v 3.3v ? v dd ?? 3.6v with schmitt trigger buffer 0.8 v dd 5.5 v d042 mclr 0.8 v dd v dd v d043 osc1 0.7 v dd v dd v hs, hspll modes d043a d044 osc1 t13cki 0.8 v dd 1.6 v dd v dd vv ec, ecpll modes i il input leakage current (1) d060 i/o ports with analog functions 200 na v ss ?? v pin ?? v dd , pin at high-impedance digital only i/o ports 200 na v ss ?? v pin ?? 5.5v, pin at high-impedance d061 mclr ? 1 ? avss ?? v pin ?? v dd d063 osc1 ? 1 ? avss ?? v pin ?? v dd i pu weak pull-up current d070 i purb portb weak pull-up current 80 400 ? av dd = 3.3v, v pin = v ss note 1: negative current is defined as current sourced by the pin. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 401 pic18f87j72 family 29.4 dc characteristics: ctmu current source specifications v ol output low voltage d080 i/o ports: porta, portf, portg, 0.4 v i ol = 2 ma, v dd = 3.3v, -40 ? c to +85 ? c portd, porte 0.4 v i ol = 3.4 ma, v dd = 3.3v, -40 ? c to +85 ? c portb, portc 0.4 v i ol = 3.4 ma, v dd = 3.3v, -40 ? c to +85 ? c d083 osc2/clko (ec, ecpll modes) 0 . 4 v i ol = 1.6 ma, v dd = 3.3v, -40 ? c to +85 ? c v oh output high voltage (1) d090 i/o ports: v porta, portf, portg 2.4 v i oh = -2 ma, v dd = 3.3v, -40 ? c to +85 ? c portd, porte 2.4 v i oh = -2 ma, v dd = 3.3v, -40 ? c to +85 ? c portb, portc 2.4 v i oh = -2 ma, v dd = 3.3v, -40 ? c to +85 ? c d092 osc2/clko (intosc, ec, ecpll modes) 2.4 v i oh = -1 ma, v dd = 3.3v, -40 ? c to +85 ? c capacitive loading specs on output pins d100 (4) cosc2 osc2 pin 15 pf in hs mode when external clock is used to drive osc1 d101 c io all i/o pins and osc2 50 pf to meet the ac timing specifications d102 c b scl, sda 400 pf i 2 c? specification dc characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ (1) max units conditions i out 1 ctmu current source, base range 550 na ctmuicon<1:0> = 01 i out 2 ctmu current source, 10x range 5 . 5 ? a ctmuicon<1:0> = 10 i out 3 ctmu current source, 100x range 5 5 ? a ctmuicon<1:0> = 11 note 1: nominal value at center point of current trim range (ctmuicon<7:2> = 000000 ). 29.3 dc characteristics: pic18f87j72 family (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ? +85c for industrial param no. symbol characteristic min max units conditions note 1: negative current is defined as current sourced by the pin. downloaded from: http:///
pic18f87j72 family ds39979a-page 402 preliminary ? 2010 microchip technology inc. table 29-1: memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ? max units conditions program flash memory d130 e p cell endurance 10k e/w -40 ? c to +85 ? c d131 v pr v dd for read v min 3 . 6vv min = minimum operating voltage d132b v pew voltage for self-timed erase or write operations v dd v ddcore 2.35 2.25 3.6 2.7 vv envreg tied to v dd envreg tied to v ss d133a t iw self-timed write cycle time 2.8 ms d133b t ie self-timed block erased cycle time 3 3m s d134 t retd characteristic retention 20 year provided no other specifications are violated d135 i ddp supply current during programming 31 4m a d140 t we writes per erase cycle 1 for each physical address ? data in typ column is at 3.3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 403 pic18f87j72 family table 29-2: comparator specifications table 29-3: voltage reference specifications table 29-4: internal voltag e regulator specifications table 29-5: internal lcd voltag e regulator specifications operating conditions: 3.0v ? v dd ? 3.6v, -40c ? t a ? +85c (unless otherwise stated) param no. sym characteristics min typ max units comments d300 v ioff input offset voltage 5.0 25 mv d301 v icm input common-mode voltage 0 av dd C 1.5 v d302 cmrr common-mode rejection ratio 55 db d303 t resp response time (1) 1 5 04 0 0 n s d304 t mc 2 ov comparator mode change to output valid* 1 0 ? s note 1: response time measured with one comparator input at (av dd C 1.5)/2, while the other input transitions from v ss to v dd . operating conditions: 3.0v ? v dd ? 3.6v, -40c ? t a ? +85c (unless otherwise stated) param no. sym characteristics min typ max units comments d310 v res resolution v dd /24 v dd /32 lsb d311 vr aa absolute accuracy 1/2 lsb d312 vr ur unit resistor value (r) 2k ? 310 t set settling time (1) 10 ? s note 1: settling time measured while cvrr = 1 and cvr<3:0> transitions from 0000 to 1111 . operating conditions: -40c ? t a ? +85c (unless otherwise stated) param no. sym characteristics min typ max units comments v rgout regulator output voltage* 2.5 v c efc external filter capacitor value* 4.7 10 ? f capacitor must be low-esr, a low series resistance (< 5 ? ) operating conditions: 2.0v ? v dd ? 3.6v, -40c ? t a ? +85c (unless otherwise stated) param no. sym characteristics min typ max units comments c fly fly back capacitor 0.47 4.7 ? f capacitor must be low-esr v bias v pk - pk between lcdbias0 & lcdbias3 3.40 3.6 v bias<2:0> = 111 3.27 v bias<2:0> = 110 3.14 v bias<2:0> = 101 3.01 v bias<2:0> = 100 2.88 v bias<2:0> = 011 2.75 v bias<2:0> = 010 2.62 v bias<2:0> = 001 2.49 v bias<2:0> = 000 downloaded from: http:///
pic18f87j72 family ds39979a-page 404 preliminary ? 2010 microchip technology inc. 29.5 ac (timing) characteristics 29.5.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t13cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hh i g h rr i s e i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 405 pic18f87j72 family 29.5.2 timing conditions the temperature and voltages specified in table 29-6 apply to all timing specifications unless otherwise noted. figure 29-3 specifies the load conditions for the timing specifications. table 29-6: temperature and voltage specifications C ac figure 29-3: load conditions for device timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ?? +85c for industrial operating voltage v dd range as described in section 29.1 and section 29.3 . v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osc2/clko/ra6 and including d and e outputs as ports c l = 15 pf for osc2/clko/ra6 load condition 1 load condition 2 downloaded from: http:///
pic18f87j72 family ds39979a-page 406 preliminary ? 2010 microchip technology inc. 29.5.3 timing diagrams and specifications figure 29-4: external clock timing table 29-7: external clock timing requirements param. no. symbol characteristic min max units conditions 1a f osc external clki frequency (1) dc 48 mhz ec oscillator mode dc 10 ecpll oscillator mode oscillator frequency (1) 4 25 mhz hs oscillator mode 4 10 hspll oscillator mode 1t osc external clki period (1) 20.8 ns ec oscillator mode 100 ecpll oscillator mode oscillator period (1) 40.0 250 ns hs oscillator mode 100 250 hspll oscillator mode 2t cy instruction cycle time (1) 83.3 ns t cy = 4/f osc , industrial 3t os l, t os h external clock in (osc1) high or low time 10 ns hs oscillator mode 4t os r, t os f external clock in (osc1) rise or fall time 7.5 ns hs oscillator mode note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period for all configurations except pll. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limit s may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at min. values with an external clock applied to the osc1/clki pin. when an external clock input is used, the max. cycle time limit is dc (no clock) for all devices. osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 407 pic18f87j72 family table 29-8: pll clock timing specifications (v dd = 2.15v to 3.6v) table 29-9: internal rc accuracy (intosc and intrc sources) param no. sym characteristic min typ? max units conditions f10 f osc oscillator frequency range 4 10 mhz hs mode only f11 f sys on-chip vco system frequency 16 40 mhz hs mode only f12 t rc pll start-up time (lock time) 2 ms f13 ? clk clko stability (jitter) -2 +2 % ? data in typ column is at 3.3v, 25 ? c, unless otherwise stated. these parameters are for design guidance only and are not tested. pic18f87j72 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. device min typ max units conditions intosc accuracy @ freq = 8 mhz, 4 mhz, 2 mhz, 1 mhz, 500 khz, 250 khz, 125 khz, 31 khz (1) all devices -2 +/-1 2 % +25c v dd = 2.7-3.3v -5 5 % -10c to +85c v dd = 2.0-3.3v -10 +/-1 10 % -40c to +85c v dd = 2.0-3.3v intrc accuracy @ freq = 31 khz (1) all devices 21.7 40.3 khz -40c to +85c v dd = 2.0-3.3v note 1: the accuracy specification of the 31 khz clock is determined by which source is providing it at a given time. when intsrc (osctune<7>) is 1 , use the intosc accuracy specification. when intsrc is 0 , use the intrc accuracy specification. downloaded from: http:///
pic18f87j72 family ds39979a-page 408 preliminary ? 2010 microchip technology inc. figure 29-5: clko and i/o timing table 29-10: clko and i/o timing requirements param no. symbol characteristic min typ max units conditions 10 t os h2 ck losc1 ? to clko ? 7 52 0 0n s (note 1) 11 t os h2 ck hosc1 ? to clko ? 7 52 0 0n s (note 1) 12 t ck rc l k o r i s e t i m e 1 5 3 0 n s (note 1) 13 t ck f clko fall time 15 30 ns (note 1) 14 t ck l2 io vclko ? to port out valid 0.5 t cy + 20 ns 15 t io v2 ck h port in valid before clko ? 0.25 t cy + 25 ns 16 t ck h2 io i port in hold after clko ? 0n s 17 t os h2 io vosc1 ? (q1 cycle) to port out valid 50 150 ns 18 t os h2 io iosc1 ? (q2 cycle) to port input invalid (i/o in hold time) 100 ns 19 t io v2 os h port input valid to osc1 ?? (i/o in setup time) 0n s 20 t io r port output rise time 6 ns 21 t io f port output fall time 5 ns 22? t inp intx pin high or low time t cy n s 23? t rbp rb<7:4> change intx high or low time t cy n s ? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in ec mode, where clko output is 4 x t osc . note: refer to figure 29-3 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 409 pic18f87j72 family figure 29-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 29-11: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements param. no. symbol characteristic min typ max units conditions 30 t mc lmclr pulse width (low) 2 t cy 10 t cy (note 1) 31 t wdt watchdog timer time-out period (no postscaler) 3.4 4.0 4.6 ms 32 t ost oscillation start-up timer period 1024 t osc 1024 t osc t osc = osc1 period 33 t pwrt power-up timer period 45.8 65.5 85.2 ms 34 t ioz i/o high-impedance from mclr low or watchdog timer reset 2 s 38 t csd cpu start-up time 10 s 200 s voltage regulator enabled and put to sleep 39 t iobst time for intosc to stabilize 1 s note 1: to ensure device reset, mclr must be low for at least 2 t cy or 400 ? s, whichever is lower. v dd mclr internal por pwrt time-out oscillator time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 29-3 for load conditions. downloaded from: http:///
pic18f87j72 family ds39979a-page 410 preliminary ? 2010 microchip technology inc. figure 29-7: timer0 and timer1 external clock timings table 29-12: timer0 and timer1 external clock requirements param no. symbol characteristic min max units conditions 40 t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ns with prescaler 10 ns 41 t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ns with prescaler 10 ns 42 t t 0p t0cki period no prescaler t cy + 10 ns with prescaler greater of: 20 ns or (t cy + 40)/n n sn = p r e s c a l e value (1, 2, 4,..., 256) 45 t t 1h t13cki high time synchronous, no prescaler 0.5 t cy + 20 ns synchronous, with prescaler 10 ns asynchronous 30 ns 46 t t 1l t13cki low time synchronous, no prescaler 0.5 t cy + 5 ns synchronous, with prescaler 10 ns asynchronous 30 ns 47 t t 1p t13cki input period synchronous greater of: 20 ns or (t cy + 40)/n n sn = p r e s c a l e value (1, 2, 4, 8) asynchronous 60 ns f t 1 t13cki oscillator input frequency range dc 50 khz 48 t cke 2 tmr i delay from external t13cki clock edge to timer increment 2 t osc 7 t osc note: refer to figure 29-3 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t13cki tmr0 or tmr1 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 411 pic18f87j72 family figure 29-8: capture/compare/pwm timings (ccp1, ccp2 modules) table 29-13: capture/compare/pwm re quirements (ccp1, ccp2 modules) param no. symbol characteristic min max units conditions 50 t cc l ccpx input low time no prescaler 0.5 t cy + 20 ns with prescaler 10 ns 51 t cc h ccpx input high time no prescaler 0.5 t cy + 20 ns with prescaler 10 ns 52 t cc p ccpx input period 3 t cy + 40 n ns n = prescale value (1, 4 or 16) 53 t cc r ccpx output fall time 25 ns 54 t cc f ccpx output fall time 25 ns note: refer to figure 29-3 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) downloaded from: http:///
pic18f87j72 family ds39979a-page 412 preliminary ? 2010 microchip technology inc. figure 29-9: example spi master mode timing (cke = 0 ) table 29-14: example spi mode requirements (master mode, cke = 0 ) param no. symbol characteristic min max units conditions 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 20 ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ns 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 40 ns 75 t do r sdo data output rise time 25 ns 76 t do f sdo data output fall time 25 ns 78 t sc r sck output rise time (master mode) 25 ns 79 t sc f sck output fall time (master mode) 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge 50 ns note 1: requires the use of parameter #73a. sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - - 1 lsb in bit 6 - - - - 1 note: refer to figure 29-3 for load conditions. msb in downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 413 pic18f87j72 family figure 29-10: example spi master mode timing (cke = 1 ) table 29-15: example spi mode requirements (master mode, cke = 1 ) param. no. symbol characteristic min max units conditions 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 20 ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 40 ns 75 t do r sdo data output rise time 25 ns 76 t do f sdo data output fall time 25 ns 78 t sc r sck output rise time (master mode) 25 ns 79 t sc f sck output fall time (master mode) 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge 50 ns 81 t do v2 sc h, t do v2 sc l sdo data output setup to sck edge t cy n s note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 74 75, 76 78 80 msb 79 73 bit 6 - - - - - - 1 lsb in bit 6 - - - - 1 lsb note: refer to figure 29-3 for load conditions. msb in downloaded from: http:///
pic18f87j72 family ds39979a-page 414 preliminary ? 2010 microchip technology inc. figure 29-11: example spi slave mode timing (cke = 0 ) table 29-16: example spi mode requirements (slave mode timing, cke = 0 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss ? to sck ? or sck ? input 3 t cy n s 70a t ss l2wb ss to write to sspbuf 3 t cy n s 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ns 71a single byte 40 ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ns 72a single byte 40 ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ns 75 t do r sdo data output rise time 25 ns 76 t do f sdo data output fall time 25 ns 77 t ss h2 do zss ? to sdo output high-impedance 10 50 ns 78 t sc r sck output rise time (master mode) 25 ns 79 t sc f sck output fall time (master mode) 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge 50 ns 83 t sc h2 ss h, t sc l2 ss h ss ? after sck edge 1.5 t cy + 40 ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 msb lsb bit 6 - - - - - - 1 bit 6 - - - - 1 lsb in 83 note: refer to figure 29-3 for load conditions. msb in downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 415 pic18f87j72 family figure 29-12: example spi slave mode timing (cke = 1 ) table 29-17: example spi slave mode requirements (cke = 1 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss ? to sck ? or sck ? input 3 t cy n s 70a t ss l2wb ss to write to sspbuf 3 t cy n s 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ns 71a single byte 40 ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ns 72a single byte 40 ns (note 1) 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ns 75 t do r sdo data output rise time 25 ns 76 t do f sdo data output fall time 25 ns 77 t ss h2 do zss ? to sdo output high-impedance 10 50 ns 78 t sc r sck output rise time (master mode) 25 ns 79 t sc f sck output fall time (master mode) 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge 50 ns 82 t ss l2 do v sdo data output valid after ss ? edge 50 ns 83 t sc h2 ss h, t sc l2 ss h ss ? after sck edge 1.5 t cy + 40 ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 82 74 75, 76 msb bit 6 - - - - - - 1 lsb 77 bit 6 - - - - 1 lsb in 80 83 note: refer to figure 29-3 for load conditions. msb in downloaded from: http:///
pic18f87j72 family ds39979a-page 416 preliminary ? 2010 microchip technology inc. figure 29-13: i 2 c? bus start/stop bits timing table 29-18: i 2 c? bus start/stop bits requirements (slave mode) param. no. symbol characteristic min max units conditions 90 t su : sta start condition setup time 100 khz mode 4700 ns only relevant for repeated start condition 400 khz mode 600 91 t hd : sta start condition hold time 100 khz mode 4000 ns after this period, the first clock pulse is generated 400 khz mode 600 92 t su : sto stop condition setup time 100 khz mode 4700 ns 400 khz mode 600 93 t hd : sto stop condition hold time 100 khz mode 4000 ns 400 khz mode 600 note: refer to figure 29-3 for load conditions. 91 92 93 scl sda start condition stop condition 90 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 417 pic18f87j72 family figure 29-14: i 2 c? bus data timing table 29-19: i 2 c? bus data requirements (slave mode) param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s 400 khz mode 0.6 ? s mssp module 1.5 t cy 101 t low clock low time 100 khz mode 4.7 ? s 400 khz mode 1.3 ? s mssp module 1.5 t cy 102 t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 ? s 107 t su : dat data input setup time 100 khz mode 250 ns (note 2) 400 khz mode 100 ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode 3500 ns (note 1) 400 khz mode ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s d102 c b bus capacitive loading 400 pf note 1: as a transmitter, the device must provide this internal mini mum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode i 2 c? bus device can be used in a standard mode i 2 c bus system, but the requirement, t su : dat ? 250 ns, must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal . if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) , before the scl line is released. note: refer to figure 29-3 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out downloaded from: http:///
pic18f87j72 family ds39979a-page 418 preliminary ? 2010 microchip technology inc. figure 29-15: mssp i 2 c? bus start/stop bits timing waveforms table 29-20: mssp i 2 c? bus start/stop bits requirements figure 29-16: mssp i 2 c? bus data timing param. no. symbol characteristic min max units conditions 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ns only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1,2) 2(t osc )(brg + 1) 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ns after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1,2) 2(t osc )(brg + 1) 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ns 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1,2) 2(t osc )(brg + 1) 93 t hd : sto stop condition hold time 100 khz mode 2(t osc )(brg + 1) ns 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1,2) 2(t osc )(brg + 1) note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. 2: f osc must be at least 16 mhz for i 2 c bus operation at this speed. note: refer to figure 29-3 for load conditions. 91 93 scl sda start condition stop condition 90 92 note: refer to figure 29-3 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 419 pic18f87j72 family table 29-21: mssp i 2 c? bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) s 400 khz mode 2(t osc )(brg + 1) s 1 mhz mode (1,2) 2(t osc )(brg + 1) s 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) s 400 khz mode 2(t osc )(brg + 1) s 1 mhz mode (1,2) 2(t osc )(brg + 1) s 102 t r sda and scl rise time 100 khz mode 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1,2) 300 ns 103 t f sda and scl fall time 100 khz mode 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1,2) 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) s only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) s 1 mhz mode (1,2) 2(t osc )(brg + 1) s 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) s after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) s 1 mhz mode (1,2) 2(t osc )(brg + 1) s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 s 1 mhz mode (1,2) n s 107 t su : dat data input setup time 100 khz mode 250 ns (note 3) 400 khz mode 100 ns 1 mhz mode (1,2) n s 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) s 400 khz mode 2(t osc )(brg + 1) s 1 mhz mode (1,2) 2(t osc )(brg + 1) s 109 t aa output valid from clock 100 khz mode 3500 ns 400 khz mode 1000 ns 1 mhz mode (1,2) n s 110 t buf bus free time 100 khz mode 4.7 s time the bus must be free before a new trans- mission can start 400 khz mode 1.3 s 1 mhz mode (1,2) s d102 c b bus capacitive loading 400 pf legend: tbd = to be determined note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. 2: f osc must be at least 16 mhz for i 2 c bus operation at this speed. 3: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter #107 ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode), before the scl line is released. downloaded from: http:///
pic18f87j72 family ds39979a-page 420 preliminary ? 2010 microchip technology inc. figure 29-17: eusart/ausart synchronous transmission (master/slave) tim ing table 29-22: eusart/ausart synchronous transmission requirements figure 29-18: eusart/ausart synchronous receive (master/slave) timing table 29-23: eusart/ausart synchronous receive requirements param no. symbol characteristic min max units conditions 120 t ck h2 dt v sync xmit (master and slave) clock high to data out valid 40 ns 121 t ckrf clock out rise time and fall time (master mode) 20 ns 122 t dtrf data out rise time and fall time 20 ns param. no. symbol characteristic min max units conditions 125 t dt v2 ckl sync rcv (master and slave) data hold before ckx ? (dtx hold time) 10 ns 126 t ck l2 dtl data hold after ckx ? (dtx hold time) 15 ns 121 121 120 122 txx/ckx rxx/dtx pin pin note: refer to figure 29-3 for load conditions. 125 126 txx/ckx rxx/dtx pin pin note: refer to figure 29-3 for load conditions. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 421 pic18f87j72 family table 29-24: a/d converter characteristics: pic18f87j72 family (industrial) param no. sym characteristic min typ max units conditions a01 n r resolution 12 bit ? v ref ? 3.0v a03 e il integral linearity error <1 2.0 lsb ? v ref ? 3.0v a04 e dl differential linearity error <1 1.5 lsb ? v ref ? 3.0v a06 e off offset error <1 5 lsb ? v ref ? 3.0v a07 e gn gain error <1 3 lsb ? v ref ? 3.0v a10 monotonicity guaranteed (1) v ss ? v ain ? v ref a20 ? v ref reference voltage range (v refh C v refl ) 3 v dd C v ss v for 12-bit resolution a21 v refh reference voltage high v ss + 3.0v v dd + 0.3v v for 12-bit resolution a22 v refl reference voltage low v ss C 0.3v v dd C 3.0v v for 12-bit resolution a25 v ain analog input voltage v refl v refh v note 2 a30 z ain recommended impedance of analog voltage source 2 . 5k ? a50 i ref v ref input current (2) 5 150 ? a ? a during v ain acquisition. during a/d conversion cycle. note 1: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 2: v refh current is from the ra3/an3/v ref + pin or v dd , whichever is selected as the v refh source. v refl current is from the ra2/an2/v ref - pin or v ss , whichever is selected as the v refl source. downloaded from: http:///
pic18f87j72 family ds39979a-page 422 preliminary ? 2010 microchip technology inc. figure 29-19: a/d conversion timing table 29-25: a/d conversion requirements param no. symbol characteristic min max units conditions 130 t ad a/d clock period 0.8 12.5 (1) ? st osc based, v ref ? 3.0v 131 t cnv conversion time (not including acquisition time) (2) 13 14 t ad 132 t acq acquisition time (3) 1.4 ? s 135 t swc switching time from convert ? sample (note 4) 137 t dis discharge time 0.2 ? s note 1: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 2: adres registers may be read on the following t cy cycle. 3: the time for the holding capacitor to acquire the new input voltage wh en the voltage changes full scale after the conversion (v dd to v ss or v ss to v dd ). the source impedance (r s ) on the input channels is 50 ? . 4: on the following cycle of the device clock. 131 130 132 bsf adcon0, go q4 a/d clk (1) a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 11 10 9 3 2 1 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capa citor from the analog input. . . . . . . t cy 0 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 423 pic18f87j72 family table 29-26: dual-channel afe electrical characteristics electrical specifications: unless otherwise indicated: sav dd = 4.5 to 5.5v, sv dd = 2.7 to 5.5v, -40c < t a <+85c, mclk = 4 mhz, prescale = 1 , osr = 64, gain = 1 , dithering off, v in = -0.5, dbfs = 353 mv rms @ 50/60 hz parameters symbol min typical max units conditions internal voltage reference internal voltage reference to l e r a n c e v ref -2% 2.37 +2% v vrefext = 0 temperature coefficient tc ref 12 ppm/c vrefext = 0 output impedance zout ref 7 k ? sav dd = 5v, vrefext = 0 voltage reference input input capacitance 10 pf differential input voltage range (v ref + C v ref -) v ref 2.2 2.6 v v ref = (v ref + C v ref -), vrefext = 1 absolute voltage on refin+ pin v ref + 1.9 2.9 v vrefext = 1 absolute voltage on refin- pin v ref -- 0 . 30 . 3v adc performance resolution (no missing codes) 24 bits osr = 256 sampling frequency f s 125 1000 khz f s = dmclk = mclk/ (4 x prescale) output data rate f d 0.4882 31.25 ksps f d = drclk = dmclk/ osr = mclk/ (4 x prescale x osr) analog input absolute voltage on ch0+, ch0-, ch1+, ch1- pins chn+/- -1 +1 v all analog input channels, measured to savss (note 1) analog input leakage current a in 1 n a (note 2) differential input voltage range (chn+ C chn-) 500/gain mv (note 3) offset error (note 4) v os -3 +3 mv (note 5) offset error drift 3 ? v/c from -40c to +125c gain error (note 4) ge -0.4 % g = 1 -2.5 +2.5 % all gains gain error drift 1 ppm/c from -40c to +125c note 1: outside of this range, the adc accuracy is not specified. an extended input range of 6v can be ap plied continuously to the part with no risk of damage. 2: for these operating currents, the following bit settings apply: shutdown<1:0> = 00 , reset<1:0> = 00 , vrefext = 0 , clkext = 0 . 3: this specification implies that the adc output is valid over this entire differe ntial range and that there is no distortion or instability across this input range. dynamic performance is specified at -0.5 db below the maximum signal range, v in = -0.5 dbfs @ 50/60 hz = 353 mv rms , mv ref = 2.4v. 4: see appendix b.3 terminology and formulas for definitions. 5: applies to all gains. offset error is dependent on pga gain setting. 6: this parameter is established by characterization and is not 100% tested. 7: for proper operation and to keep adc accuracy, amclk should always be in the range of 1 to 5 mhz with boost bits off. with boost bits on, amclk should be in the range of 1 to 8.192 mhz. amclk = mclk/prescale. 8: for these operating currents, the following configuration bit settings apply: shutdown<1:0> = 11 , vrefext = 1 , clkext = 1 . downloaded from: http:///
pic18f87j72 family ds39979a-page 424 preliminary ? 2010 microchip technology inc. adc performance (continued) integral non-linearity (note 4) inl 15 ppm gain = 1 , dither = on input impedance z in 3 5 0k ? proportional to 1/amclk signal-to-noise and distortion ratio (notes 4, 6) sinad 90 db osr = 256, dither = on 7 8 d bo s r = 6 4 , dither = off total harmonic distortion (notes 4, 6) thd -101 db osr = 256, dither = on -82 db osr = 64, dither = off signal-to-noise ratio (notes 4, 6) snr 91 db osr = 256, dither = on 8 1 d bo s r = 6 4 , dither = off spurious free dynamic range (note 4) sfdr 103 db osr = 256, dither = on 8 3 d bo s r = 6 4 , dither = off crosstalk (50/60 hz) (note 4) ctalk -133 db osr = 256, dither = on ac power supply rejection ac psrr -77 db sav dd and sv dd = 5v + 1v pp @ 50/60 hz dc power supply rejection dc psrr -77 db sav dd and sv dd = 4.5 to 5.5v dc common-mode rejection ratio (note 4) cmrr -72 db v cm varies from -1v to +1v table 29-26: dual-channel afe electrical characteristics (continued) electrical specifications: unless otherwise indicated: sav dd = 4.5 to 5.5v, sv dd = 2.7 to 5.5v, -40c < t a <+85c, mclk = 4 mhz, prescale = 1 , osr = 64, gain = 1 , dithering off, v in = -0.5, dbfs = 353 mv rms @ 50/60 hz parameters symbol min typical max units conditions note 1: outside of this range, the adc accuracy is not specified. an extended input range of 6v can be ap plied continuously to the part with no risk of damage. 2: for these operating currents, the following bit settings apply: shutdown<1:0> = 00 , reset<1:0> = 00 , vrefext = 0 , clkext = 0 . 3: this specification implies that the adc output is valid over this entire differ ential range and that there is no distortion or instability across this input range. dynamic performance is specified at -0.5 db below the maximum signal range, v in = -0.5 dbfs @ 50/60 hz = 353 mv rms , mv ref = 2.4v. 4: see appendix b.3 terminology and formulas for definitions. 5: applies to all gains. offset error is dependent on pga gain setting. 6: this parameter is established by characterization and is not 100% tested. 7: for proper operation and to keep adc accuracy, amclk should always be in the ra nge of 1 to 5 mhz with boost bits off. with boost bits on, amclk should be in the range of 1 to 8.192 mhz. amclk = mclk/prescale. 8: for these operating currents, the following configuration bit settings apply: shutdown<1:0> = 11 , vrefext = 1 , clkext = 1 . downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 425 pic18f87j72 family oscillator input master clock frequency range mclk 1 16.384 mhz (note 7) power specifications operating voltage, analog sav dd 4.5 5.5 v operating voltage, digital sv dd 2.7 3.6 5.5 v operating current, analog (note 2) ai dd 2 2.8 boost<1:0> = 00 3.5 5.6 ma boost<1:0> = 11 operating current, digital di dd 0 . 6 50 . 9 m as v dd = 5v, mclk = 4 mhz 0 . 30 . 4m as v dd = 2.7v, mclk = 4 mhz 1 . 21 . 6m as v dd = 5v, mclk = 8.192 mhz shutdown current, analog i dds , a 1 as a v dd pin only (note 8) shutdown current, digital i dds , d 1 as v dd pin only (note 8) table 29-26: dual-channel afe electrical characteristics (continued) electrical specifications: unless otherwise indicated: sav dd = 4.5 to 5.5v, sv dd = 2.7 to 5.5v, -40c < t a <+85c, mclk = 4 mhz, prescale = 1 , osr = 64, gain = 1 , dithering off, v in = -0.5, dbfs = 353 mv rms @ 50/60 hz parameters symbol min typical max units conditions note 1: outside of this range, the adc accuracy is not specified. an extended input range of 6v can be ap plied continuously to the part with no risk of damage. 2: for these operating currents, the following bit settings apply: shutdown<1:0> = 00 , reset<1:0> = 00 , vrefext = 0 , clkext = 0 . 3: this specification implies that the adc output is valid over this entire differe ntial range and that there is no distortion or instability across this input range. dynamic performance is specified at -0.5 db below the maximum signal range, v in = -0.5 dbfs @ 50/60 hz = 353 mv rms , mv ref = 2.4v. 4: see appendix b.3 terminology and formulas for definitions. 5: applies to all gains. offset error is dependent on pga gain setting. 6: this parameter is established by characterization and is not 100% tested. 7: for proper operation and to keep adc accuracy, amclk should always be in the range of 1 to 5 mhz with boost bits off. with boost bits on, amclk should be in the range of 1 to 8.192 mhz. amclk = mclk/prescale. 8: for these operating currents, the following configuration bit settings apply: shutdown<1:0> = 11 , vrefext = 1 , clkext = 1 . downloaded from: http:///
pic18f87j72 family ds39979a-page 426 preliminary ? 2010 microchip technology inc. table 29-27: dual-channel af e serial peripheral in terface specifications electrical specifications: unless otherwise indicated, all parameters apply at sav dd = 4.5 to 5.5v, dv dd = 2.7 to 5.5v, -40c < t a <+85c, c load = 30 pf. parameters sym min typ max units conditions serial clock frequency f sck 2010 mhzmhz 4.5 ?? sv dd ?? 5.5 2.7 ?? sv dd ?? 5.5 cs setup time t css 2550 nsns 4.5 ?? sv dd ?? 5.5 2.7 ?? sv dd ?? 5.5 cs hold time t csh 50 100 nsns 4.5 ?? sv dd ?? 5.5 2.7 ?? sv dd ?? 5.5 cs disable time t csd 50 ns data setup time t su 5 10 nsns 4.5 ?? sv dd ?? 5.5 2.7 ?? sv dd ?? 5.5 data hold time t hd 1020 nsns 4.5 ?? sv dd ?? 5.5 2.7 ?? sv dd ?? 5.5 serial clock high time t hi 2550 nsns 4.5 ?? sv dd ?? 5.5 2.7 ?? sv dd ?? 5.5 serial clock low time t lo 2550 nsns 4.5 ?? dv dd ?? 5.5 2.7 ?? dv dd ?? 5.5 serial clock delay time t cld 50 ns serial clock enable time t cle 50 ns output valid from sck low t do 50 ns 2.7 ?? sv dd ?? 5.5 output hold time t ho 0n s (note 1) output disable time t dis 2550 nsns 4.5 ?? sv dd ?? 5.5 2.7 ?? sv dd ?? 5.5 (note 1) reset pulse width (reset )t mclr 100 ns 2.7 ?? sv dd ?? 5.5 data transfer time to dr (data ready) t dodr 50 ns 2.7 ?? sv dd ?? 5.5 data ready pulse low time t drp 1 / d m c l k s2 . 7 ?? sv dd ?? 5.5 schmitt trigger high-level input voltage v ih 1 0.7 sv dd s v dd + 1 v schmitt trigger low-level input voltage v il 1 -0.3 0.2 sv dd v hysteresis of schmitt trigger inputs (all digital inputs) v hys 300 mv low-level output voltage, sdoa pin v ol 0 . 4v i ol = +2.5 ma, sv dd = 5.0v low-level output voltage, dr pin v ol 0 . 4 v i ol = +1.25 ma, sv dd = 5.0v high-level output voltage, sdoa pin v oh sv dd C 0.5 v i oh = -2.5 ma, sv dd = 5.0v high-level output voltage, dr pin v oh sv dd C 0.5 v i oh = -1.25 ma, sv dd = 5.0v input leakage current i li 1 a c s a = sv dd , v in = sv ss or sv dd output leakage current i lo 1 a c s a = sv dd , v out = sv ss or sv dd internal capacitance (all inputs and outputs) c int 7p f t a = 25c, scka = 1.0 mhz, sv dd = 5.0v (note 1) note 1: this parameter is periodically sampled and is not 100% tested. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 427 pic18f87j72 family figure 29-20: serial output timing diagram figure 29-21: serial input timing diagram figure 29-22: data ready pulse timing diagram t csh t dis t hi t lo f sck cs sck sdo msb out lsb out dont care sdi mode 1,1 mode 0,0 t ho t do cs sck sdi lsb in msb in mode 1,1 mode 0,0 t css t su t hd t csd t csh t cld t cle sdo hi-z t hi t lo f sck dr sck sdo 1/drclk t dodr t drp downloaded from: http:///
pic18f87j72 family ds39979a-page 428 preliminary ? 2010 microchip technology inc. figure 29-23: specific timing diagrams cs v ih timing waveform for t dis hi-z 90% 10% t dis sdo scksdo t do timing waveform for t do downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 429 pic18f87j72 family 30.0 packaging information 30.1 package marking information 3 e 80-lead tqfp xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic18f86j72 -i/pt 1002017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e downloaded from: http:///
pic18f87j72 family ds39979a-page 430 preliminary ? 2010 microchip technology inc. 30.2 package details the following sections give the technical details of the packages.

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? 2010 microchip technology inc. preliminary ds39979a-page 433 pic18f87j72 family appendix a: revision history revision a (june 2010) original data sheet for the pic18f87j72 family devices. downloaded from: http:///
pic18f87j72 family ds39979a-page 434 preliminary ? 2010 microchip technology inc. appendix b: dual-channel, 24-bit afe reference b.1 introduction b.1.1 description the dual-channel analog front end (afe) contains two synchronous sampling delta-sigma analog-to-digital converters (adc), two pgas, phase delay compensa- tion block, internal voltage reference, modulator output block and high-speed 20 mhz spi compatible serial interface. the converters contain a proprietary dithering algorithm for reduced idle tones and improved thd. the internal register map contains 24-bit wide adc data words, as well as six writable control registers to program gain, oversampling ratio, phase, resolution, dithering, shutdown, reset and communication features. the communication is largely simplified with various continuous read modes that can be accessed by the dma of an external device, and with a separate data ready (dr) pin that can directly be connected to an irq input of an external microcontroller. the afe is capable of interfacing to a large variety of voltage and current sensors, including shunts, current transformers, rogowski coils and hall effect sensors. b.1.2 delta-sigma adc architecture the afe incorporates two delta-sigma adcs with a multi-bit architecture. a delta-sigma adc is an oversampling converter that incorporates a built-in modulator which is digitizing the quantity of charge integrated by the modulator loop. the quantizer is the block that is performing the analog-to-digital conversion. the quantizer is typically 1-bit or a simple comparator which helps to maintain the linearity performance of the adc (the dac structure is in this case inherently linear). multi-bit quantizers help to lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the osr which leads to better snr figures. however, typically, the linearity of such architectures is more difficult to achieve since the dac is no more simple to realize and its linearity limits the thd of such adcs. the 5-level quantizer is a flash adc composed of 4 comparators, arranged with equally spaced thresh- olds and a thermometer coding. the afe also includes proprietary, 5-level dac architecture that is inherently linear for improved thd figures. b.1.3 features two synchronous sampling 16/24-bit resolution delta-sigma a/d converters with proprietary multi-bit architecture 91 db sinad, -104 dbc thd (up to 35 th harmonic), 109 db sfdr for each channel programmable data rate of up to 64 ksps ultra low-power shutdown mode with <2 a -133 db crosstalk between the two channels low drift internal voltage reference: 12 ppm/c differential voltage reference input pins high gain pga on each channel (up to 32v/v) phase delay compensation between the two channels with 1 s time resolution separate modulator outputs for each channel high-speed addressable 20 mhz spi interface with mode 0,0 and 1,1 compatibility independent analog and digital power supplies 4.5v-5.5v sav dd , 2.7v-5.5v sv dd low-power consumption (14 mw typical at 5v) b.1.4 applications energy metering and power measurement automotive portable instrumentation medical and power monitoring downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 435 pic18f87j72 family figure b-1: dual-channel af e functional block diagram ch0+ ch0- ch1+ ch1- sdoa sdia scka dual-ds adc digital sinc 3 - + pga mclk clkia dr areset digital spi interface clock generation sinc 3 - + pga modulator amclk dmclk/drclk dmclk phase shifter phase<7:0> osr<1:0> pre<1:0> data_ch0<23:0> data_ch1<23:0> csa refin+/out+ refin- sav dd sav ss sv ss sv dd por av dd monitoring por modulator v ref + v ref - vrefext voltage reference v ref + - d-s d-s f sdn<1:0>, reset<1:0>, gain<7:0> analog downloaded from: http:///
pic18f87j72 family ds39979a-page 436 preliminary ? 2010 microchip technology inc. b.2 pin description b.2.1 afe reset (areset ) this pin is active-low and places the afe in a reset state when active. when areset = 0 , all registers are reset to their default value, no communication can take place and no clock is distributed to internal circuitry. this state is equivalent to a por state. since the default state of the adcs is on, the analog power consumption when areset = 0 is equivalent to when areset = 1 . only the digital power consumption is largely reduced because this current consumption is essentially dynamic and is reduced drastically when there is no clock running. all the analog biases are enabled during a reset, so that the part is fully operational just after a areset rising edge. this input is schmitt triggered. b.2.2 digital v dd (sv dd ) sv dd is the power supply pin for the afes digital cir- cuitry. this pin requires appropriate bypass capacitors and should be maintained between 2.7v and 5.5v for specified operation. b.2.3 analog v dd (sav dd ) av dd is the power supply pin for the afes analog cir- cuitry. this pin requires appropriate bypass capacitors and should be maintained to 5v 10% for specified operation. b.2.4 adc differential analog inputs (chn+/chn-) ch0-/ch0+ and ch1-/ch1+ are the two fully differential, analog voltage inputs for the delta-sigma adcs. the linear and specified region of the channels are dependent on the pga gain. this region corresponds to a differential voltage range of 500 mv/gain with v ref = 2.4v. the maximum absolute voltage, with respect to sav ss , for each chn+/- input pin is 1v with no distortion and 6v with no breaking after continuous voltage. b.2.5 analog ground (sav ss ) savss is the ground connection to internal analog circuitry (adcs, pga, voltage reference, por). to ensure accuracy and noise cancellation, this pin must be connected to the same ground as sv ss , preferably with a star connection. if an analog ground plane is available, it is recommended that this pin be tied to this plane of the pcb. this plane should also reference all other analog circuitry in the system. b.2.6 non-inverting reference input, internal reference output (refin+/out) this pin is the non-inverting side of the differential voltage reference input for both adcs or the internal voltage reference output. when vrefext = 1 , and an external voltage reference source can be used, the internal voltage ref- erence is disabled. when using an external differential voltage reference, it should be connected to its v ref + pin. when using an external single-ended reference, it should be connected to this pin. when vrefext = 0 , the internal voltage reference is enabled and connected to this pin through a switch. this voltage reference has minimal drive capability, and thus, needs proper buffering and bypass capacitances (10 f tantalum in parallel with 0.1 f ceramic) if used as a voltage source. for optimal performance, bypass capacitances should be connected between this pin and agnd at all times, even when the internal voltage reference is used. however, these capacitors are not mandatory to ensure proper operation. b.2.7 inverting reference input (refin-) this pin is the inverting side of the differential voltage reference input for both adcs. when using an external differential voltage reference, it should be connected to its v ref - pin. when using an external, single-ended voltage reference, or when vrefext = 0 (default) and using the internal voltage reference, this pin should be directly connected to savss. b.2.8 digital gr ound connection (sv ss ) svss is the ground connection to internal digital circuitry (sinc filters, oscillator, serial interface). to ensure accuracy and noise cancellation, svss must be connected to the same ground as savss, preferably with a star connection. if a digital ground plane is available, it is recommended that this pin be tied to this plane of the printed circuit board (pcb). this plane should also reference all other digital circuitry in the system. b.2.9 data ready (dr ) the data ready pin indicates if a new conversion result is ready to be read. the default state of this pin is high when dr_hizn = 1 and is high impedance when dr_hizn = 0 (default). after each conversion is finished, a low pulse will take place on the data ready pin to indicate the conversion result is ready as an interrupt. this pulse is synchronous with the master clock and has a defined and constant width. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 437 pic18f87j72 family the data ready pin is independent of the spi interface and acts like an interrupt output. the pin state is not latched and the pulse width (and period) are both deter- mined by the mclk frequency, oversampling rate and internal clock prescale settings. the dr pulse width is equal to one dmclk period and the frequency of the pulses is equal to drclk (see figure 29-22 in section 29.0 electrical characteristics of the data sheet). b.2.10 master clock input (clkia) clkia provides the master clock for the device. the typical clock frequency specified is 4 mhz. however, the clock frequency can be 1 mhz to 5 mhz without disturbing adc accuracy. with the current boost circuit enabled, the master clock can be used up to 8.192 mhz without disturbing adc accuracy. appropri- ate load capacitance should be connected to these pins for proper operation. b.2.11 chip select (csa ) this pin is the spi chip select that enables the serial communication. when this pin is high, no communication can take place. a chip select falling edge initiates the serial communication and a chip select rising edge terminates the communication. no communication can take place even when csa is low and when areset is low. this input is schmitt triggered. b.2.12 serial data clock (scka) this is the serial clock pin for spi communication. data is clocked into the device on the rising edge of sck. data is clocked out of the device on the falling edge of sck. the afe interface is compatible with both spi 0,0 and 1,1 modes. spi modes can only be changed during a reset. the maximum clock speed specified is 20 mhz when sv dd > 4.5v and 10 mhz otherwise. this input is schmitt triggered. b.2.13 serial data output (sdoa) this is the spi data output pin. data is clocked out of the device on the falling edge of sck. this pin stays high impedance during the first command byte. it also stays high impedance during the whole com- munication for write commands and when the csa pin is high or when the areset pin is low. this pin is active only when a read command is processed. each read is processed by a packet of 8 bits. b.2.14 serial data input (sdia) this is the spi data input pin. data is clocked into the device on the rising edge of sck. when cs is low, this pin is used to communicate with series of 8-bit commands. the interface is half-duplex (inputs and outputs do not happen at the same time). each communication starts with a chip select falling edge, followed by an 8-bit command word entered through the sdi pin. each command is either a read or a write command. toggling sdi during a read command has no effect. this input is schmitt triggered. note: this pin should not be left floating when the dr_hizn bit is low; a 10 k ? pull-up resistor connected to dv dd is recommended. downloaded from: http:///
pic18f87j72 family ds39979a-page 438 preliminary ? 2010 microchip technology inc. b.3 terminology and formulas this section defines the terms and formulas used throughout this data sheet. the following terms are defined: mclk C master clock amclk C analog master clock dmclk C digital master clock drclk C data rate clock osr C oversampling ratio offset error gain error integral non-linearity error signal-to-noise ratio (snr) signal-to-noise ratio and distortion (sinad) total harmonic distortion (thd) spurious-free dynamic range (sfdr) idle tones dithering crosstalk psrr cmrr adc reset mode hard reset mode (areset = 0) adc shutdown mode full shutdown mode b.3.1 mclk C master clock this is the fastest clock present in the device. this is the frequency of the clock input at the clkia. b.3.2 amclk C analog master clock this is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the config1 prescale<1:0> register bits. the ana- log portion includes the pgas and the two sigma-delta modulators. equation b-1: b.3.3 dmclk C digital master clock this is the clock frequency that is present on the digital portion of the device, after prescaling and division by 4. this is also the sampling frequency, that is the rate at which the modulator outputs are refreshed. each period of this clock corresponds to one sample and one modulator output. equation b-2: b.3.4 drclk C data rate clock this is the output data rate (i.e., the rate at which the adcs output new data). each new data is signaled by a data ready pulse on the dr pin. this data rate is depending on the osr and the prescaler with the following formula: equation b-3: since this is the output data rate, and since the decimation filter is a sinc (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. table b-2 describes the various combinations of osr and prescale and their associated amclk, dmclk and drclk rates. amclk mclk prescale ------------------------------ - = table b-1: oversampling ratio settings prescale (config1<15:14>) analog master clock prescale 00 amclk = mclk/1 (default) 01 amclk = mclk/2 10 amclk = mclk/4 11 amclk = mclk/8 dmclk amclk 4 -------------------- - mclk 4 prescale ? --------------------------------------- - == drclk dmclk osr ---------------------- amclk 4osr ? --------------------- mclk 4 osr prescale ? ? ---------------------------------------------------------- - === downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 439 pic18f87j72 family b.3.5 osr C oversampling ratio the ratio of the sampling frequency to the output data rate, osr = dmclk/drclk. the default osr is 64, or with mclk = 4 mhz, prescale = 1 , amclk = 4 mhz, f s = 1 mhz, f d = 15.625 ksps. the following bits in the config1 register are used to change the oversampling ratio (osr). b.3.6 offset error this is the error induced by the adc when the inputs are shorted together (vin = 0v). the specification incorporates both pga and adc offset contributions. this error varies with pga and osr settings. the offset is different on each channel and varies from chip to chip. this offset error can easily be calibrated out by a mcu with a subtraction. the offset is specified in mv. the offset on the dual-channel afe has a low temperature coefficient. b.3.7 gain error this is the error induced by the adc on the slope of the transfer function. it is the deviation expressed in per- cent compared to the ideal transfer function defined by equation b-15. the specification incorporates both pga and adc gain error contributions, but not the v ref contribution (it is measured with an external v ref ).this error varies with pga and osr settings. the gain error of the dual-channel afe has a low temperature coefficient. b.3.8 integral non-linearity error integral nonlinearity error is the maximum deviation of an adc transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the endpoints equal to zero. it is the maximum remaining error after calibration of offset and gain errors for a dc input signal. b.3.9 signal-to-noise ratio (snr) for the afe, the signal-to-noise ratio is a ratio of the output fundamental signal power to the noise power (not including the harmonics of the signal), when the input is a sine wave at a predetermined frequency. it is measured in db. usually, only the maximum signal to noise ratio is specified. the snr figure depends mainly on the osr and dither settings of the device. table b-2: device data rates in function of mclk, osr and prescale pre<1:0> osr<1:0> osr amclk dmclk drclk drclk (ksps) sinad (db) enob (bits) 1111 256 mclk/8 mclk/32 mclk/8192 0.4882 91.4 14.89 1110 128 mclk/8 mclk/32 mclk/4096 0.976 86.6 14.10 1101 64 mclk/8 mclk/32 mclk/2048 1.95 78.7 12.78 1100 32 mclk/8 mclk/32 mclk/1024 3.9 68.2 11.04 1011 256 mclk/4 mclk/16 mclk/4096 0.976 91.4 14.89 1010 128 mclk/4 mclk/16 mclk/2048 1.95 86.6 14.10 1001 64 mclk/4 mclk/16 mclk/1024 3.9 78.7 12.78 1000 32 mclk/4 mclk/16 mclk/512 7.8125 68.2 11.04 0111 256 mclk/2 mclk/8 mclk/2048 1.95 91.4 14.89 0110 128 mclk/2 mclk/8 mclk/1024 3.9 86.6 14.10 0101 64 mclk/2 mclk/8 mclk/512 7.8125 78.7 12.78 0100 32 mclk/2 mclk/8 mclk/256 15.625 68.2 11.04 0011 256 mclk mclk/4 mclk/1024 3.9 91.4 14.89 0010 128 mclk mclk/4 mclk/512 7.8125 86.6 14.10 0001 64 mclk mclk/4 mclk/256 15.625 78.7 12.78 0000 32 mclk mclk/4 mclk/128 31.25 68.2 11.04 note: for osr = 32 and 64, dither = 0 . for osr = 128 and 256, dither = 1 . table b-3: oversampling ratio settings config oversampling ratio (osr) osr<1:0> 00 32 01 64 (default) 10 128 11 256 downloaded from: http:///
pic18f87j72 family ds39979a-page 440 preliminary ? 2010 microchip technology inc. equation b-4: signal-to-noise ratio b.3.10 signal-to-noise ratio and distortion (sinad) the most important figure of merit for the analog performance of the adcs is the signal-to-noise and distortion (sinad) specification. signal-to-noise and distortion ratio is similar to signal-to-noise ratio, with the exception that you must include the harmonics power in the noise power calcu- lation. the sinad specification depends mainly on the osr and dither settings. equation b-5: sinad equation the calculated combination of snr and thd per the following formula also yields sinad: equation b-6: sinad, thd and snr relationship b.3.11 total harmonic distortion (thd) the total harmonic distortion is the ratio of the output harmonics power to the fundamental signal power for a sine wave input and is defined by the following equation. equation b-7: the thd calculation includes the first 35 harmonics for the afes specifications. the thd is usually only measured with respect to the first 10 harmonics. this specification depends mainly on the dither setting. thd is sometimes expressed in percentage. for converting the thd to a percentage, here is the formula: equation b-8: b.3.12 spurious-free dynamic range (sfdr) the ratio between the output power of the fundamental and the highest spur in the frequency spectrum. the spur frequency is not necessarily a harmonic of the fundamental even though it is usually the case. this figure represents the dynamic range of the adc when a full-scale signal is used at the input. this specification depends mainly on the dither setting. equation b-9: b.3.13 idle tones a delta-sigma converter is an integrating converter. it also has a finite quantization step (lsb) which can be detected by its quantizer. a dc input voltage that is below the quantization step should only provide an all zeros result, since the input is not large enough to be detected. as an integrating device, any delta-sigma will show, in this case, idle tones. this means that the output will have spurs in the frequency content that are depending on the ratio between quantization step voltage and the input voltage. these spurs are the result of the integrated subquantization step inputs that will eventually cross the quantization steps after a long enough integration. this will induce an ac frequency at the output of the adc and can be shown in the adc output spectrum. these idle tones are residues that are inherent to the quantization process and the fact that the converter is integrating at all times without being reset. they are residues of the finite resolution of the conversion process. they are very difficult to attenuate and they are heavily signal dependent. they can degrade both sfdr and thd of the converter, even for dc inputs. they can be localized in the baseband of the converter, and thus, difficult to filter from the actual input signal. for power metering applications, idle tones can be very disturbing because energy can be detected even at the 50 or 60 hz frequency, depending on the dc offset of the adcs, while no power is really present at the inputs. the only practical way to suppress or attenuate idle tones phenomenon is to apply dithering to the adc. the idle tones amplitudes are a function of the order of the modulator, the osr and the number of levels in the quantizer of the modulator. a higher order, a higher osr or a higher number of levels for the quantizer will attenuate the idle tones amplitude. snr db ?? 10 signalpower noisepower ---------------------------------- ?? ?? log = sinad db ?? 10 signalpower noise harmonicspower + ------------------------------------------------------------------- - ?? ?? log = sinad db ?? 10 10 snr 10 ----------- ?? ?? 10 thd ? 10 --------------- - ?? ?? + log = thd db ?? 10 harmonicspower fundamentalpower ---------------------------------------------------- - ?? ?? log = thd % ?? 100 10 thd db ?? 20 ------------------------ ? = sfdr db ?? 10 fundamentalpower highestspurpower ---------------------------------------------------- - ?? ?? log = downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 441 pic18f87j72 family b.3.14 dithering in order to suppress or attenuate the idle tones present in any delta-sigma adcs, dithering can be applied to the adc. dithering is the process of adding an error to the adc feedback loop in order to decorrelate the outputs and break the idle tones behavior. usually a random or pseudo-random generator adds an analog or digital error to the feedback loop of the delta-sigma adc in order to ensure that no tonal behavior can happen at its outputs. this error is filtered by the feed- back loop and typically has a zero average value so that the converter static transfer function is not dis- turbed by the dithering process. however, the dithering process slightly increases the noise floor (it adds noise to the part) while reducing its tonal behavior, and thus, improving sfdr and thd. the dithering process scrambles the idle tones into baseband white noise and ensures that dynamic specs (snr, sinad, thd, sfdr) are less signal dependent. the afe incorporates a proprietary dithering algorithm on both adcs in order to remove idle tones and improve thd, which is crucial for power metering applications. b.3.15 crosstalk the crosstalk is defined as the perturbation caused by one adc channel on the other adc channel. it is a measurement of the isolation between the two adcs present in the chip. this measurement is a two-step procedure: 1. measure one adc input with no perturbation on the other adc (adc inputs shorted). 2. measure the same adc input with a perturbation sine wave signal on the other adc at a certain predefined frequency. the crosstalk is then the ratio between the output power of the adc when the perturbation is present and when it is not divided by the power of the perturbation signal. a lower crosstalk value implies more independence and isolation between the two channels. the measurement of this signal is performed under the following conditions: gain = 1 prescale = 1 osr = 256 mclk = 4 mhz step 1 ch0+ = ch0- = sav ss ch1+ = ch1- = sav ss step 2 ch0+ = ch0- = sav ss ch1+ C ch1- = 1v p - p @ 50/60 hz (full-scale sine wave) the crosstalk is then calculated with the following formula: equation b-10: b.3.16 psrr this is the ratio between a change in the power supply voltage and the adc output codes. it measures the influence of the power supply voltage on the adc outputs. the psrr specification can be dc (the power supply is taking multiple dc values) or ac (the power supply is a sine wave at a certain frequency with a certain common-mode). in ac, the amplitude of the sine wave is representing the change in the power supply. it is defined as: equation b-11: where v out is the equivalent input voltage that the output code translates to with the adc transfer function. for the afe, sav dd ranges from 4.5v to 5.5v, and for ac psrr, a 50/60 hz sine wave is chosen, centered around 5v, with a maximum 500 mv amplitude. the psrr specification is measured with sav dd = sv dd . ctalk db ?? 10 ? ch0power ? ch1power -------------------------------- - ?? ?? log = psrr db ?? 20 ? v out ? sav dd ---------------------- ?? ?? log = downloaded from: http:///
pic18f87j72 family ds39979a-page 442 preliminary ? 2010 microchip technology inc. b.3.17 cmrr this is the ratio between a change in the common-mode input voltage and the adc output codes. it measures the influence of the common-mode input voltage on the adc outputs. the cmrr specification can be dc (the common-mode input voltage is taking multiple dc values) or ac (the common-mode input voltage is a sine wave at a certain frequency with a certain common-mode). in ac, the amplitude of the sine wave is representing the change in the power supply. it is defined as: equation b-12: when v cm = (chn+ + chn-)/2, the common-mode input voltage, and v out is the equivalent input voltage that is what the output code translates to with the adc transfer function. for the afe, vcm varies from -1v to +1v, and for the ac specification, a 50/60 hz sine wave is chosen centered around 0v with a 500 mv amplitude. b.3.18 adc reset mode adc reset mode (also called soft reset mode) can only be entered through setting the reset<1:0> bits high in the configuration register. this mode is defined as the condition where the converters are active but their output is forced to 0 . the registers are not affected in this reset mode and retain their values. the adcs can immediately output meaningful codes after leaving reset mode (and after the sinc filter settling time of 3/drclk). this mode is both entered and exited through the setting of the bits in the configuration register. each converter can be placed in soft reset mode independently. the configuration registers are not modified by the soft reset mode. a data ready pulse will not be generated by any adc while in reset mode. when an adc exits adc reset mode, any phase delay present before reset was entered will still be present. if one adc was not in reset, the adc leaving reset mode will automatically resynchronize the phase delay, relative to the other adc channel, per the phase delay register block and give dr pulses accordingly. if an adc is placed in reset mode while the other is converting, it is not shutting down the internal clock. when going back out of reset, it will be resynchronized automatically with the clock that did not stop during reset. if both adcs are in soft reset or shutdown modes, the clock is no longer distributed to the digital core for low-power operation. once any of the adc is back to normal operation, the clock is automatically distributed again. b.3.19 hard reset mode (areset = 0 ) this mode is only available during a por or when the areset pin is pulled low. the areset pin low state places the device in a hard reset mode. in this mode, all internal registers are reset to their default state. the dc biases for the analog blocks are still active (i.e., the afe is ready to convert). however, this pin clears all conversion data in the adcs. the comparator outputs of both adcs are forced to their reset state ( 0011 ). the sinc filters are all reset as well as their double output buffers. see serial timing for minimum pulse low time in section 29.0 electrical characteristics of the data sheet. during a hard reset, no communication with the part is possible. the digital interface is maintained in a reset state. b.3.20 adc shutdown mode adc shutdown mode is defined as a state where the converters and their biases are off, consuming only leakage current. after this is removed, start-up delay time (sinc filter settling time will occur before outputting meaningful codes). the start-up delay is needed to power up all dc biases in the channel that were in shutdown. this delay is the same than t por and any dr pulse coming within this delay should be discarded. each converter can be placed in shutdown mode independently. the config registers are not modified by the shutdown mode. this mode is only available through programming of the shutdown<1:0> bits in the config2 register. the output data is flushed to all zeros while in adc shutdown. no data ready pulses are generated by any adc while in adc shutdown mode. cmrr db ?? 20 ? v out ? v cm ----------------- ?? ?? log = downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 443 pic18f87j72 family when an adc exits adc shutdown mode, any phase delay present before shutdown was entered will still be present. if one adc was not in shutdown, the adc leaving shutdown mode will resynchronize automatically the phase delay relative to the other adc channel per the phase delay register block and give dr pulses accordingly. if an adc is placed in shutdown mode while the other is converting, it is not shutting down the internal clock. when going back out of shutdown, it will be resynchronized automatically with the clock that did not stop during reset. if both adcs are in adc reset or adc shutdown modes, the clock is no more distributed to the digital core for low-power operation. once any of the adc is back to normal operation, the clock is automatically distributed again. b.3.21 full shutdown mode the lowest power consumption can be achieved when shutdown<1:0> = 11 , vrefext = clkext = 1 . this mode is called full shutdown mode and no ana- log circuitry is enabled. in this mode, the por sv dd monitoring circuit is also disabled. when the clock is idle (clkia = 0 or 1 continuously), no clock is propa- gated throughout the chip. both adcs are in shutdown, the internal voltage reference is disabled and the internal oscillator is disabled. the only circuit that remains active is the spi interface, but this circuit does not induce any static power consumption. if sck is idle, the only current consumption comes from the leakage currents induced by the transistors and is less than 1 a on each power supply. this mode can be used to power down the chip completely and avoid power consumption when there is no data to convert at the analog inputs. any sck or mclk edge coming, while on this mode, will induce dynamic power consumption. once any of the shutdown, clkext and vrefext bits returns to 0 , the por sv dd monitoring block is back to operation and sv dd monitoring can take place. b.4 device overview b.4.1 analog inputs (chn+/-) the analog inputs of the dual-channel afe can be con- nected directly to current and voltage transducers (such as shunts, current transformers or rogowski coils). each input pin is protected by specialized esd structures that are certified to pass 7 kv hbm and 400v mm contact charge. these structures allow bipolar 6v continuous voltage, with respect to sav ss , to be present at their inputs without the risk of permanent damage. both channels have fully differential voltage inputs for better noise performance. the absolute voltage at each pin relative to sav ss should be maintained in the 1v range during operation in order to ensure the specified adc accuracy. the common-mode signals should be adapted to respect both the previous conditions and the differential input voltage range. for best performance, the common-mode signals should be maintained to sav ss . b.4.2 programmable gain amplifiers (pga) the two programmable gain amplifiers (pgas) reside at the front end of each delta-sigma adc. they have two functions: translate the common-mode of the input from sav ss to an internal level between sav ss and sav dd , and amplify the input differential signal. the translation of the common-mode does not change the differential signal, but re-centers the common-mode so that the input signal can be properly amplified. the pga block can be used to amplify very low signals, but the differential input range of the delta-sigma modulator must not be exceeded. the pga is controlled by the pga_chn<2:0> bits in the gain register. table b-4 represents the gain settings for the pga: table b-4: pga configuration setting pga gain (pga_chn<2:0>) gain v in range (v) (v/v) (db) 000 10 0 . 5 001 26 0 . 2 5 010 4 12 0.125 011 8 18 0.0625 100 16 24 0.03125 101 32 30 0.015625 downloaded from: http:///
pic18f87j72 family ds39979a-page 444 preliminary ? 2010 microchip technology inc. b.4.3 delta-sigma modulator b.4.3.1 architecture both of the adcs in the afe are identical and they include a second-order modulator with a multi-bit dac architecture (see figure b-2). the quantizer is a flash adc composed of 4 comparators with equally spaced thresholds and a thermometer output coding. the proprietary 5-level architecture ensures minimum quantization noise at the outputs of the modulators without disturbing linearity or inducing additional distortion. the sampling frequency is dmclk (typically 1 mhz with mclk = 4 mhz) so the modulator outputs are refreshed at a dmclk rate. both modulators also include a dithering algorithm that can be enabled through the dither<1:0> bits in the configuration register. this dithering process improves thd and sfdr (for high osr settings) while increasing slightly the noise floor of the adcs. for power metering applications and applications that are distortion-sensitive, it is recommended to keep dither enabled for both adcs. in the case of power metering applications, thd and sfdr are critical specifications to optimize snr (noise floor). this is not really problematic due to the large averaging factor at the output of the adcs; therefore, even for low osr settings, the dithering algorithm will show a positive impact on the performance of the application. figure b-2 represents a simplified block diagram of the delta-sigma adc present on the afe. figure b-2: simplified delta-sigma adc block diagram b.4.3.2 modulator input range and saturation point for a specified voltage reference value of 2.4v, the mod- ulators specified differential input range is 500 mv. the input range is proportional to v ref and scales according to the v ref voltage. this range ensures the stability of the modulator over amplitude and frequency. outside of this range, the modulator is still functional, however, its stability is no longer ensured, and therefore, it is not rec- ommended to exceed this limit. the saturation point for the modulator is v ref /3 since the transfer function of the adc includes a gain of 3 by default (independent from the pga setting). see section b.4.5 adc output coding . b.4.3.3 boost mode the delta-sigma modulators also include an independent boost mode for each channel. if the corresponding boost<1:0> bit is enabled, the power consumption of the modulator is multiplied by 2 and its bandwidth is increased to be able to sustain amclk clock frequencies, up to 8.192 mhz, while keeping the adc accuracy. when disabled, the power consumption is back to normal and the amclk clock frequencies can only reach up to 5 mhz without affecting adc accuracy. b.4.4 sinc 3 filter both of the adcs include a decimation filter that is a third-order sinc (or notch) filter. this filter processes the multi-bit bitstream into 16 or 24-bit words (depending on the width configuration bit). the settling time of the filter is 3 dmclk periods. it is recommended to dis- card unsettled data to avoid data corruption, which can be done easily by setting the dr_lty bit high in the status/com register. the resolution achievable at the output of the sinc filter (the output of the adc) is dependant on the osr and is summarized with the following table: for 24-bit output mode (width = 1 ), the output of the sinc filter is padded with least significant zeros for any resolution less than 24 bits. for 16-bit output modes, the output of the sinc filter is rounded to the closest 16-bit number in order to conserve only 16-bit words and to minimize truncation error. second order integrator loop filter quantizer dac differential voltage input output bitstream 5-level flash adc delta-sigma modulator table b-5: adc resolution vs. osr osr<1:0> osr adc resolution (bits) no missing codes 00 32 17 01 64 20 10 128 23 11 256 24 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 445 pic18f87j72 family the gain of the transfer function of this filter is 1 at each multiple of dmclk (typically 1 mhz), so a proper anti-aliasing filter must be placed at the inputs to attenuate the frequency content around dmclk and keep the desired accuracy over the baseband of the converter. this anti-aliasing filter can be a simple first-order rc network with a sufficiently low time constant to generate high rejection at dmclk frequency. equation b-13: sinc filter transfer function h(z) the normal-mode rejection ratio (nmrr) or gain of the transfer function is given by the following equation: equation b-14: magnitude of frequency response h(f) figure b-3 shows the sinc filter frequency response: figure b-3: sinc filter response with mclk = 4 mhz, osr = 64, prescale = 1 b.4.5 adc output coding the second-order modulator, sinc 3 filter, pga, v ref and analog input structure all work together to produce the device transfer function for the analog to digital conversion (see equation b-15). the channel data is either a 16-bit or 24-bit word, presented in 23-bit or 15-bit plus sign, twos complement format and is msb (left) justified. the adc data is two or three bytes wide depending on the width bit of the associated channel. the 16-bit mode includes a round to the closest 16-bit word (instead of truncation) in order to improve the accuracy of the adc data. in case of positive saturation (chn+ C chn- > v ref /3), the output is locked to 7fffff for 24-bit mode (7fff for 16-bit mode). in case of negative saturation (chn+ C chn- ? v ref /3), the output code is locked to 800000 for 24-bit mode (8000 for 16-bit mode). equation b-15 is only true for dc inputs. for ac inputs, this transfer function needs to be multiplied by the transfer function of the sinc 3 filter (see equation b-13 and equation b-14). equation b-15: hz ?? 1z osr ? ? osr 1 z 1 ? ? ?? -------------------------------- - ?? ?? ?? 3 = z 2 ? fj dmclk --------------------- - ?? ?? exp = where nmrr f ?? c ? f dmclk --------------------- - ? ?? ?? sin c ? f drclk -------------------- ? ?? ?? sin ---------------------------------------------- 3 = nmrr f ?? c ? f f s --- - ? ?? ?? sin c ? f f d ---- - ? ?? ?? sin ----------------------------- 3 = cx ?? sin x ?? sin x -------------- - = or, where -120 -100 -80 -60 -40 -20 0 20 1 10 100 1000 10000 100000 1000000 input frequency (hz) magnitude (db) data_chn ch n+ ch n- ? ?? v ref+ v ref- ? ------------------------------------- - ?? ?? 8,388,608 g 3 ? ? ? = data_chn ch n+ ch n- ? ?? v ref+ v ref- ? ------------------------------------- - ?? ?? 32 768 ,g3 ? ? ? = (for 24-bit mode or width = 1) (for 16-bit mode or width = 0) downloaded from: http:///
pic18f87j72 family ds39979a-page 446 preliminary ? 2010 microchip technology inc. b.4.5.1 adc resolution as a function of osr the adc resolution is a function of the osr ( section b.4.4 sinc3 filter ). the resolution is the same for both channels. no matter what the resolution is, the adc output data is always presented in 24-bit words, with added zeros at the end, if the osr is not large enough to produce 24-bit resolution (left justification). table b-6: osr = 256 output code examples adc output code (msb first) hexadecimal decimal 011 1 1111 1111 1111 1111 1111 0x7fffff + 8,388,607 0111 1111 1111 1111 1111 1110 0x7ffffe + 8,388,606 0000 0000 0000 0000 0000 0000 0x000000 0 1111 1111 1111 1111 1111 1111 0xffffff -1 1000 0000 0000 0000 0000 0001 0x800001 - 8,388,607 1000 0000 0000 0000 0000 0000 0x800000 - 8,388,608 table b-7: osr = 128 output code examples adc output code (msb first) hexadecimal decimal 23-bit resolution 0111 1111 1111 1111 1111 111 0 0x7ffffe + 4,194,303 0111 1111 1111 1110 1111 110 0 0x7ffffc + 4,194,302 0000 0000 0000 0000 0000 000 0 0x000000 0 1111 1111 1111 1111 1111 111 0 0xfffffe -1 1000 0000 0000 0000 0000 001 0 0x800002 - 4,194,303 1000 0000 0000 0000 0000 000 0 0x800000 - 4,194,304 table b-8: osr = 64 output code examples adc output code (msb first) hexadecimal decimal 20-bit resolution 0111 1111 1111 1111 1111 0 0 0 0 0x7ffff0 + 524, 287 0111 1111 1111 1111 1110 0 0 0 0 0x7fffe0 + 524, 286 0000 0000 0000 0000 0000 0 0 0 0 0x000000 0 1111 1111 1111 1111 1111 0 0 0 0 0xfffff0 -1 1000 0000 0000 0000 0001 0 0 0 0 0x800010 - 524,287 1000 0000 0000 0000 0000 0 0 0 0 0x800000 - 524, 288 table b-9: osr = 32 output code examples adc output code (msb first) hexadecimal decimal 17-bit resolution 0111 1111 1111 1111 1 0 0 0 0 0 0 0 0x7fff80 + 65, 535 0111 1111 1111 1111 0 0 0 0 0 0 0 0 0x7fff00 + 65, 534 0000 0000 0000 0000 0 0 0 0 0 0 0 0 0x000000 0 1111 1111 1111 1111 1 0 0 0 0 0 0 0 0xffff80 -1 1000 0000 0000 0000 1 0 0 0 0 0 0 0 0x800080 - 65,535 1000 0000 0000 0000 0 0 0 0 0 0 0 0 0x800000 - 65, 536 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 447 pic18f87j72 family b.4.6 voltage reference b.4.6.1 internal voltage reference the afe contains an internal voltage reference source specially designed to minimize drift over temperature. in order to enable the internal voltage reference, the vrefext bit in the configuration register must be set to 0 (default mode). this internal v ref supplies refer- ence voltage to both channels. the typical value of this voltage reference is 2.37v 2%. the internal reference has a very low typical temperature coefficient of 12 ppm/c, allowing the output codes to have minimal variation with respect to temperature since they are proportional to (1/v ref ). the noise of the internal voltage reference is low enough not to significantly degrade the snr of the adc if compared to a precision external low-noise voltage reference. the output pin for the internal voltage reference is refin+/out. when the internal voltage reference is enabled, the refin- pin should always be connected to sav ss . for optimal adc accuracy, appropriate bypass capacitors should be placed between refin+/out and sav ss . decoupling at the sampling frequency, around 1 mhz is important, for any noise around this frequency will be aliased back into the conversion data. 0.1 f ceramic and 10 f tantalum capacitors are recommended. these bypass capacitors are not mandatory for correct adc operation, but removing these capacitors may degrade accuracy of the adc. the bypass capacitors also help for applications where the voltage reference output is connected to other circuits. in this case, additional buffering may be needed as the output drive capability of this output is low. b.4.6.2 differential external voltage inputs when the vrefext bit is high, the two reference pins (refin+/out, refin-) become a differential voltage reference input. the voltage at the refin+/out is noted v ref + and the voltage at the refin- pin is noted v ref -. the differential voltage input value is given by the following equation: v ref = v ref + C v ref - the specified v ref range is from 2.2v to 2.6v. the refin- pin voltage (v ref -) should be limited to 0.3v. typically, for single-ended reference applications, the refin- pin should be directly connected to sav ss . b.4.7 power-on reset the afe contains its own internal por circuit that monitors analog supply voltage av dd during operation. the typical threshold for a power-up event detection is 4.2v, 5%. the por circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mv. proper decoupling capacitors (0.1 f ceramic and 10 f tantalum) should be mounted as close as possible to the av dd pin, providing additional transient immunity. figure b-4 illustrates the different conditions at power-up and a power-down event in the typical conditions. all internal dc biases are not settled until at least 50 s after system por. any dr pulses during this time after system reset should be ignored. after por, dr pulses are present at the pin with all the default conditions in the configuration registers. the analog and digital power supplies are indepen- dent. since av dd is the only power supply that is mon- itored, it is highly recommended to power up dv dd first as a power-up sequence. if av dd is powered up first, it is highly recommended to keep the reset pin low during the whole power-up sequence. figure b-4: power-on reset operation av dd 5v 4.2v 4v 0v device mode reset proper operation reset time 50 s t por downloaded from: http:///
pic18f87j72 family ds39979a-page 448 preliminary ? 2010 microchip technology inc. b.4.8 areset effect on delta-sigma modulator/sinc filter when the areset pin is low, both adcs will be in reset and output code, 0x0000h. the reset pin per- forms a hard reset (dc biases still on, part ready to convert) and clears all charges contained in the sigma-delta modulators. the comparator output is 0011 for each adc. the sinc filters are all reset, as well as their double output buffers. this pin is independent of the serial interface. it brings the config registers to the default state. when reset is low, any write with the spi interface will be disabled and will have no effect. the output pins (sdoa, dr ) are high impedance and no clock is propagated through the chip. b.4.9 phase delay block the afe incorporates a phase delay generator which ensures that the two adcs are converting the inputs with a fixed delay between them. the two adcs are synchronously sampling, but the averaging of modulator outputs is delayed so that the sinc filter outputs (thus, the adc outputs) show a fixed phase delay, as determined by the phase register setting. the phase register (phase<7:0>) is a 7-bit + sign, msb first, twos complement register, that indicates how much phase delay there is to be between channel 0 and channel 1. the reference channel for the delay is channel 1 (typically the voltage channel for power metering applications). when phase<7:0> bits are positive, channel 0 is lagging versus channel 1. when phase<7:0> are negative, channel 0 is leading versus channel 1. the amount of delay between two adc conversions is given by the following formula: equation b-16: the timing resolution of the phase delay is 1/dmclk or 1 s in the default configuration with mclk = 4 mhz. the data ready signals are affected by the phase delay settings. typically, the time difference between the data ready pulses of channel 0 and channel 1 is equal to the phase delay setting. b.4.9.1 phase delay limits the phase delay can only go from -osr/2 to +osr/2 C 1. this sets the fine phase resolution. the phase register is coded with 2s complement. if larger delays between the two channels are needed, they can be implemented by the microcontroller. a fifo can save incoming data from the leading channel for a number n of drclk clocks. in this case, drclk would represent the coarse timing resolution, and dmclk the fine timing resolution. the total delay will then be equal to: delay = n/drclk + phase/dmclk the phase delay register can be programmed once with the osr = 256 setting, and will adjust to the osr automatically afterwards, without the need to change the value of the phase register. osr = 256 : the delay can go from -128 to +127. phase<7> is the sign bit. phase<6> is the msb and phase<0> is the lsb. osr = 128: the delay can go from -64 to +63. phase<6> is the sign bit. phase<5> is the msb and phase<0> is the lsb. osr = 64 : the delay can go from -32 to +31. phase<5> is the sign bit. phase<4> is the msb and phase<0> is the lsb. osr = 32: the delay can go from -16 to +15. phase<4> is the sign bit. phase<3> is the msb and phase<0> is the lsb. note: a detailed explanation of the data ready pin (dr ) with phase delay is present in section b.5.9.1 data ready latches and data ready modes (drmode<1:0>) . delay phase register code dmclk ------------------------------------------------- - = table b-10: phase values with mclk = 4 mhz, osr = 256 phase register value delay (ch0 relative to ch1) binary hex 01111111 0x7f +127 s 01111110 0x7e +126 s 00000001 0x01 +1 s 00000000 0x00 0 s 11111111 0xff -1 s 10000001 0x81 -127 s 10000000 0x80 -128 s downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 449 pic18f87j72 family b.4.10 internal afe clock the afe uses an external clock signal to operate its internal digital logic. an internal clock generation chain (figure b-5) is used to produce a range of drclk sampling frequencies. for keeping specified adc accuracy, amclk should be kept between 1 and 5 mhz with boost off, or 1 and 8.192 mhz with boost on. larger mclk frequencies can be used provided the prescaler clock settings allow the amclk to respect these ranges. figure b-5: afe internal clock detail b.5 serial interface description b.5.1 overview the afe is accessed for control and data output exclu- sively through its dedicated serial peripheral interface (spi). the interface is compatible with spi modes 0,0 and 1,1. data is clocked out of the afe on the falling edge of sck, and data is clocked in on the rising edge of sck. in these modes, sck can idle either high or low. each spi communication starts with a cs falling edge and stops with the cs rising edge. each spi communication is independent. when cs is high, sdo is in high-impedance, transitions on sck and sdi have no effect. additional controls pins (areset and dr ) are also provided on separate pins for advanced communication. the afes spi interface has a simple command structure. the first byte transmitted is always the control byte and is followed by data bytes that are 8-bit wide. both adcs are continuously converting data by default and can be reset or shut down through a config2 register setting. since each adc data is either 16 or 24 bits (depending on the width bits), the internal registers can be grouped together with various configurations (through the read bits) in order to allow easy data retrieval within only one communication. for device reads, the internal address counter can be automatically incremented in order to loop through groups of data within the register map. sdoa will then output the data located at the address (a<4:0>) defined in the con- trol byte and then address + 1 depending on the read<1:0> bits, which select the groups of registers. these groups are defined in section b.6.1 adc channel data output registers (register map). the data ready pin (dr ) can be used as an interrupt for a microcontroller and outputs pulses when new adc channel data is available. the areset pin acts like a hard reset and can reset the afe to its default power-up configuration, independent of the microcontroller. b.5.2 control byte the control byte of the afe contains two device address bits (a<6:5>), 5 register address bits (a<4:0>) and a read/write bit (r/w ). the first byte transmitted to the afe is always the control byte. the afe interface is device-addressable (through a<6:5>) so that multiple devices can be present on the same spi bus with no data bus contention. this functionality enables three-phase power metering systems containing an afe and two other external afe-type chips, controlled by a single spi bus (single cs , sck, sdi and sdo pins). the default device address bits are 00 . figure b-6: control byte a read on undefined addresses will give an all zeros output on the first and all subsequent transmitted bytes. a write on an undefined address will have no effect and will not increment the address counter either. the register map is defined in section b.6.1 adc channel data output registers . prescale<1:0> 1/ mclk amclk 1/4 dmclk 1/osr drclk osr<1:0> clock divider clock divider clock divider clkia prescale f s adc sampling rate f d adc output data rate digital buffer a6 a5 a4 a3 a2 a1 a0 r/w read write bit register device address bits address bits downloaded from: http:///
pic18f87j72 family ds39979a-page 450 preliminary ? 2010 microchip technology inc. b.5.3 reading from the device the first data byte read is the one defined by the address given in the control byte. after this first byte is transmitted, if the cs pin is maintained low, the com- munication continues and the address of the next transmitted byte is determined by the status of the read bits in the status/com register. multiple looping configurations can be defined through the read<1:0> bits for the address increment (see section b.5.6 spi mode 0,0 - clock idle low, read/write examples ). b.5.4 writing to the device the first data byte written is the one defined by the address given in the control byte. the write communication automatically increments the address for subsequent bytes. the address of the next transmitted byte within the same communication (csa stays low) is the next address defined on the register map. at the end of the register map, the address loops to the beginning of the register map. writing a non-writable register has no effect. the sdoa pin stays in a high-impedance state during a write communication. b.5.5 spi mode 1,1 C clock idle high, read/write examples in this spi mode, the clock idles high. for the afe, this means that there will be a falling edge before there is a rising edge. figure b-7: device read (spi mode 1,1 C clock idles high) figure b-8: device write (spi mode 1,1 C clock idles high) note: changing from an spi mode 1,1 to an spi mode 0,0 is possible, but needs a reset pulse in-between to ensure correct communication. scksdi sdo cs a6 a5 a4 a3 a2 a1 a0 d6 d5 d4 d3 d2 d1 d0 (address) data (address + 1) data d6 d5 d4 d3 d2 d1 data transitions on the falling edge afe latches bits on the rising edge d0 hi-z hi-z d7 d7 r/w hi-z scksdi sdo cs r/w a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 (address) data (address + 1) data d6 d5 d4 d3 d2 d1 d0 data transitions on the falling edge afe latches bits on the rising edge d0 hi-z hi-z d7 hi-z downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 451 pic18f87j72 family b.5.6 spi mode 0,0 - clock idle low, read/write examples in this spi mode, the clock idles low. for the afe, this means that there will be a rising edge before there is a falling edge. figure b-9: device read (spi mode 0,0 C clock idles low) figure b-10: device write (spi mode 0,0 C clock idles low) scksdi sdo cs r/w a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 (address) data (address + 1) data d7 d6 d5 d4 d3 d2 d1 data transitions on the falling edge afe latches bits on the rising edge d0 d7 of (address + 2) data hi-z hi-z hi-z scksdi sdo cs r/w a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d7 (address) data (address + 1) data d6 d5 d4 d3 d2 d1 d7 of (address + 2) data d0 data transitions on the falling edge afe latches bits on the rising edge d0 hi-z hi-z hi-z downloaded from: http:///
pic18f87j72 family ds39979a-page 452 preliminary ? 2010 microchip technology inc. b.5.7 continuous communication, looping on address sets if the user wishes to read back either of the adc channels continuously, or both channels continuously, the internal address counter can be set to loop on spe- cific register sets. in this case, there is only one control byte on sdi to start the communication. the part stays within the same loop until cs returns high. this internal address counter allows the following functionality: read one adc channel data continuously read both adc channel data continuously (both adc data can be independent or linked with drmode settings) read continuously the entire register map read continuously each separate register read continuously all configuration registers write all configuration registers in one communication (see figure b-11) the status/com register contains the loop settings for the internal address counter (read<1:0>). the internal address counter can either stay constant (read<1:0> = 00 ) and read continuously the same byte, or it can auto-increment and loop through the register groups defined below (read<1:0> = 01 ), register types (read<1:0> = 10 ) or the entire register map (read<1:0> = 11 ). each channel is configured independently as either a 16-bit or 24-bit data word depending on the setting of the corresponding width bit in the config1 register. for continuous reading, in the case of width = 0 (16-bit), the lower byte of the adc data is not accessed and the part jumps automatically to the following address (the user does not have to clock out the lower byte since it becomes undefined for width = 0 ). the following figure represents a typical, continuous read communication with the default settings (drmode<1:0> = 00 , read<1:0> = 10 ) for both width settings. this configuration is typically used for power metering applications. figure b-11: typical cont inuous read communication ch0 adc addr/r cs sck sdi ch0 adc upper byte sdo ch0 adc middle byte ch0 adc lower byte dr ch1 adc upper byte ch1 adc middle byte ch1 adc lower byte ch0 adc upper byte ch0 adc middle byte ch0 adc lower byte ch1 adc upper byte ch1 adc middle byte ch1 adc lower byte these btes are not present when width=0 (16-bit mode) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 453 pic18f87j72 family b.5.7.1 continuous write both adcs are powered up with their default configurations and begin to output dr pulses immediately (reset<1:0> and shutdown<1:0> bits are all 0 by default). the default output codes for both adcs are all zeros. the default modulator output for both adcs is 0011 (corresponding to a theoretical zero voltage at the inputs). the default phase is zero between the two channels. it is recommended to enter into adc reset mode for both adcs just after power-up because the desired register configuration may not be the default one, and in this case, the adc would output undesired data. within the adc reset mode (reset<1:0> = 11 ), the user can configure the whole part with a single commu- nication. the write commands increment the address automatically so that the user can start writing the phase register, and finish with the config2 register, in only one communication (see figure b-11). the reset<1:0> bits are in the config2 register to allow exiting of the soft reset mode, and have the whole part configured and ready to run in only one command. the following register sets are defined as groups: the following register sets are defined as types: b.5.8 situations that reset adc data immediately after the following actions, the adcs are temporarily reset in order to provide proper operation: 1. change in the phase register. 2. change in the osr setting. 3. change in the prescale setting. 4. overwrite of the same phase register value. 5. change in the clkext bit in the config2 register, modifying the internal oscillator state. after these temporary resets, the adcs go back to the normal operation with no need for an additional command. these are also the settings where the dr position is affected. the phase register can be used to serially soft reset the adcs without using the reset bits in the configuration register if the same value is written in the phase register. figure b-12: recommended config uration sequence at power up table b-11: register groups group addresses adc data ch0 0x00-0x02 adc data ch1 0x03-0x05 phase, gain 0x07-0x08 config, status 0x09-0x0b table b-12: register types type addresses adc data (both channels) 0x00-x05 configuration 0x07-0x0b 00011000 cs sck sdi av dd 11xxxxx1 config2 addr/w config2 optional reset of both adcs one command for writing complete configuration phase addr/w gain status/com config1 config2 phase 00001110 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx downloaded from: http:///
pic18f87j72 family ds39979a-page 454 preliminary ? 2010 microchip technology inc. b.5.9 data ready pin (dr ) to signify when channel data is ready for transmission, the data ready signal is available on the data ready pin (dr ) through an active-low pulse at the end of a channel conversion. the data ready pin outputs an active-low pulse with a period that is equal to the drclk clock period and with a width equal to one dmclk period. when not active-low, this pin can either be in high impedance (when dr_hizn = 0 ) or in a defined logic high state (when dr_hizn = 1 ). this is controlled through the configuration registers. this allows multiple devices to share the same data ready pin (with a pull-up resistor connected between dr and dv dd ) in 3-phase energy meter designs to reduce microcontroller pin count. a single device on the bus does not require a pull-up resistor. after a data ready pulse has occurred, the adc output data can be read through spi communication. two sets of latches at the output of the adc prevent the communication from outputting corrupted data (see section b.5.9.1 data ready latches and data ready modes (drmode<1:0>) ). the cs pin has no effect on the dr pin, which means even if cs is high, data ready pulses will be provided (except when the configuration prevents from outputting data ready pulses). the dr pin can be used as an interrupt when connected to an external micro- controller. when the areset pin is low, the dr pin is not active. b.5.9.1 data ready latches and data ready modes (drmode<1:0>) to ensure that both channel adc data are present at the same time for spi read, regardless of phase delay settings for either or both channels, there are two sets of latches in series with both the data ready and the read start triggers. the first set of latches holds each output when data is ready and latches both outputs together when drmode<1:0> = 00 . when this mode is on, both adcs work together and produce one set of available data after each data ready pulse (that corresponds to the lagging adc data ready). the second set of latches ensures that when reading starts on an adc output, the corresponding data is latched so that no data corruption can occur. if an adc read has started, in order to read the following adc output, the current reading needs to be completed (all bits must be read from the adc output data registers). b.5.9.2 data ready pin (dr ) control using drmode bits there are four modes that control the data ready pulses and these modes are set with the drmode<1:0> bits in the status/com register. for power metering applications, drmode<1:0> = 00 is recommended (default mode). the position of dr pulses vary with respect to this mode, to the osr and to the phase settings: drmode<1:0> = 11 : both data ready pulses from adc channel 0 and adc channel 1 are output on the dr pin. drmode<1:0> = 10 : data ready pulses from adc channel 1 are output on the dr pin. dr pulses from adc channel 0 are not present on the pin. drmode<1:0> = 01 : data ready pulses from adc channel 0 are output on the dr pin. dr pulses from adc channel 1 are not present on the pin. drmode<1:0> = 00 : (recommended and default mode). data ready pulses from the lagging adc, between the two, are output on the dr pin. the lagging adc depends on the phase register and on the osr. in this mode, the two adcs are linked together so their data is latched together when the lagging adc output is ready. b.5.9.3 dr pulses with shutdown or reset conditions there will be no dr pulses if drmode<1:0> = 00 when either one or both of the adcs are in reset or shutdown. in mode 00, a dr pulse only happens when both adcs are ready. any dr pulse will correspond to one data on both adcs. the two adcs are linked together and act as if there was only one channel with the combined data of both adcs. this mode is very practical when both adc channel data retrieval and processing need to be synchronized, as in power metering applications. figure b-13 represents the behavior of the data ready pin with the different drmode and dr_lty configurations, while shutdown or resets are applied. note: if drmode<1:0> = 11 , the user will still be able to retrieve the dr pulse for the adc not in shutdown or reset (i.e., only one adc channel needs to be awake). downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 455 pic18f87j72 family figure b-13: data ready behavior d0 d1 d2 d0 d1 d2 d3 d4 d5 d3 d4 d5 d0 d1 d2 d3 d4 d5 d6 d7 d8 d1 d3 d5 d6 d7 d8 d10 d12 d0 d2 d4 d9 d11 d13 d14 d6 d6 d12 d9 d13 d16 d17 d18 d19 d21 d24 d15 d20 d22 d25 d26 d7 d8 d9 d10 d11 d10 d11 d12 d10 d7 d8 d9 d23 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 d12 d13 d14 d15 d16 d0 d1 d2 d4 d5 d3 d7 d8 d9 d10 d11 d12 d13 d6 d15 d16 d14 d0 d1 d2 d6 d10 d11 d12 d13 d11 d13 d14 d15 d16 d12 d13 d14 d14 d28 d29 d31 d33 d27 d30 d32 d34 d15 d16 d17 d8 d7 d9 d4 d5 d3 reset<1> or shutdown<1> reset<0> or shutdown<0> reset d0 d1 d2 d3 d4 d5 d0 d1 d2 d3 d4 d5 d6 d7 d8 d1 d3 d5 d6 d7 d8 d11 d13 d0 d2 d4 d10 d12 d14 d15 d6 d9 d13 d17 d18 d21 d24 d16 d19 d22 d25 d26 d10 d11 d12 d10 d8 d9 d23 d11 d12 d13 d14 d28 d29 d31 d33 d27 d30 d32 d34 d14 d15 d16 d0 d1 d2 d3 d4 d5 d12 d11 d13 d15 d16 d17 d8 d9 d10 d7 phase < 0 phase = 0 phase > 0 d6 d7 drclk period drclk period internal reset synchronisation (1 dmclk period) 3*drclk period 3*drclk period d14 d9 d20 drmode = 00 ; dr drmode = 01 ; dr drmode = 10 ; dr drmode = 11 ; dr drmode = 00 ; dr drmode = 01 ; dr drmode = 10 ; dr drmode = 11 ; dr drmode = 00 ; dr drmode = 01 ; dr drmode= 10 ; dr drmode = 11 ; dr drmode = 00 : select the lagging data ready drmode = 01 : select the data ready on channel 0 drmode = 10 : select the data ready on channel 1 drmode = 11 : select both data ready data ready pulse that appears only when dr_lty = 0 drclk period 1 dmclk period downloaded from: http:///
pic18f87j72 family ds39979a-page 456 preliminary ? 2010 microchip technology inc. b.6 internal registers the addresses associated with the internal registers are listed below. a detailed description of the registers follows. all registers are 8 bits long and can be addressed separately. read modes define the groups and types of registers for continuous read communication or looping on address sets. . table b-14: register map grouping for continuous read modes table b-13: register map address name bits r/w description 0x00 data_ch0 24 r channel 0 adc data<23:0>, msb first 0x03 data_ch1 24 r channel 1 adc data<23:0>, msb first 0x06 reserved 8 reserved; ignore reads, do not write 0x07 phase 8 r/w phase delay configuration register 0x08 gain 8 r/w gain configuration register 0x09 status/com 8 r/w status/communication register 0x0a config1 8 r/w configuration register 1 0x0b config2 8 r/w configuration register 2 function address read<1:0> 01 10 11 data_ch0 0x00 group type loop entire register map 0x01 0x02 data_ch1 0x03 group 0x04 0x05 phase 0x07 group type gain 0x08 status/com 0x09 group config1 0x0a config2 0x0b downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 457 pic18f87j72 family b.6.1 adc channel data output registers the adc channel data output registers always con- tain the most recent a/d conversion data for each channel. these registers are read-only. they can be accessed independently as three 8-bit registers or linked together (with read<1:0> bits). these registers are latched when an adc read com- munication occurs. when a data ready event occurs during a read communication, the most current adc data is also latched to avoid data corruption issues. the three bytes of each channel are updated synchro- nously at a drclk rate. the three bytes can be accessed separately if needed but are refreshed synchronously. register b-1: data_chn: channel output registers (ch0, addresses 0x00-0x02; ch1; 0x03-0x05) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data_chn <23> data_chn <22> data_chn <21> data_chn <20> data_chn <19> data_chn <18> data_chn <17> data_chn <16> bit 23 bit 16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data_chn <15> data_chn <14> data_chn <13> data_chn <12> data_chn <11> data_chn <10> data_chn <9> data_chn <8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data_chn <7> data_chn <6> data_chn <5> data_chn <4> data_chn <3> data_chn <2> data_chn <1> data_chn <0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
pic18f87j72 family ds39979a-page 458 preliminary ? 2010 microchip technology inc. b.6.2 phase register the phase register (phase<7:0>) is a 7 bits + sign, msb first, twos complement register that indicates how much phase delay there should be between channel 0 and channel 1. the reference channel for the delay is channel 1 (typically, the voltage channel when used in energy metering applications) i.e., when phase register code is positive, channel 0 is lagging channel 1. when phase register code is negative, channel 0 is leading versus channel 1. the delay is give by the following formula: equation b-17: b.6.2.1 phase resolution from osr the timing resolution of the phase delay is 1/dmclk or 1 s in the default configuration (mclk = 4 mhz). the phase register coding depends on the osr setting, as shown in table b-15. delay phase register code dmclk ------------------------------------------------- - = table b-15: phase encoding resolution by oversampling ratio oversampling ratio encoding osr <1:0> value # significant digits sign bit range 00 32 7 <6:0> <7> -128 to +127 01 64 6 <5:0> <6> -64 to +63 10 128 5 <4:0> <5> -32 to +31 11 256 4 <3:0> <4> -16 to +15 register b-2: phase: phase register (address 0x07) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phase<7> phase<6> phase<5> phase<4> phase<3> phase<2> phase<1> phase<0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 phase<7-0>: ch0 relative to ch1 phase delay bits delay = phase register twos complement code/dmclk (default phase = 0 ) downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 459 pic18f87j72 family b.6.3 gain configuration register this registers contains the settings for the pga gains for each channel, as well as the boost options for each channel. register b-3: gain: gain configuration register (address 0x08) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pga_ch1 <2> pga_ch1 <1> pga_ch1 <0> boost<1> boost<0> pga_ch0 <2> pga_ch0 <1> pga_ch0 <0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-5 pga_ch1<2:0>: pga setting for channel 1 bits 111 = reserved (gain = 1) 110 = reserved (gain = 1) 101 = gain is 32 100 = gain is 16 011 = gain is 8 010 = gain is 4 001 = gain is 2 000 = gain is 1 bit 4-3 boost<1:0>: current scaling for high-speed operation bits 11 = both channels have current x 2 10 = channel 1 has current x 2 01 = channel 0 has current x 2 00 = neither channel has current x 2 bit 2-0 pga_ch0<2:0>: pga setting for channel 0 bits 111 = reserved (gain = 1) 110 = reserved (gain = 1) 101 = gain is 32 100 = gain is 16 011 = gain is 8 010 = gain is 4 001 = gain is 2 000 = gain is 1 downloaded from: http:///
pic18f87j72 family ds39979a-page 460 preliminary ? 2010 microchip technology inc. b.6.4 status and communication register this register contains all settings related to the communication, including data ready settings and status, and read mode settings. b.6.4.1 data ready (dr ) latency control C dr_lty this bit determines if the first data ready pulses correspond to settled data, or unsettled data, from each sinc 3 filter. unsettled data will provide dr pulses every drclk period. if this bit is set, unsettled data will wait for 3 drclk periods before giving dr pulses and will then give dr pulses every drclk period. b.6.4.2 data ready (dr ) pin high-z C dr_hizn this bit defines the non-active state of the data ready pin (logic 1 or high-impedance). using this bit, the user can connect multiple chips with the same dr pin with a pull-up resistor (dr_hizn = 0 ) or a single chip with no external component (dr_hizn = 1 ). b.6.4.3 data ready mode C drmode<1:0> if one of the channels is in reset or shutdown, only one of the data ready pulses is present and the situation is similar to drmode = 01 or 10 . in the 01 , 10 and 11 modes, the adc channel data to be read is latched at the beginning of a reading, in order to prevent the case of erroneous data when a dr pulse happens during a read. in these modes the two channels are independent. when these bits are equal to 11 , 10 or 01 , they con- trol which adcs data ready is present on the dr pin. when drmode = 00 , the data ready pin output is synchronized with the lagging adc channel (defined by the phase register) and the adcs are linked together. in this mode, the output of the two adcs are latched synchronously at the moment of the dr event. this prevents having bad synchronization between the two adcs. the output is also latched at the beginning of a reading in order not to be updated during a read and not to give erroneous data. this mode is very useful for power metering applications because the data from both adcs can be retrieved using this single data ready event which is processed synchronously, even in case of a large phase difference. this mode works as if there was one adc channel and its data would be 48 bits long, and contain both channel data. as a consequence, if one channel is in reset or shutdown when drmode = 00 , no data ready pulse will be present at the outputs (if both channels are not ready in this mode, the data is not considered as ready). see section b.5.9 data ready pin (dr) for more details about data ready pin behavior. b.6.4.4 dr status flag C drstatus<1:0> these bits indicate the dr status of both channels, respectively. these flags are set to logic high after each read of the status/com register. these bits are cleared when a dr event has happened on its respective adc channel. writing these bits has no effect. note: these bits are useful if multiple devices share the same dr output pin (dr_hizn = 0 ) in order to understand from which device the dr event has happened. this configuration can be used for three-phase power metering systems where all three phases share the same data ready pin. in case the drmode = 00 (linked adcs), these data ready status bits will be updated synchronously upon the same event (lagging adc is ready). these bits are also useful in systems where the dr pin is not used to save mcu i/o. downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 461 pic18f87j72 family register b-4: status and communi cation register (address 0x09) r/w-1 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r-1 r-1 read<1> read<0> dr_lty dr_hizn drmode<1> drmode<0> drstatus <1> drstatus <0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-6 read: address loop setting bits 11 = address counter loops on entire register map 10 = address counter loops on register types (default) 01 = address counter loops on register groups 00 = address not incremented, continually read same single register bit 5 dr_lty: data ready latency control bit 1 = no latency conversion, dr pulses after 3 drclk periods (default) 0 = unsettled data is available after every drclk period bit 4 dr_hizn: data ready pin inactive state control bit 1 = the data ready pin default state is a logic high when data is not ready 0 = the data ready pin default state is high impedance when data is not ready (default) bit 3-2 drmode<1:0>: data ready pin (dr) control bits 11 = both data ready pulses from adc0 and adc channel 1 are output on the dr pin 10 = data ready pulses from adc channel 1 are output on the dr pin; dr from adc channel 0 are not present on the pin 01 = data ready pulses from adc channel 0 are output on the dr pin; dr from adc channel 1 are not present on the pin 00 = data ready pulses from the lagging adc between the two are output on the dr pin; the lagging adc selection depends on the phase register and on the osr (default) bit 1-0 drstatus<1:0>: data ready status bits 11 = adc channel 1 and channel 0 data not ready (default) 10 = adc channel 1 data not ready, adc channel 0 data ready 01 = adc channel 0 data not ready, adc channel 1 data ready 00 = adc channel 1 and channel 0 data ready downloaded from: http:///
pic18f87j72 family ds39979a-page 462 preliminary ? 2010 microchip technology inc. b.6.5 configuration registers the configuration registers contain settings for the internal clock prescaler, the oversampling ratio, the channel 0 and channel 1 width settings, the state of the channel resets and shutdowns, the dithering algo- rithm control (for idle tones suppression), and the control bits for the external v ref and external clk. register b-5: config1: configuration register 1: (address 0x0a) r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r-0 r-0 prescale <1> prescale <0> osr<1> osr<0> width<1> width<0> r r bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-6 prescale<1:0>: internal master clock (amclk) prescaler value bits 11 = amclk = mclk/8 10 = amclk = mclk/4 01 = amclk = mclk/2 00 = amclk = mclk (default) bit 5-4 osr<1:0>: oversampling ratio for delta-sigma a/d conversion bits (all channels, dm clk/drclk) 11 = 256 10 = 128 01 = 64 (default) 00 = 32 bit 3-2 width<1:0>: adc channel output data word width bits 11 = 24-bit mode on both channels 10 = 24-bit mode on channel 1, 16-bit mode on channel 0 01 = 16-bit mode on channel 1, 24-bit mode on channel 0 00 = 16 bit mode on both channels (default) bit 1-0 reserved: maintain as 0 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 463 pic18f87j72 family register b-6: config2: configuration regist er 2 (address 0x0b) r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r-0 reset_ch1 reset_ch0 shutdown <1> shutdown <0> dither<1> dither<0> vrefext r bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-6 reset<1:0>: reset mode setting for adcs bits 11 = both ch0 and ch1 adc are in reset mode 10 = ch1 adc in reset mode 01 = ch0 adc in reset mode 00 = neither channel in reset mode (default) bit 5-4 shutdown<1:0>: shutdown mode setting for adcs bits 11 = both ch0 and ch1 adc are in shutdown 10 = ch1 adc is in shutdown 01 = ch0 adc is in shutdown 00 = neither channel in shutdown(default) bit 3-2 dither<1:0>: control for dithering circuit bits 11 = both ch0 and ch1 adc have dithering circuit applied (default) 10 = only ch1 adc has dithering circuit applied 01 = only ch0 adc has dithering circuit applied 00 = neither channel has dithering circuit applied bit 1 vrefext: internal voltage reference shutdown control bit 1 = internal voltage reference disabled; an external voltage reference must be placed between refin+/out and refin- 0 = internal voltage reference enabled (default) bit 0 reserved: resets as 0 ; program as 1 after any reset event downloaded from: http:///
pic18f87j72 family ds39979a-page 464 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 465 pic18f87j72 family index a a/d a/d converter interrupt, configuring ........................ 277 acquisition requirements ......................................... 278 adcal bit................................................................. 281 adcon0 register..................................................... 273 adcon1 register..................................................... 273 adcon2 register..................................................... 273 adresh register............................................. 273, 276 adresl register ..................................................... 273 analog port pins, configuring................................... 279 associated registers ................................................ 281 configuring the module........................................... .. 277 conversion clock (t ad ) ............................................ 279 conversion status (go/done bit) ........................... 276 conversions .............................................................. 280 converter calibration ................................................ 281 converter characteristics ......................................... 421 operation in power-managed modes ....................... 281 overview ................................................................... 273 selecting and configuring automatic acquisition time ............................................... 279 special event trigger (ccp)..................................... 280 use of the ccp2 trigger........................................... 280 absolute maximum ratings .............................................. 389 ac (timing) characteristics .............................................. 404 load conditions for device timing specifications.................................................... 405 parameter symbology .............................................. 404 temperature and voltage specifications .................. 405 timing conditions ............................................ ......... 405 ackstat ......................................................................... 22 9 ackstat status flag ...................................................... 229 adcal bit......................................................................... 281 adcon0 register............................................................. 273 go/done bit............................................................ 276 adcon1 register............................................................. 273 adcon2 register............................................................. 273 addfsr ........................................................................... 377 addlw ............................................................................. 340 addressable universal synchronous asynchronous receiver transmitter (ausart). see ausart. addulnk......................................................................... 37 7 addwf ............................................................................. 340 addwfc .......................................................................... 341 adresh register............................................................. 273 adresl register ................................................ ..... 273, 276 afe analog inputs ................................................ ............ 284 block diagram........................................................... 435 boost mode............................................................... 444 data ready pin (dr ) ................................................ 454 delta-sigma adc architecture ................................. 284 block diagram .................................................. 444 delta-sigma modulator ............................................. 444 electrical characteristics................................... 423C425 external voltage reference ...................................... 447 internal clock chain.................................................. 449 internal registers...................................................... 456 internal voltage reference ............................... 284, 447 output coding........................................................... 445 output data rates (table) ......................................... 439 phase delay block............................................ 284, 448 power-on reset ....................................................... 447 programmable gain amplifiers................................. 284 register map .................................................... 285, 456 registers config1.......................................................... 462 config2.......................................................... 463 data_chn....................................................... 457 gain................................................................. 459 phase ............................................................. 458 status/com .................................................. 461 required connections .............................................. 287 resolution................................................................. 446 serial interface ................................................. 286, 449 continuous communication ............................. 452 serial interface characteristics................................. 426 sinc 3 filter ...................................................... 284, 444 terminology................................................ ...... 438C443 using ........................................................................ 288 voltage reference............................................. ....... 447 analog-to-digital converter. see a/d. andlw............................................................................. 341 andwf............................................................................. 342 assembler mpasm assembler .................................................. 38 6 ausart asynchronous mode................................................ . 264 associated registers, receive......................... 267 associated registers, transmit........................ 265 receiver ........................................................... 266 setting up 9-bit mode with address detect......................................... 266 transmitter ....................................................... 264 baud rate generator (brg) .................................... 262 associated registers........................................ 262 baud rate error, calculating............................ 262 baud rates, asynchronous modes .................. 263 high baud rate select (brgh bit) .................. 262 operation in power-managed modes............... 262 sampling .......................................................... 262 synchronous master mode....................................... 268 associated registers, receive......................... 270 associated registers, transmit........................ 269 reception ......................................................... 270 transmission .................................................... 268 synchronous slave mode......................................... 271 associated registers, receive......................... 272 associated registers, transmit........................ 271 reception ......................................................... 272 transmission .................................................... 271 b baud rate generator ............................................. .......... 225 bc..................................................................................... 342 bcf .................................................................................. 343 bf ..................................................................................... 229 bf status flag .................................................................. 229 bias generation (lcd) charge pump design considerations ...................... 177 block diagrams a/d............................................................................ 276 afe, required connections ..................................... 287 analog input model................................................ ... 277 ausart receive ..................................................... 266 ausart transmit .................................................... 2 64 downloaded from: http:///
pic18f87j72 family ds39979a-page 466 preliminary ? 2010 microchip technology inc. baud rate generator ............................................. ... 225 capture mode operation .......................................... 160 comparator analog input model ............................... 297 comparator i/o operating modes............................. 294 comparator output ................................................... 296 comparator voltage reference ................................ 300 comparator voltage reference output buffer example ................................................. 301 compare mode operation ........................................ 161 connections for on-chip voltage regulator............. 327 ctmu........................................................................ 303 ctmu current source calibration circuit ................. 306 ctmu typical connections and internal configuration for pulse delay generation ........ 314 ctmu typical connections and internal configuration for time measurement ............... 313 delta-sigma adc (simplified)................................... 444 device clock ............................................................... 25 dual-channel afe ................................................. ... 435 eusart receive ..................................................... 250 eusart transmit .................................................... 248 external power-on reset circuit (slow v dd power-up).......................................... 45 fail-safe clock monitor (fscm) ............................... 329 generic i/o port operation ....................................... 105 interrupt logic ............................................................. 90 lcd clock generation .............................................. 172 lcd driver module .................................................. . 167 lcd regulator connections (m0 and m1) ................ 174 mssp (i 2 c master mode) ......................................... 223 mssp (i 2 c mode) ................................................ ..... 204 mssp (spi mode)............................................. ........ 195 on-chip reset circuit ................................................. 43 pic18f8xj72.............................................................. 12 pll.............................................................................. 30 pwm operation (simplified) ..................................... 163 reads from flash program memory.......................... 81 resistor ladder connections for m2 configuration............................................... 175 resistor ladder connections for m3 configuration............................................... 176 rtcc ........................................................................ 139 single comparator .................................................... 295 spi master/slave connection ................................... 199 table read operation............................................. .... 77 table write operation ................................................. 78 table writes to flash program memory ..................... 83 timer0 in 16-bit mode............................................... 124 timer0 in 8-bit mode................................................. 124 timer1 (16-bit read/write mode) ............................. 128 timer1 (8-bit mode) ........................................... ....... 128 timer2 ....................................................................... 134 timer3 (16-bit read/write mode) ............................. 136 timer3 (8-bit mode) ........................................... ....... 136 watchdog timer............................................ ............ 325 bn ..................................................................................... 343 bnc................................................................................... 344 bnn................................................................................... 344 bnov ................................................................................ 345 bnz ................................................................................... 345 bor. see brown-out reset. bov................................................................................... 348 bra................................................................................... 346 break character (12-bit) transmit and receive ............... 253 brg. see baud rate generator. brgh bit txsta1 register...................................................... 243 txsta2 register...................................................... 262 brown-out reset (bor)........................................... ........... 45 and on-chip voltage regulator................................ 328 detecting .................................................................... 45 bsf................................................................................... 346 btfsc .............................................................................. 347 btfss .............................................................................. 347 btg .................................................................................. 348 bz ..................................................................................... 349 c c compilers mplab c18 .............................................................. 386 call........................................................................... ...... 349 callw ............................................................................. 378 capture (ccp module) ............................................... ...... 160 associated registers ........................................... ..... 162 ccp pin configuration........................................... ... 160 ccpr2h:ccpr2l registers.................................... 160 software interrupt .................................................. ... 160 timer1/timer3 mode selection................................. 160 capture/compare/pwm (ccp) ........................................ 1 57 capture mode. see capture. ccp mode and timer resources............................. 158 ccprxh register..................................................... 158 ccprxl register ..................................................... 158 compare mode. see compare. configuration ............................................................ 1 58 interaction of ccp1 and ccp2 for timer resources .............................................. 159 interconnect configurations...................................... 158 charge time measurement unit (ctmu)......................... 303 associated registers ........................................... ..... 317 calibrating the module.............................................. 305 creating a delay ....................................................... 314 effects of a reset ..................................................... 314 measuring capacitance with the ctmu ................... 311 measuring time ........................................................ 313 module initialization .................................................. 305 operation .................................................................. 304 during sleep and idle modes ........................... 314 clkia ............................................................................. .... 20 clock sources........................................................ ............. 27 default system clock on reset .................................. 28 selection using osccon register............................ 28 clrf ................................................................................ 35 0 clrwdt .......................................................................... 350 code examples 16 x 16 signed multiply routine ................................. 88 16 x 16 unsigned multiply routine ............................. 88 8 x 8 signed multiply routine ..................................... 87 8 x 8 unsigned multiply routine ................................. 87 afe clock source and interrupt configuration......... 290 capacitance calibration routine .............................. 310 changing between capture prescalers.................... 160 computed goto using an offset value.................... 59 current calibration routine ...................................... 308 erasing a flash program memory row...................... 82 fast register stack ............................................... ..... 59 how to clear ram (bank 1) using indirect addressing . 71 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 467 pic18f87j72 family implementing a real-time clock using a timer1 interrupt service ................................... 131 initializing porta..................................................... 106 initializing portb..................................................... 108 initializing portc..................................................... 111 initializing portd..................................................... 114 initializing porte..................................................... 116 initializing portf ..................................................... 118 initializing portg .................................................... 121 initializing the mssp module for using the afe....... 290 loading the sspbuf (sspsr) register.................. 198 overall structure for using the afe.......................... 289 reading a flash program memory word ................... 81 reading data from afe during interrupt................. 292 routine for capacitive touch switch ........................ 312 saving status, wreg and bsr registers in ram.............................................. 104 setting the rtcwren bit ........................................ 151 setup for ctmu calibration routines....................... 307 single-word write to flash program memory ............ 85 writing and reading afe registers through mssp ............................................. .... 291 writing to flash program memory .............................. 84 code protection ............................................... ................. 319 comf ............................................................................... 351 comparator ....................................................................... 293 analog input connection considerations.................. 297 associated registers ................................................ 297 configuration............................................................. 294 effects of a reset...................................................... 296 interrupts................................................................... 296 operation .................................................................. 295 operation during sleep ............................................ 296 outputs ..................................................................... 295 reference ................................................................. 295 external signal............................................... ... 295 internal signal .............................................. ..... 295 response time............................................... .......... 295 comparator specifications................................................ 403 comparator voltage reference ...................................... .. 299 accuracy and error .............................................. ..... 300 associated registers ................................................ 301 configuring................................................................ 299 connection considerations....................................... 300 effects of a reset...................................................... 300 operation during sleep ............................................ 300 compare (ccp module) .............................................. ..... 161 associated registers ................................................ 162 ccp pin configuration.............................................. 161 ccpr2 register ....................................................... 161 software interrupt ..................................................... 16 1 special event trigger................................ 137, 161, 280 timer1/timer3 mode selection................................. 161 computed goto ................................................................ 59 configuration bits.............................................................. 319 configuration mismatch (cm) ............................................. 4 5 configuration register protection ..................................... 331 core features easy migration .............................................................. 9 extended instruction set.......................................... ..... 9 memory options............................................................ 9 nanowatt technology ............................................. ...... 9 oscillator options and features ................................... 9 cpfseq ........................................................................... 351 cpfsgt ........................................................................... 352 cpfslt .................................................................. .......... 352 crystal oscillator/ceramic resonator................................. 29 customer change notification service............................. 475 customer notification service .......................................... 475 customer support............................................... .............. 475 d data addressing modes ................................................. .... 71 comparing addressing modes with the extended instruction set enabled ...................... 75 direct .......................................................................... 7 1 indexed literal offset ................................................. 7 4 bsr .................................................................... 76 instructions affected ........................................... 74 mapping access bank ........................................ 76 indirect........................................................................ 71 inherent and literal............................................ ......... 71 data memory ................................................................ ...... 62 access bank.............................................................. . 64 bank select register (bsr) .................................... ... 62 extended instruction set ......................................... ... 74 general purpose registers ........................................ 64 memory maps pic18f86j72/87j72 devices ............................. 63 special function registers................................. 65 special function registers...................................... ... 65 daw ................................................................................. 353 dc characteristics............................................................ 40 0 power-down and supply current ............................. 392 supply voltage ............................................. ............ 391 dcfsnz ................................................................... ........ 354 decf ................................................................................ 353 decfsz ........................................................................... 354 default system clock ......................................................... 28 details on individual family members ................................ 11 development support ................................................... .... 385 device overview............................................................... .... 9 features (80-pin devices)...................................... .... 11 direct addressing ............................................................... 72 dual-channel analog front end (afe) ............................ 434 dual-channel analog front end (afe). see afe. e effect on standard pic18 instructions.............................. 381 effects of power-managed modes on various clock sources ......................................................... ... 33 electrical characteristics ............................... ................... 389 enhanced universal synchronous asynchronous receiver transmitter (eusart). see eusart. envreg pin .................................................................... 327 equations a/d acquisition time ................................................ 278 a/d minimum charging time ................................... 278 calculating the minimum required acquisition time ............................................... 278 lcd static and dynamic current ............................. 177 errata .................................................................. .................. 7 eusart asynchronous mode................................................ . 248 12-bit break transmit and receive.................. 253 associated registers, receive......................... 251 associated registers, transmit........................ 249 auto-wake-up on sync break character ......... 252 receiver ........................................................... 250 setting up 9-bit mode with address detect ...... 250 transmitter ....................................................... 248 downloaded from: http:///
pic18f87j72 family ds39979a-page 468 preliminary ? 2010 microchip technology inc. baud rate generator (brg)..................................... 243 auto-baud rate detect ..................................... 246 baud rate error, calculating ............................ 243 baud rates, associated registers ................... 243 baud rates, asynchronous modes................... 244 high baud rate select (brgh bit)................... 243 operation in power-managed modes ............... 243 sampling ........................................................... 243 synchronous master mode ....................................... 254 associated registers, receive ......................... 256 associated registers, transmit ........................ 255 reception.......................................................... 256 transmission..................................................... 254 synchronous slave mode ......................................... 257 associated registers, receive ......................... 258 associated registers, transmit ........................ 257 reception.......................................................... 258 transmission..................................................... 257 extended instruction set addfsr ................................................................... 377 addulnk................................................................. 377 callw...................................................................... 378 movsf ..................................................................... 378 movss ..................................................................... 379 pushl ...................................................................... 379 subfsr ................................................................... 380 subulnk ................................................................. 380 external oscillator modes clock input (ec and ecpll modes) .......................... 30 hs ............................................................................... 29 f fail-safe clock monitor........................................ ..... 319, 329 exiting fail-safe operation ....................................... 330 interrupts in power-managed modes ........................ 330 por or wake-up from sleep ................................... 330 wdt during oscillator failure .................................. 329 fast register stack............................................................. 59 firmware instructions........................................................ 33 3 flash configuration words................................................ 319 flash program memory....................................................... 77 associated registers .................................................. 86 control registers ........................................................ 78 eecon1 and eecon2 ...................................... 78 tablat (table latch) register.......................... 80 tblptr (table pointer) register ....................... 80 erase sequence ................................................ ......... 82 erasing ........................................................................ 82 operation during code-protect .................................. 86 reading.................................................. ..................... 81 table pointer boundaries based on operation......................... 80 table pointer boundaries ........................................... 80 table reads and table writes ................................... 77 write sequence .............................................. ............ 83 write sequence (word programming) ........................ 85 writing ......................................................................... 83 unexpected termination..................................... 86 write verify ......................................................... 86 fscm. see fail-safe clock monitor. g goto................................................................................ 355 h hardware multiplier............................................................. 87 8 x 8 multiplication algorithms .................................... 87 operation .................................................................... 87 performance comparison (table)................................ 87 i i/o ports............................................................................ 1 05 input voltage considerations.................................... 10 5 open-drain outputs.................................................. 106 output pin drive ....................................................... 105 pin capabilities ............................................... .......... 105 pull-up configuration ......................................... ....... 106 i 2 c mode (mssp) ........................................................... .. 204 acknowledge sequence timing ............................... 232 associated registers ........................................... ..... 238 baud rate generator ............................................. .. 225 bus collision during a repeated start condition................... 236 during a stop condition ................................... 237 clock arbitration ....................................................... 226 clock stretching........................................................ 21 8 10-bit slave receive mode (sen = 1) ............. 218 10-bit slave transmit mode ............................. 218 7-bit slave receive mode (sen = 1) ............... 218 7-bit slave transmit mode ............................... 218 clock synchronization and the ckp bit.................... 219 effects of a reset ..................................................... 233 general call address support .................................. 222 i 2 c clock rate w/brg.............................................. 225 master mode............................................................. 223 baud rate generator ....................................... 225 operation.......................................................... 224 reception ......................................................... 229 repeated start condition timing ..................... 228 start condition timing ...................................... 227 transmission .................................................... 229 multi-master communication, bus collision and arbitration ............................................... ... 233 multi-master mode .................................................... 233 operation .................................................................. 209 read/write bit information (r/w bit) ................ 209, 211 registers .................................................................. 2 04 serial clock (sck/scl)............................................ 211 slave mode............................................................... 209 address masking .............................................. 210 addressing........................................................ 209 reception ......................................................... 211 transmission .................................................... 211 sleep operation................................................ ........ 233 stop condition timing ........................................... ... 232 incf ................................................................................. 355 incfsz........................................................................... .. 356 in-circuit debugger.............................................. ............. 331 in-circuit serial programming (icsp)....................... 319, 331 indexed literal offset addressing and standard pic18 instructions.............................. 381 indexed literal offset mode.......................................... .... 381 indirect addressing ............................................................. 72 infsnz............................................................................. 3 56 initialization conditions for all registers ....................... 49C54 instruction cycle .................................................. ............... 60 clocking scheme..................................................... ... 60 flow/pipelining............................................................ 60 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 469 pic18f87j72 family instruction set ................................................................... 333 addlw ..................................................................... 340 addwf..................................................................... 340 addwf (indexed literal offset mode) ..................... 382 addwfc .................................................................. 341 andlw ..................................................................... 341 andwf..................................................................... 342 bc ............................................................................. 342 bcf........................................................................... 343 bn ............................................................................. 343 bnc .......................................................................... 344 bnn .......................................................................... 344 bnov........................................................................ 345 bnz........................................................................... 345 bov .......................................................................... 348 bra........................................................................... 346 bsf ........................................................................... 346 bsf (indexed literal offset mode) ........................... 382 btfsc ...................................................................... 347 btfss ...................................................................... 347 btg........................................................................... 348 bz ............................................................................. 349 call ......................................................................... 349 clrf......................................................................... 350 clrwdt................................................................... 350 comf ....................................................................... 351 cpfseq ................................................................... 351 cpfsgt ................................................................... 352 cpfslt .................................................................... 352 daw.......................................................................... 353 dcfsnz ................................................................... 354 decf ........................................................................ 353 decfsz.................................................................... 354 extended instructions .......................................... ..... 376 considerations when enabling ......................... 381 syntax............................................................... 376 use with mplab ide tools .............................. 383 general format.............................................. ........... 336 goto ....................................................................... 355 incf.......................................................................... 355 incfsz ..................................................................... 356 infsnz ..................................................................... 356 iorlw ...................................................................... 357 iorwf ...................................................................... 357 lfsr......................................................................... 358 movf........................................................................ 358 movff ..................................................................... 359 movlb ..................................................................... 359 movlw .................................................................... 360 movwf .................................................................... 360 mullw ..................................................................... 361 mulwf..................................................................... 361 negf ........................................................................ 362 nop .......................................................................... 362 opcode field descriptions........................................ 334 pop .......................................................................... 363 push ........................................................................ 363 rcall ...................................................................... 364 reset ...................................................................... 364 retfie ..................................................................... 365 retlw ..................................................................... 365 return ................................................................... 366 rlcf......................................................................... 366 rlncf ...................................................................... 367 rrcf ........................................................................ 367 rrncf ................... .................................................. 368 setf ........................................................................ 368 setf (indexed literal offset mode) ......................... 382 sleep ...................................................................... 369 standard instructions........................................... ..... 333 subfwb .................................................................. 369 sublw..................................................................... 3 70 subwf..................................................................... 37 0 subwfb .................................................................. 371 swapf..................................................................... 3 71 tblrd...................................................................... 372 tblwt ..................................................................... 373 tstfsz .................................................................... 374 xorlw .................................................................... 374 xorwf .................................................................... 375 intcon register rbif bit .................................................................... 108 inter-integrated circuit. see i 2 c mode. internal lcd voltage regulator specifications................. 403 internal oscillator block ....................................... ............... 31 adjustment.................................................................. 32 intio modes ............................................ .................. 31 intosc frequency drift ....................................... ..... 32 intosc output frequency ...................................... .. 32 intpll modes............................................. ............... 31 internal rc oscillator use with wdt........................................................... 325 internal voltage regulator specifications......................... 403 internet address ............................................................... 475 interrupt sources ................................................... ........... 319 a/d conversion complete ........................................ 277 capture complete (ccp) ......................................... 160 compare complete (ccp) ....................................... 161 interrupt-on-change (rb7:rb4)............................... 108 tmr0 overflow......................................................... 125 tmr2 to pr2 match (pwm)..................................... 163 tmr3 overflow......................................................... 137 interrupts ............................................................................ 89 during, context saving............................................. 104 interrupt-on-change (rb7:rb4) flag (rbif bit).......................................................... 108 intx pin.................................................................... 104 portb, interrupt-on-change................................... 104 tmr0........................................................................ 104 intosc, intrc. see internal oscillator block. iorlw ............................................................................ .. 357 iorwf.............................................................................. 357 llcd associated registers........................................... ..... 193 bias generation................................................ ........ 173 bias configurations .......................................... 17 4 m0 and m1 ............................................... 174 m2 ............................................................ 175 m3 ............................................................ 176 bias types........................................................ 173 voltage regulator............................................. 1 73 charge pump ................................................... 174, 1 77 clock source selection ............................................ 172 configuring the module ........................................... . 192 frame frequency .............................................. ....... 178 interrupts .................................................................. 190 lcdcon register .................................................... 168 lcddata register .................................................. 168 downloaded from: http:///
pic18f87j72 family ds39979a-page 470 preliminary ? 2010 microchip technology inc. lcdps register........................................................ 168 lcdreg register..................................................... 168 lcdse register........................................................ 168 multiplex types ......................................................... 177 operation during sleep ............................................ 191 pixel control.............................................................. 177 segment enables...................................................... 177 waveform generation .......................................... ..... 178 lcd driver .......................................................................... 10 lcdcon register............................................................. 168 lcddata register ........................................................... 168 lcdps register................................................................ 16 8 lcdreg register............................................................. 168 lcdse register................................................................ 16 8 lfsr ................................................................................. 358 liquid crystal display (lcd) driver .................................. 167 low-voltage detection ........................................... ........... 327 m master clear (mclr ) .......................................................... 45 master synchronous serial port (mssp). see mssp. memory organization............................................ .............. 55 data memory .............................................................. 62 program memory ........................................................ 55 memory programming requirements ............................... 402 microchip internet web site .............................................. 475 movf................................................................................ 358 movff.............................................................................. 359 movlb.............................................................................. 359 movlw............................................................................. 360 movsf ............................................................................. 378 movss ............................................................................. 379 movwf ............................................................................ 360 mplab asm30 assembler, linker, librarian ................... 386 mplab integrated development environment software............................................... 385 mplab pm3 device programmer..................................... 388 mplab real ice in-circuit emulator system................. 387 mplink object linker/mplib object librarian ................ 386 mssp ack pulse................................................ ......... 209, 211 control registers (general) ....................................... 195 module overview ................................................ ...... 195 sspbuf register ..................................................... 200 sspsr register ....................................................... 200 mullw ............................................................................. 361 mulwf ............................................................................. 361 n negf ................................................................................ 362 nop .................................................................................. 362 o oscillator configuration....................................................... 25 ec ............................................................................... 25 ecpll......................................................................... 25 hs ............................................................................... 25 hspll......................................................................... 25 internal oscillator block .............................................. 31 intio1 ........................................................................ 25 intio2 ........................................................................ 25 intpll1 ...................................................................... 25 intpll2 ...................................................................... 25 oscillator selection ........................................................... 319 oscillator start-up timer (ost) .......................................... 33 oscillator switching............................................................. 27 oscillator transitions .......................................................... 28 oscillator, timer1...................................................... 127, 137 oscillator, timer3........................................................ ...... 135 p packaging ......................................................................... 429 details............................................................... ........ 430 marking ..................................................................... 429 pin functions av dd ........................................................................... 19 av ss ........................................................................... 19 ch0+/ch0- ................................................................. 20 ch1+/ch1- ................................................................. 20 csa ............................................................................ 20 dr .............................................................................. 20 envreg ............................................................... ..... 19 mclr ......................................................................... 13 osc1/clki/ra7 ......................................................... 13 osc2/clko/ra6 ....................................................... 13 ra0/an0............................................................. ........ 13 ra1/an1/seg18 ....................................................... . 13 ra2/an2/v ref - .......................................................... 13 ra3/an3/v ref + ......................................................... 13 ra4/t0cki/seg14 ..................................................... 13 ra5/an4/seg15 ....................................................... . 13 rb0/int0/seg30 ....................................................... 14 rb1/int1/seg8 ......................................................... 14 rb2/int2/seg9/cted1............................................. 14 rb3/int3/seg10/cted2........................................... 14 rb4/kbi0/seg11 ....................................................... 14 rb5/kbi1/seg29 ....................................................... 14 rb6/kbi2/pgc ........................................................... 14 rb7/kbi3/pgd ........................................................... 14 rc0/t1oso/t13cki .................................................. 15 rc1/t1osi/ccp2/seg32 .......................................... 15 rc2/ccp1/seg13 ..................................................... 15 rc3/sck/scl/seg17................................................ 1 5 rc4/sdi/sda/seg16................................................. 15 rc5/sdo/seg12 ....................................................... 1 5 rc6/tx1/ck1/seg27 ................................................ 15 rc7/rx1/dt1/seg28 ................................................ 15 rd0/seg0/ctpls ..................................................... 16 rd0/seg1 .................................................................. 16 rd2/seg2 .................................................................. 16 rd3/seg3 .................................................................. 16 rd4/seg4 .................................................................. 16 rd5/seg5 .................................................................. 16 rd6/seg6 .................................................................. 16 rd7/seg7 .................................................................. 16 re0/lcdbias1 .......................................................... 17 re1/lcdbias2 .......................................................... 17 re2/lcdbias3 .......................................................... 17 re3/com0 ................................................................. 17 re4/com1 ................................................................. 17 re5/com2 ................................................................. 17 re6/com3 ................................................................. 17 re7/ccp2/seg31...................................................... 17 refin-........................................................................ 20 refin+/out .............................................................. 20 reset ........................................................................ 20 rf1/an6/c2out/seg19 ........................................... 18 rf2/an7/c1out/seg20 ........................................... 18 rf3/an8/seg21/c2inb............................................. 18 rf4/an9/seg22/c2ina............................................. 18 rf5/an10/cv ref /seg23/c1inb ............................... 18 rf6/an11/seg24/c1ina........................................... 18 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 471 pic18f87j72 family rf7/an5/ss /seg25................................................... 18 rg0/lcdbias0 .......................................................... 19 rg1/tx2/ck2 ............................................................. 19 rg2/rx2/dt2/v lcap 1................................................ 19 rg3/v lcap 2................................................................ 19 rg4/seg26/rtcc ..................................................... 19 sav dd ......................................................................... 20 sav ss ......................................................................... 20 scka .......................................................................... 20 sdia............................................................................ 20 sdoa.......................................................................... 20 sv dd ........................................................................... 20 sv ss ........................................................................... 20 v dd ............................................................................. 19 v ddcore /v cap ............................................................ 19 v ss .............................................................................. 19 pinout i/o descriptions ........................................ ............... 13 pll...................................................................................... 30 hspll and ecpll oscillator modes ......................... 30 use with intosc........................................................ 30 pop .................................................................................. 363 por. see power-on reset. porta associated registers ................................................ 107 lata register........................................................... 106 porta register ....................................................... 106 trisa register ......................................................... 106 portb associated registers ................................................ 110 latb register........................................................... 108 portb register ....................................................... 108 rb7:rb4 interrupt-on-change flag (rbif bit)......... 108 trisb register ......................................................... 108 portc associated registers ................................................ 113 latc register .......................................................... 111 portc register ....................................................... 111 rc3/sck/scl/seg17 pin........................................ 211 trisc register......................................................... 111 portd associated registers ................................................ 115 latd register .......................................................... 114 portd register ....................................................... 114 trisd register......................................................... 114 porte associated registers ................................................ 117 late register........................................................... 116 porte register ....................................................... 116 trise register ......................................................... 116 portf associated registers ................................................ 120 latf register........................................................... 118 portf register ....................................................... 118 trisf register ......................................................... 118 portg associated registers ................................................ 122 latg register .......................................................... 121 portg register....................................................... 121 trisg register......................................................... 121 power-managed modes ............................................... ....... 35 and spi operation ............................................ ........ 203 clock sources............................................................. 35 clock transitions and status indicators...................... 36 entering....................................................................... 35 exiting idle and sleep modes ..................................... 41 by interrupt ......................................................... 41 by reset ............................................................. 41 by wdt time-out ............................................... 41 without an oscillator start-up delay .................. 41 idle modes ................................................ .................. 39 pri_idle ........................................................... 40 rc_idle ............................................................ 41 sec_idle .......................................................... 40 multiple sleep commands.......................................... 36 run modes .................................................. ............... 36 pri_run............................................................ 36 rc_run............................................................. 38 sec_run .......................................................... 36 selecting..................................................................... 35 sleep mode .................................................. .............. 39 osc1 and osc2 pin states............................... 33 summary (table) ...................................................... ... 35 power-on reset (por)....................................................... 45 power-up delays ............................................................ .... 33 power-up timer (pwrt) ........................................... ... 33, 46 time-out sequence ............................................ ........ 46 prescaler, capture............................................... ............. 160 prescaler, timer0 .................................................. ........... 125 prescaler, timer2 .................................................. ........... 164 pri_idle mode.................................................................. 40 pri_run mode .................................................................. 36 program counter ............................................... ................. 57 pcl, pch and pcu registers ................................... 57 pclath and pclatu registers ............................... 57 program memory extended instruction set ......................................... ... 73 flash configuration words ...................................... ... 56 hard memory vectors................................................. 5 6 instructions ................................................................. 61 two-word ........................................................... 61 interrupt vector...................................................... ..... 56 look-up tables................................................ ........... 59 memory maps............................................................. 55 hard vectors and configuration words.............. 56 reset vector............................................................... 56 program verification and code protection ....................... 331 programming, device instructions............................... ..... 333 pulse-width modulation. see pwm (ccp module). push................................................................... ............. 363 push and pop instructions...................................... ......... 58 pushl.............................................................................. 379 pwm (ccp module) associated registers........................................... ..... 165 duty cycle ................................................................ 164 example frequencies/resolutions ........................... 164 period ....................................................................... 163 setup for pwm operation ........................................ 165 tmr2 to pr2 match ................................................. 1 63 q q clock ............................................................................. 1 64 r ram. see data memory. rc_idle mode................................................................... 41 rc_run mode................................................................... 38 rcall .................................................................. ............ 364 rcon register bit status during initialization..................................... 48 downloaded from: http:///
pic18f87j72 family ds39979a-page 472 preliminary ? 2010 microchip technology inc. reader response ................................................. ............ 476 real-time clock and calendar operation .................................................................. 149 registers................................................................... 1 40 real-time clock and calendar (rtcc)............................ 139 register file ........................................................................ 64 register file summary.................................................. 66C69 registers adcon0 (a/d control 0) .......................................... 273 adcon1 (a/d control 1) .......................................... 274 adcon2 (a/d control 2) .......................................... 275 alrmcfg (alarm configuration) ............................. 143 alrmday (alarm day value) .................................. 147 alrmhr (alarm hours value) ................................. 148 alrmmin (alarm minutes value) ............................. 148 alrmmnth (alarm month value)............................ 147 alrmrpt (alarm calibration).................................. 144 alrmsec (alarm seconds value)........................... 148 alrmwd (alarm weekday value) ........................... 147 baudcon1 (baud rate control) ............................. 242 ccpxcon (ccpx control) ....................................... 157 cmcon (comparator control) ................................. 293 config1 (afe configuration 1) .............................. 462 config1h (configuration 1 high) ........................... 321 config1l (configuration 1 low)............................. 321 config2 (afe configuration 2) .............................. 463 config2h (configuration 2 high) ........................... 323 config2l (configuration 2 low)............................. 322 config3h (configuration 3 high) ........................... 324 config3l (configuration 3 high) ............................ 323 ctmuconh (ctmu control high) .......................... 315 ctmuconl (ctmu control low)............................ 316 ctmuicon (ctmu current control) ....................... 317 cvrcon (comparator voltage reference control)............................................ 299 data_chn (afe channel output)........................... 457 day (day value)....................................................... 145 devid1 (device id register 1)................................. 324 devid2 (device id register 2)................................. 324 eecon1 (eeprom control 1)................................... 79 gain (afe gain configuration)................................ 459 hour (hour value) .................................................. 146 intcon (interrupt control) ......................................... 91 intcon2 (interrupt control 2).................................... 92 intcon3 (interrupt control 3).................................... 93 ipr1 (peripheral interrupt priority 1)......................... 100 ipr2 (peripheral interrupt priority 2)......................... 101 ipr3 (peripheral interrupt priority 3)......................... 102 lcdcon (lcd control)............................................ 168 lcddatax (lcd data) ............................................ 171 lcdps (lcd phase) ................................................ 169 lcdreg (lcd voltage regulator control) .............. 173 lcdsex (lcd segment enable) .............................. 170 minute (minute value)............................................ 146 month (month value) ............................................. 145 osccon (oscillator control) ..................................... 26 osctune (oscillator tuning) .................................... 27 padcfg1 (pad configuration)................................. 142 phase (afe phase delay) ...................................... 458 pie1 (peripheral interrupt enable 1) ........................... 97 pie2 (peripheral interrupt enable 2) ........................... 98 pie3 (peripheral interrupt enable 3) ........................... 99 pir1 (peripheral interrupt request (flag) 1) .............. 94 pir2 (peripheral interrupt request (flag) 2) .............. 95 pir3 (peripheral interrupt request (flag) 3) .............. 96 rcon (reset control)........................................ 44, 103 rcsta1 (eusart receive status and control)............................................... ....... 241 rcsta2 (ausart receive status and control)............................................... ....... 261 reserved .................................................................. 144 rtccal (rtcc calibration).................................... 142 rtccfg (rtcc configuration) ............................... 141 second (second value)......................................... 146 sspcon1 (mssp control 1, i 2 c mode) .................. 206 sspcon1 (mssp control 1, spi mode).................. 197 sspcon2 (mssp control 2, i 2 c master mode) ............................................. 207 sspcon2 (mssp control 2, i 2 c slave mode) ........ 208 sspstat (mssp status, i 2 c mode) ....................... 205 sspstat (mssp status, spi mode)....................... 196 status ..................................................................... 70 status/com (afe status/communications)......... 461 stkptr (stack pointer)............................................. 5 8 t0con (timer0 control) .......................................... 123 t1con (timer1 control) .......................................... 127 t2con (timer2 control) .......................................... 133 t3con (timer3 control) .......................................... 135 txsta1 (eusart transmit status and control)............................................... ....... 240 txsta2 (ausart transmit status and control)............................................... ....... 260 wdtcon (watchdog timer control) ....................... 326 weekday (weekday value) ................................... 145 year (year value)................................................... 144 reset.............................................................................. 364 reset ............................................................................ ...... 43 brown-out reset (bor)........................................... ... 43 configuration mismatch (cm) ..................................... 43 mclr reset, during power-managed modes ........... 43 mclr reset, normal operation................................. 43 power-on reset (por)............................................... 43 reset instruction ...................................................... 43 stack full reset.......................................................... 43 stack underflow reset ............................................ ... 43 watchdog timer (wdt) reset ................................... 43 resets........................................................................... .... 319 brown-out reset (bor)........................................... . 319 oscillator start-up timer (ost) ................................ 319 power-on reset (por)............................................. 319 power-up timer (pwrt) .......................................... 3 19 retfie ............................................................................. 3 65 retlw ............................................................................. 3 65 return........................................................................... 366 return address stack......................................................... 57 return stack pointer (stkptr) ......................................... 58 revision history...................................................... .......... 433 rlcf ................................................................................ 36 6 rlncf.............................................................................. 367 rrcf................................................................................ 367 rrncf .................... ......................................................... 368 rtcc alarm ........................................................................ 152 configuring ....................................................... 152 interrupt ............................................................ 154 mask settings ................................................... 153 alarm value registers (alrmval).......................... 147 control registers ...................................................... 141 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 473 pic18f87j72 family operation calibration......................................................... 152 clock source .................................................... 150 digit carry rules............................................... 150 general functionality ........................................ 151 leap year .................................................. ....... 151 register mapping.............................................. 151 alrmval ................................................. 152 rtcval.................................................... 151 safety window for register reads and writes.............................................. ... 151 write lock ......................................................... 151 register interface...................................................... 149 register maps........................................................... 155 reset......................................................................... 154 device ............................................................... 154 power-on reset (por)..................................... 154 sleep mode.................................................. ............. 154 value registers (rtcval) ....................................... 144 rtcen bit write ............................................................... 149 s sck................................................................................... 195 sdi .................................................................................... 195 sdo .................................................................................. 195 sec_idle mode................................................................. 40 sec_run mode ................................................................. 36 serial clock, sck ............................................................. 195 serial data in (sdi) ........................................................... 195 serial data out (sdo) .................................................... .. 195 serial peripheral interface. see spi mode. setf ................................................................................. 368 slave select (ss ).............................................................. 195 sleep .............................................................................. 369 software simulator (mplab sim)..................................... 387 special event trigger. see compare (ccp module). special features of the cpu ............................................ 319 spi mode (mssp) associated registers ................................................ 203 bus mode compatibility ......................................... ... 203 effects of a reset...................................................... 203 enabling spi i/o ....................................................... 199 master mode ............................................................. 200 operation .................................................................. 198 operation in power-managed modes ....................... 203 serial clock............................................................... 195 serial data in ............................................................ 195 serial data out ......................................................... 195 slave mode ............................................................... 201 slave select .............................................................. 195 slave select synchronization ................................... 201 spi clock .................................................................. 200 typical connection ................................................... 199 ss ..................................................................................... 195 sspov.............................................................................. 229 sspov status flag .......................................................... 229 sspstat register r/w bit.................................................. ............ 209, 211 stack full/underflow resets ...................................... ......... 59 subfsr ........................................................................... 380 subfwb........................................................................... 369 sublw ............................................................................. 370 subulnk ......................................................................... 380 subwf ............................................................................. 370 subwfb........................................................................... 371 swapf ............................................................................. 371 t table pointer operations (table)......................................... 80 table reads/table writes ......................................... ......... 59 tblrd .............................................................................. 372 tblwt ............................................................................. 373 timer0 .............................................................................. 123 associated registers........................................... ..... 125 clock source select (t0cs bit) ............................... 124 operation.................................................................. 124 overflow interrupt ..................................................... 125 prescaler .................................................................. 1 25 switching assignment ...................................... 125 prescaler assignment (psa bit)............................... 125 prescaler select (t0ps2:t0ps0 bits) ...................... 125 prescaler. see prescaler, timer0. reads and writes in 16-bit mode............................. 124 source edge select (t0se bit) ................................ 124 timer1 .............................................................................. 127 16-bit read/write mode ......................................... .. 129 associated registers........................................... ..... 131 interrupt .................................................................... 130 operation.................................................................. 128 oscillator........................................................... 127, 129 layout considerations...................................... 130 oscillator, as secondary clock................................... 27 resetting, using the ccp special event trigger.................................................... 130 tmr1h register....................................................... 127 tmr1l register ....................................................... 127 use as a clock source ............................................. 129 use as a real-time clock ........................................ 130 timer2 .............................................................................. 133 associated registers........................................... ..... 134 interrupt .................................................................... 134 operation.................................................................. 133 output....................................................................... 134 pr2 register ............................................................ 16 3 tmr2 to pr2 match interrupt................................... 163 timer3 .............................................................................. 135 16-bit read/write mode ......................................... .. 137 associated registers........................................... ..... 137 operation.................................................................. 136 oscillator........................................................... 135, 137 overflow interrupt ..................................................... 137 special event trigger (ccp) .................................... 137 tmr3h register....................................................... 135 tmr3l register ....................................................... 135 timing diagrams a/d conversion ........................................................ 42 2 acknowledge sequence ........................................... 232 afe continuous read.............................................. 452 afe data ready behavior ....................................... 455 afe data ready pulse........................................... .. 427 afe read/write (spi mode 0,0) .............................. 451 afe read/write (spi mode 1,1) .............................. 450 afe recommended configuration sequence.......... 453 afe serial input ............................................ ........... 427 afe serial output..................................................... 42 7 afe specific diagrams............................................. 428 asynchronous reception.................................. 251, 267 asynchronous transmission ............................ 249, 265 asynchronous transmission (back to back) .......................................... 249, 265 automatic baud rate calculation............................. 247 downloaded from: http:///
pic18f87j72 family ds39979a-page 474 preliminary ? 2010 microchip technology inc. auto-wake-up bit (wue) during normal operation.............................................. 252 auto-wake-up bit (wue) during sleep .................... 252 baud rate generator with clock arbitration ............. 226 brg overflow sequence .......................................... 247 brg reset due to sda arbitration during start condition .............................................. .... 235 bus collision during a repeated start condition (case 1) ............................................ 236 bus collision during a repeated start condition (case 2) ............................................ 236 bus collision during a start condition (scl = 0) .......................................................... 235 bus collision during a stop condition (case 1) ............................................................ 237 bus collision during a stop condition (case 2) ............................................................ 237 bus collision during start condition (sda only)........................................................ 234 bus collision for transmit and acknowledge............ 233 capture/compare/pwm............................................ 411 clko and i/o .............................................. ............. 408 clock synchronization .............................................. 219 clock/instruction cycle ............................................... 60 eusart/ausart synchronous receive (master/slave)................................................... 420 eusart/ausart synchronous transmission (master/slave)................................................... 420 example spi master mode (cke = 0) ...................... 412 example spi master mode (cke = 1) ...................... 413 example spi slave mode (cke = 0) ........................ 414 example spi slave mode (cke = 1) ........................ 415 external clock........................................................... 406 fail-safe clock monitor (fscm) ............................... 330 first start bit timing ................................................. 227 i 2 c bus data ............................................................. 417 i 2 c bus start/stop bits.............................................. 416 i 2 c master mode (7 or 10-bit transmission) ............ 230 i 2 c master mode (7-bit reception) ........................... 231 i 2 c slave mode (10-bit reception, sen = 0, admsk = 01001) .............................................. 216 i 2 c slave mode (10-bit reception, sen = 0) ........... 215 i 2 c slave mode (10-bit reception, sen = 1) ........... 221 i 2 c slave mode (10-bit transmission)...................... 217 i 2 c slave mode (7-bit reception, sen = 0, admsk = 01011) .............................................. 213 i 2 c slave mode (7-bit reception, sen = 0) ............. 212 i 2 c slave mode (7-bit reception, sen = 1) ............. 220 i 2 c slave mode (7-bit transmission)........................ 214 i 2 c slave mode general call address sequence (7 or 10-bit addressing mode) .......................... 222 i 2 c stop condition receive or transmit mode ......... 232 lcd interrupt in quarter duty cycle drive................ 190 lcd sleep entry/exit when slpen = 1 or cs1:cs0 = 00 ................................................... 191 mssp i 2 c bus data .................................................. 418 mssp i 2 c bus start/stop bits .................................. 418 pwm output ............................................................. 163 repeated start condition.......................................... 228 reset, watchdog timer (wdt), oscillator start-up timer (ost) and power-up timer (pwrt) ...... 409 send break character sequence ............................. 253 slave synchronization .............................................. 201 slow rise time (mclr tied to v dd , v dd rise > t pwrt ) ............................................. 47 spi mode (master mode).......................................... 200 spi mode (slave mode, cke = 0) ............................ 202 spi mode (slave mode, cke = 1) ............................ 202 synchronous reception (master mode, sren) ...................................................... 256, 270 synchronous transmission .............................. 254, 268 synchronous transmission (through txen) ....................................... 255, 269 time-out sequence on power-up (mclr not tied to v dd ), case 1 ....................... 46 time-out sequence on power-up (mclr not tied to v dd ), case 2 ....................... 47 time-out sequence on power-up (mclr tied to v dd , v dd rise t pwrt ) ............... 46 timer pulse generation.......................................... .. 154 timer0 and timer1 external clock ........................... 410 transition for entry to idle mode................................. 40 transition for entry to sec_run mode ..................... 37 transition for entry to sleep mode ............................. 39 transition for two-speed start-up (intrc to hspll)............................................ 328 transition for wake from idle to run mode............... 40 transition for wake from sleep (hspll) .................. 39 transition from rc_run mode to pri_run mode.................................................. 38 transition from sec_run mode to pri_run mode (hspll) ................................... 37 transition to rc_run mode ...................................... 38 type-a in 1/2 mux, 1/2 bias drive ........................... 180 type-a in 1/2 mux, 1/3 bias drive ........................... 182 type-a in 1/3 mux, 1/2 bias drive ........................... 184 type-a in 1/3 mux, 1/3 bias drive ........................... 186 type-a in 1/4 mux, 1/3 bias drive ........................... 188 type-a/type-b in static drive .................................. 179 type-b in 1/2 mux, 1/2 bias drive ........................... 181 type-b in 1/2 mux, 1/3 bias drive ........................... 183 type-b in 1/3 mux, 1/2 bias drive ........................... 185 type-b in 1/3 mux, 1/3 bias drive ........................... 187 type-b in 1/4 mux, 1/3 bias drive ........................... 189 timing diagrams and specifications a/d conversion requirements ................................. 422 capture/compare/pwm requirements .................... 411 clko and i/o requirements.................................... 408 eusart/ausart synchronous receive requirements ................................................ ... 420 eusart/ausart synchronous transmission requirements ................................................ ... 420 example spi mode requirements (master mode, cke = 0)................................... 412 example spi mode requirements (master mode, cke = 1)................................... 413 example spi mode requirements (slave mode, cke = 0)..................................... 414 example spi slave mode requirements (cke = 1).......................................................... 415 external clock requirements ................................... 406 i 2 c bus data requirements (slave mode) ............... 417 i 2 c bus start/stop bits requirements |(slave mode)..... 416 internal rc accuracy (intosc and intrc)............ 407 mssp i 2 c bus data requirements .......................... 419 mssp i 2 c bus start/stop bits requirements........... 418 pll clock ................................................................. 407 downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 475 pic18f87j72 family reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ......................................... 409 timer0 and timer1 external clock requirements ......................................... 410 top-of-stack access ........................................................... 57 tstfsz ............................................................................ 374 two-speed start-up ............................................. ..... 319, 328 two-word instructions example cases........................................................... 61 vv ddcore /v cap pin............................................................ 327 voltage reference specifications ..................................... 403 voltage regulator (on-chip) .......................................... .. 327 brown-out reset (bor) ............................................ 328 low-voltage detection (lvd) ................................... 327 operation in sleep mode .......................................... 328 power-up requirements ........................................... 328 w watchdog timer (wdt)............................................ 319, 325 associated registers........................................... ..... 326 control register........................................................ 32 5 during oscillator failure ........................................ ... 329 programming considerations ................................... 325 wcol ............................................... ........ 227, 228, 229, 232 wcol status flag.................................... 227, 228, 229, 232 www address ................................................................. 475 www, on-line support ..................... .................................. 7 x xorlw ............................................................................ 374 xorwf ............................................................................ 3 75 downloaded from: http:///
pic18f87j72 family ds39979a-page 476 preliminary ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 477 pic18f87j72 family the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following informa- tion: product support C data sheets and errata, appli- cation notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of micro- chip sales offices, distributors and factory repre- sentatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representa- tive or field application engineer (fae) for support. local sales offices are also available to help custom- ers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com downloaded from: http:///
pic18f87j72 family ds39979a-page 478 preliminary ? 2010 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microc hip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our document ation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this docume nt. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39979a pic18f87j72 family 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:///
? 2010 microchip technology inc. preliminary ds39979a-page 479 pic18f87j72 family product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device (1,2) pic18f86j72, pic18f86j72t pic18f87j72, pic18f87j72t temperature range i = -40 ? c to +85 ? c (industrial) package pt = tqfp (thin quad flatpack) pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18f87j72-i/pt 301 = industrial temperature, tqfp package, qtp pattern #301. b) pic18f87j72t-i/pt = tape and reel, industrial temperature, tqfp package. note 1: f = standard voltage range 2: t = in tape and reel downloaded from: http:///
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